JP3282212B2 - Digital signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing circuit for recording and reproducing digital data.

[0002]

2. Description of the Related Art k mounted on a cylindrical cylinder
In a digital signal recording / reproducing apparatus for recording / reproducing a digital signal as an oblique track on a tape by means of (k is an integer of 1 or more) heads, a recording signal for one track corresponds to the beginning of the block of digital data. It is formed by connecting a plurality of synchronization blocks each including a synchronization pattern shown, an ID indicating a position of a data as an information signal and indicating a block order, and data including an ID parity for detecting or correcting an error of the ID. And one or more signal regions. As an example of the related art, a case is considered where a recording signal for one track is composed of an audio area for an audio signal and a video area for a video signal. FIG. 13 shows a conventional track pattern. Here, the Audio area and the Video area are a synchronization pattern indicating the beginning of the block of digital data, an ID indicating the order of the block, an ID parity for detecting an ID error, and a pattern obtained by modulating video signal data or audio signal data. And a synchronous block unit consisting of
A gap is provided between each signal region. FIG.
FIG. 4 shows the configuration of the synchronization block. FIG. 14A shows a configuration of a synchronization block before modulation, which is composed of an ID indicating a position of a data as an information signal and indicating the order of the synchronization block, and an ID parity for detecting an ID error. FIG. 14B shows the configuration of a synchronous block obtained by modulating the pattern a and adding a synchronous pattern.

[0003] Audio area of recorded tape, Vi
When the reproduction process of the deo area is performed, a synchronous block is detected based on the detected digital data synchronous pattern detection, the ID value, and the ID parity, and it is determined whether a synchronous block exists.

The operation of the conventional example will be described below with reference to the drawings. FIG. 15 is a block diagram of a conventional digital signal processing circuit. 131 is the reproduced digital signal 15
A delay circuit 132 outputs a signal 152 obtained by delaying 1 by one synchronous block length, and a delay circuit 132 outputs a signal 153 obtained by delaying the delayed signal 152 by 1 synchronous block length. 13
Reference numeral 3 denotes a synchronization pattern detection circuit that detects a synchronization pattern in the reproduced digital signal 151 and outputs a synchronization pattern detection pulse 154. Reference numeral 134 denotes a synchronization pattern that detects a synchronization pattern in the delay signal 152 and outputs a synchronization pattern detection pulse 155. A detection circuit 135 detects a synchronization pattern in the delay signal 153 and outputs a synchronization pattern detection pulse 156. A synchronization pattern detection circuit 136 detects an ID in the reproduction digital signal 151 and detects the ID 157.
And an ID detection circuit 137 that detects an error based on the detected ID 157 and ID parity and outputs an ID error flag 158. The ID detection circuit 137 outputs the ID 159 detected by detecting the ID in the delay signal 152, and An error is detected by the ID 159 and the ID parity, and the ID error flag 16 is detected.
The ID detection circuit 138 that outputs 0 outputs the ID 161 detected by detecting the ID in the delay signal 153, detects an error based on the detected ID 161 and the ID parity, and outputs the ID 161.
This is an ID detection circuit that outputs a D error flag 162.
139, when the window 165 is true, the synchronous pattern detection pulses 154, 155, 156 and the detection ID 157,
159, 161 and the ID error flag 158, 160, 1
62, it is determined whether or not a synchronization block exists in the output data of the delay circuit 152, a synchronization block detection pulse 163 is generated, and the estimated ID of the synchronization block is determined.
Is output as a modification ID 164. 140 is a window 1 with a width of 1 every synchronous block length interval when a synchronous block detection pulse is output.
This is a mask circuit that always sets the window 165 to true if the synchronous block detection pulse is not found three consecutive times when the window 65 is set to true when the window 165 is true. 1
41 is a synchronous block detection pulse 163 and a correction ID 16
4 demodulates the synchronous block in the data 152,
In addition, the erroneous ID is corrected, and the demodulated data 167 and the synchronous block head pulse 166 indicating the head of the synchronous block are corrected.
And a demodulation circuit that outputs

[0005] The synchronous block detecting circuit 139 detects when one or more synchronous pattern detection pulses are detected, there are two or more IDs for which no ID error flag is set, and the continuity of the IDs is satisfied. And the delay circuit 131
It is determined that a synchronous block exists in the output 152, and a synchronous block detection pulse is generated. In addition, the modification ID 13
9 is created from an ID with no ID error flag set.

FIGS. 16 and 17 show an operation example of a conventional digital signal processing circuit. With the above-described circuit configuration, three consecutive digital signals are output from the reproduced digital data at a synchronous block length interval.
The synchronization pattern, ID and ID parity are detected from the location, and it is determined whether or not a synchronization block exists in the data extracted from the center among the data extracted from the three locations in the reproduced digital data.

First, the operation of detecting a synchronous block will be described with reference to FIG. By the operation of the synchronous block detection circuit 139 alone, the missing synchronous block is corrected as shown in FIG. 16A, and the false synchronous block whose synchronization is not satisfied as shown in FIG. 16B. To eliminate.

[0008] Further, the synchronous block detecting circuit 139 and the mask circuit 140 eliminate a false synchronous block generated in a synchronous block cycle as shown in FIG.
Further, as shown by d in FIG. 16, even if two or more synchronous blocks are not detected consecutively, it is assumed that a synchronous block exists, and the missing synchronous block is corrected.

Next, FIG. 17 shows a case where a malfunction occurs. As shown by e in FIG. 17, even if the values of the three IDs are normally detected, if there is an error in the ID parity portion, I
The D detection circuits 136, 137, and 138 consider that there is an error in the ID, and the synchronization block detection circuit 139 does not determine that a synchronization block exists.

As shown by f in FIG. 17, when the period of the synchronization pattern in the reproduced digital data changes due to a malfunction of the reproduction clock or the like, an erroneous synchronization block is output at a portion g in FIG. Resulting in. The above operation is due to the influence of the pull-in time by the window in order to take measures against the loss of the synchronous block. Also, as shown by h in FIG. 17, although the synchronous block detection circuit detects ID number = 8, only the middle synchronous block among the three synchronous blocks extracted from the reproduced digital data is used. Is not determined to be a synchronous block. That is, the information is not effectively used.

[0011]

However, in the conventional digital signal processing circuit, when the period of the synchronization pattern in the reproduced digital data changes due to a malfunction of the reproduction clock, the synchronization cannot be detected normally. In this case, an erroneous synchronization block is detected over three synchronization blocks. Also, since only the central synchronization block is used among the three synchronization blocks extracted from the reproduced digital data, information is not effectively used.

In the state before the mask operation is started by the window, if only the ID parity is erroneous,
Even if the ID itself is normally detected, it is not regarded as a synchronous block.

In order to solve the above-mentioned problems, the present invention has the effects of improving the accuracy of correcting missing sync patterns and ID errors and eliminating false sync blocks, and improving the accuracy of reproduced digital data due to malfunctions of the reproduced clock. A digital signal processing circuit capable of normally detecting a synchronous block even when the period of the synchronous pattern changes.

[0014]

In order to solve the above-mentioned problems, a digital signal processing circuit according to a first aspect of the present invention uses a k-number of heads mounted on a cylindrical cylinder as a diagonal track on a tape. It is composed of a recorded synchronization pattern indicating the beginning of the block of digital data, data indicating the position of the data as an information signal and indicating the order of the block, and data including an ID parity for detecting or correcting an ID error. A digital signal processing circuit of a digital signal reproducing apparatus for reproducing data of one or more signal areas formed by connecting a plurality of synchronous blocks, wherein two or more x points separated by a synchronous block length interval in reproduced digital data The synchronization pattern is detected from the width of m bits before and n bits after the position of the center, and the position of x places separated by the synchronization block length interval is detected. The ID and the ID parity are detected from the width of the preceding m bits and the next n bits centering on x positions separated by the synchronous block length interval corresponding to the position of the synchronization pattern existing at the width of the preceding m bits and the n bits before the center. , X synchronization pattern detection positions and x synchronization pattern detection positions indicating where the synchronization pattern exists in the width of (m + n), and x detection IDs and positions of the width of (m + n) Is composed of a synchronous block detecting means for detecting y synchronous blocks equal to or less than x, based on x ID detection positions indicating whether a detection ID exists and x ID parities.

[0015] Alternatively, the center of the reproduction digital data may be set at two or more x positions separated by a synchronization block length interval.
The synchronization pattern is detected from the width of n bits after the bit, and x
The position of a synchronous block is predicted by detecting the number of synchronous patterns and x synchronous pattern detection positions indicating at which position in the (m + n) width the synchronous pattern exists, and corresponding to the predicted position of the synchronous block. ID and ID parity are detected from x positions separated by a synchronous block length interval, and x
Synchronization pattern detection and the detection position of the synchronization pattern, x
It is configured by a synchronous block detecting means for detecting y synchronous blocks equal to or less than x using the detected IDs and the x ID parities.

In order to solve the above-mentioned problems, a digital signal processing circuit according to a second aspect of the present invention is a digital signal processing circuit comprising: a k-head mounted on a cylindrical cylinder; A plurality of synchronous blocks consisting of a synchronous pattern indicating the beginning of the digital data and an ID indicating the position of the data as an information signal and indicating an order of the block and data including an ID parity for detecting or correcting an ID error are connected. A digital signal processing circuit of a digital signal reproducing apparatus for reproducing data of one or more signal regions, wherein x is detected from two or more x positions separated by a synchronization block length interval in the reproduced digital data. By detecting the synchronization patterns, x detection IDs and x ID parities, y synchronization blocks equal to or less than x can be obtained. In determining whether a resident, x number of detected ID and x pieces all ID by the ID parity
Even if an error is detected, if the continuity of the z or more detection IDs of 2 or more and x or less is satisfied, the synchronous block detecting means is configured to determine that y synchronous blocks have been detected.

[0017]

According to the first aspect of the present invention, the information of the synchronous block is detected from the width of the preceding m bits and the subsequent n bits centering on the positions of two or more x positions separated by the synchronous block length interval in the reproduced digital data. Therefore, there is an opportunity to detect the position where the same synchronous block exists at least x times and determine the position as the synchronous block x times. Further, since it has a width of (m + n) bits, it is possible to detect even a period shift of the synchronous block.

By the above operation, the synchronization pattern is missing or the ID
The effect of improving the accuracy of error correction and the elimination of false synchronous blocks, and the effect of being able to detect synchronous blocks normally even if the period of the synchronous pattern in the reproduced digital data changes due to a malfunction of the reproduction clock. Can be obtained.

Next, the second invention has the above-described structure,
Even when an error has occurred in the parity portion of all IDs, the ID itself is normal, so that synchronous block detection can be performed using the continuity of IDs. Thus, it is possible to prevent the detection accuracy from deteriorating due to an ID detection error. This is very effective especially at the initial stage when the protection circuit of the synchronous block has not been pulled in yet.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

K mounted on a cylindrical cylinder
In a digital signal recording / reproducing apparatus for recording / reproducing a digital signal as an oblique track on a tape by means of (k is an integer of 1 or more) heads, a recording signal for one track corresponds to the beginning of the block of digital data. 1 is formed by linking a plurality of synchronization blocks each including a synchronization pattern shown, data indicating the position of the data as an information signal and indicating the block order, and data including an ID parity for detecting or correcting an ID error. And at least two signal regions. As an example of a recording signal for explaining the present invention, a case is considered in which a recording signal for one track is composed of an audio signal Audio area and a video signal Video area. The audio area and the video area constituting the track pattern are demodulated with a synchronization pattern indicating the beginning of the block of digital data, an ID indicating the order of the block, an ID parity for detecting an ID error, and video signal data or audio signal data. It is configured in units of synchronous blocks composed of the following patterns. A gap is provided between each signal region.

FIG. 1 is a diagram showing an example of the configuration of synchronous block data. A 16-bit ID and an 8-bit ID parity for detecting an ID error are added to the 1088-bit data shown in FIG. 1A, as shown in FIG. 1B. The ID indicates the position of the data of the synchronous block as an information signal. Further, as shown in c, 1 of b
By adding a 7-bit synchronization pattern and adding 1-bit modulation data to every 24 bits of the data string, 11
A synchronous block having a length of 75 bits is configured. The purpose of such a modulation method is to add, for example, one bit of modulation data to every 24 bits of data so that the length (run length) of consecutive 1's or 0's on the recording pattern is two.
It can be limited to 4 bits or less, and the operation accuracy of a clock generation circuit that generates a reproduction clock based on a change point of reproduction data during reproduction is improved.

FIG. 2 is a block diagram of a digital signal processing circuit according to the first embodiment of the present invention. Reference numeral 10 denotes a serial / parallel signal which outputs data 41 obtained by rearranging the reproduced digital signal 40 sequentially input in 1-bit units in 5-bit units, and setting the operation unit of the circuit to 1/5 from the operating frequency of the reproduced digital data. It is a conversion circuit. 11 is serial /
A delay circuit that outputs a signal 42 obtained by delaying the output 41 of the parallel conversion circuit by one synchronous block length, and 12 is a delay signal 42
Is a delay circuit that outputs a signal 43 delayed by one synchronous block. The delay circuit 12 delays the synchronous block of 1175 bits, but since the data is parallel in 5 bits, it is a circuit for delaying the data by 235 circuit operation units.

Reference numeral 13 denotes a synchronous pattern detection pulse 45 for detecting a synchronous pattern in the output 41 of the serial / parallel conversion circuit and a synchronous pattern detection position indicating the start position of the synchronous pattern in the 5-bit data for each circuit operation unit. 46
A sync pattern detection circuit 14 for detecting a sync pattern in the delay signal 42 for each circuit operation unit and a sync pattern detection pulse 47 and a sync pattern detection indicating the start position of the sync pattern in the 5-bit data. A synchronization pattern detection circuit 15 outputs a position 48 and a synchronization pattern detection circuit 49 detects a synchronization pattern in the delay signal 43 for each circuit operation unit, and indicates a synchronization pattern detection pulse 49 and a start position of the synchronization pattern in the 5-bit data. This is a synchronous pattern detection circuit that outputs a pattern detection position 50. Since the synchronization pattern detection position is the head position of the synchronization pattern in the 5-bit data, there are five states.

Reference numeral 16 denotes a protection synchronization pattern detection position 58 which indicates the head position of the synchronization pattern in the 5-bit data and corresponds to the protection synchronization pattern detection position from the output 41 of the serial / parallel conversion circuit for each circuit operation unit. An ID detection circuit 17 detects an ID to be output and outputs the detected ID 51, and detects an error based on the detected ID 51 and ID parity and outputs an ID error flag 52. Reference numeral 17 denotes a 5-bit data for each circuit operation unit. According to the protection synchronization pattern detection position 58 indicating the head position of the synchronization pattern of the above, the ID corresponding to the protection synchronization pattern detection position is detected from the output 42 of the delay circuit, and the detected ID 53 is output.
An ID detection circuit for detecting an error based on the detected ID 53 and ID parity and outputting an ID error flag 54;
Detects an ID corresponding to the protection synchronization pattern detection position from the output 43 of the delay circuit according to the protection synchronization pattern detection position 58 indicating the head position of the synchronization pattern in the 5-bit data for each circuit operation unit. An ID detection circuit that outputs the detected ID 55, detects an error based on the detected ID 55 and ID parity, and outputs an ID error flag 56.

Reference numeral 19 denotes a synchronization pattern detection pulse 45, 47, 49, a synchronization pattern detection position 46, 48, 50, and a protection synchronization block detection position 61 for each circuit operation unit.
And the expected synchronization pattern detection pulse 63, the position where the synchronization pattern exists is determined, and the protection synchronization pattern detection pulse 57, the protection synchronization pattern detection position 58 indicating the head position of the synchronization pattern in the 5-bit data, and the synchronization pattern A synchronous pattern detection and protection circuit that outputs a synchronous pattern detection state 59 indicating which of the three existing locations the synchronous pattern exists.

20 is a protection synchronization pattern detection pulse 57
, Protection synchronization pattern detection position 58, synchronization pattern detection state 59, detection IDs 51, 53, 55, ID error flags 52, 54, 55, and expected synchronization pattern detection pulse 6.
3 and the window 65, it is determined whether or not a synchronous block exists in the signals 41, 42, and 43 obtained by extracting the reproduced digital signal at the synchronous block length interval. If it is determined that three synchronous blocks exist, the delay is determined. Circuit output 4
In step 3, the synchronous block detection pulse 60 is output at the timing when the head of the synchronous block is output, and the protection synchronous block detection position 61 indicating the position of the head of the synchronous block in the 5-bit data is kept held until the next update. This is a synchronous block detection circuit that outputs a synchronous block from the delay circuit 43 and outputs an ID corresponding to the synchronous block as a modified ID 62. The protected synchronous block detection position is the first position of the synchronous block in the 5-bit data, that is, the first position of the synchronous pattern in the synchronous block, and therefore exists in five states, and has the same value as the corresponding synchronous pattern detection position.

Reference numeral 21 denotes a counter which is reset by a synchronous block detection pulse 60 and counts up in units of circuit operation. The counter detects an expected synchronous pattern detection pulse 63 at a timing when a synchronous pattern is expected to be detected thereafter. And outputs a protection synchronization block detection pulse 64 indicating the timing at which the head of the three synchronization blocks determined by the synchronization block detection circuit 20 as having a synchronization block to appear at the output 43 of the delay circuit. When this occurs, the mask circuit sets the window 65 to false, makes the synchronous block detection circuit 20 true twice only with a timing block that is expected to detect a synchronous block thereafter, and then always keeps true.

Reference numeral 22 denotes a protection synchronization block detection pulse 64
And the protection synchronization block detection position 61, the head of the detected synchronization block in the output 43 of the delay circuit is recognized,
The synchronous block is demodulated, and an incorrect I
A demodulation circuit that corrects D and outputs a demodulated data 66 and a synchronous block head pulse 67 indicating the head of a synchronous block of the demodulated data 66. In the demodulation operation, as shown in FIG. 1C, since 1-bit dummy is inserted in 24 bits of data, the dummy data is removed and rearranged.

The synchronous pattern detection and protection circuit 19 uses the synchronous pattern detection pulses 45, 47, and 49, the synchronous pattern detection positions 46, 48, and 50, the expected synchronous pattern detection pulse 63, and the protection synchronous block detection position 61 as follows. The position where the synchronization pattern exists is determined under the condition having the priority shown in Table 1), and the protection synchronization pattern detection pulse 57 and the protection synchronization pattern detection position 58 indicating the head position of the synchronization pattern in the 5-bit data are determined. And a synchronization pattern detection state 59 indicating which of the three locations where the synchronization pattern exists the synchronization pattern exists.

[0031]

[Table 1]

In Table 1, DET0 is a synchronization pattern detection pulse 45, DET1 is a synchronization pattern detection pulse 47, DET2 is a synchronization pattern detection pulse 49, and PHA
SE0 is a synchronization pattern detection position 46, PHASE1 is a synchronization pattern detection position 48, PHASE2 is a synchronization pattern detection position 50, old_PHASE is a protection synchronization block detection position 61, S is an expected synchronization pattern detection pulse 63,
DET is a protection synchronization pattern detection pulse 57, PHASE
Indicates a protection synchronization pattern detection position 58, and STATE indicates a synchronization pattern detection state 59. 1 if true and 0 if false.

As shown in Table 1, the priority order for determining the position in the 5-bit parallel data at which the beginning of the synchronous block is located is determined by the delay circuit as the number of detected synchronous patterns increases. Of the three locations from which the reproduced data is extracted, the location closer to the final stage is higher as the synchronization pattern is detected at a position predicted from the position where the previous synchronization block was detected. The position of the expected synchronization pattern is a synchronization pattern in which the expected synchronization pattern detection pulse 63 is true and has the same synchronization pattern detection position as the protection synchronization block detection position 61.

FIGS. 3 and 4 show the independent operation timing of the synchronous pattern detection and protection circuit. Here, it is assumed that the synchronization pattern detection position has a value in five states from 0 to 4.

The synchronization pattern detection state 59 is expressed by 3 bits, the LSB is the synchronization pattern in the output 41 of the serial / parallel conversion circuit, the second bit is the synchronization pattern in the output 42 of the delay circuit, and the MSB is the delay. Circuit output 4
3 indicates the state of the synchronization pattern, and is 1 if a synchronization pattern exists at that position, and 0 if not.

As shown in FIG. 3, even if an error occurs in the reproduced signal and the synchronization pattern cannot be detected, the position of the detected synchronization pattern and the number of the synchronization patterns can be output to the synchronization block detection circuit 20. .

Next, FIG. 4 shows a case where the period of the synchronous block changes in the middle. As shown by k in FIG. 4, when the cycle is shifted by only a few bits and there is no change in the circuit operation unit, that is, when the expected synchronization pattern detection pulse 63 is true, the values of the synchronization pattern detection positions 46, 48, and 50 are set. Are different, the one whose synchronization pattern is detected at the position expected at the output 43 of the delay circuit with the priority shown in (Table 1) is adopted.

Further, as shown in FIG. 4m, even when the expected synchronization pattern detection pulse 63 is greatly shifted from the true position and the expected synchronization pattern detection pulse 63 is shifted from the true position, the synchronization pattern is detected.
It is possible to detect a synchronization pattern.

The synchronization pattern detection and protection circuit 19 having such a priority, the synchronization block detection circuit 20 and the mask circuit 21, as described later, cause synchronization in the reproduction digital data due to a malfunction of the reproduction clock or the like. Even when the period of the pattern changes, a synchronous block can be normally detected.

The synchronous block detection circuit 20 has three consecutive locations (data 41, 42, 43) at the synchronous block length interval.
Is a circuit for determining whether or not there is a synchronous block.

When it is determined that a synchronous block exists,
A representative protection ID value 81 and three pieces of ID correction information 82, 83, and 84 indicating that the ID is to be corrected in an erroneous portion among the detection IDs 51, 53, and 55 are stored. As the representative protection ID 81, of the three IDs, the I that the synchronous block detected from the output 43 of the delay circuit should have
Holds D value.

If the window 60 is true and the protection synchronization pattern exists at the same position as the position predicted from the position where the previous synchronization block was detected, the previous representative protection ID value 81 and three pieces of ID correction information 82 , 83, 84, the synchronization pattern detection protection pulse 57, and the synchronization pattern detection state 5
9 and three detection IDs 51, 53, 55 and three ID error flags 52, 54, 56, it is determined whether or not a synchronous block exists, and if the window 60 is true and
When the synchronization pattern exists at a position different from the position predicted from the position where the previous synchronization block was detected, the synchronization pattern detection protection pulse 57, the synchronization pattern detection state 59, the three detection IDs 51, 53, 55, and the three IDs Based on the error flags 52, 54, and 56, it is determined whether a synchronous block exists.

The case where the protection synchronization pattern exists at a position predicted from the position where the previous synchronization block was detected means that the expected synchronization pattern detection pulse 63 is true, and the protection synchronization block detection position 61 and the protection synchronization pattern detection position 58 Are equal.

If it is determined that the synchronous block does not exist at the same position as the position predicted from the position where the previous synchronous block was detected, the representative protection ID is set as the ID value of the next synchronous block predicted from the current protection ID, The correction information of the three IDs is shifted backward. That is, the value of the ID correction information 83 is substituted for the ID correction information 84, and the value of the ID correction information 82 is substituted for the ID correction information 83.

By the above operation, the information of the previously detected synchronous block can be held, and the determination of the synchronous block at the position expected from the previously detected synchronous block is performed by using the information of the previously detected synchronous block. Synchronous blocks can be detected.

The following case is considered as an example of the synchronous operation.

[0047]

[Table 2]

When the protection synchronization pattern exists at a position predicted from the position where the last synchronization block was detected, as shown in (Table 2), one or more synchronization patterns are detected by the synchronization pattern detection state 59, and If two or more error-free IDs are determined by the ID error flags 52, 54, and 56 and the relationship among the error-free IDs among the detection IDs 51, 53, and 55 is satisfied, the IDs are continuously generated at the synchronization block length interval. It is determined that synchronous blocks exist in the three places (data 41, 42, 43).

[0049]

[Table 3]

As shown in (Table 3), two or more synchronization patterns are detected by the synchronization pattern detection state 59, and one ID having no error is detected by the ID error flags 52, 54, and 56. , Detection IDs 51, 53, 55
If the relationship between the error-free ID and the representative protection ID is satisfied, it is determined that there are synchronous blocks at three consecutive locations (data 41, 42, 43) at the synchronous block length interval.

When the protection synchronization pattern exists at a position different from the position predicted from the position where the previous synchronization block was detected, one or more synchronization patterns are detected by the synchronization pattern detection state 59 as shown in (Table 2). If there are two or more error-free IDs due to the ID error flags 52, 54, 56 and the relationship between the error-free IDs among the detected IDs 51, 53, 55 is satisfied, the synchronization block length Three consecutive locations (data 41, 42,
43) It is determined that a synchronous block exists.

In Table 2 and Table 3, STATE
Indicates a synchronous pattern detection state 59, CK0 indicates an ID error flag 52, CK1 indicates an ID error flag 54, and CK2 indicates an ID error.
The error flag 56, ID0 is the detection ID 51, ID1 is the detection ID 53, ID2 is the detection ID 55, COR0 is the ID correction information 82, COR1 is the ID correction information 83, COR2 is the ID correction information 84, and H_ID2 is the representative protection ID 81.
It is. Here, it is assumed that the value of the ID simply increases by one.

FIG. 5 shows an example of independent operation of the synchronous block detection circuit. However, in order to simplify the operation, the protected synchronization block detection position 61 and the protection synchronization pattern detection position 58 are assumed to be the same, and when the expected synchronization pattern detection pulse 63 is true, the position at which the previous synchronization block was detected is detected. It is assumed that a protection synchronization pattern exists at a more predicted position. It is also assumed that the value of the synchronization pattern detection state 59 is one of 3, 5, 6, and 7. It is also assumed that the window is always true.

Synchronous blocks can be detected by correcting a single ID detection error as shown in FIG. 5A or a consecutive ID detection error as shown in FIG. 5D. Also, a false synchronous block that does not satisfy the periodicity as shown in FIG. 5B can be eliminated. Here, the numbers shown in [] are the numbers of the determination conditions shown in (Table 2) and (Table 3). As can be seen from this operation, the synchronous block detection circuit 20 operates satisfactorily without the mask by the window 65.

In the above examples (Table 2) and (Table 3), the ID correction information 82, 83, 84 is not used for the determination condition, but the synchronization is achieved by using the ID correction information 82, 83, 84 for the determination condition. Block detection accuracy can be improved.

Next, a synchronous pattern detection protection circuit 19,
The operation of the synchronous block detection circuit 20 and the mask circuit 21 will be described.

In the mask circuit 21, when the synchronous block detection pulse 60 is generated, the window 65 is false.
It is assumed that the synchronous block detection circuit 20 sets the value to true twice only at the timing at which the synchronous block is expected to be detected thereafter, and then sets the value to always true after one synchronous block length.

FIG. 6 shows an operation example. As shown in FIG. 6C, a false synchronous block generated in the synchronous block cycle is eliminated by the mask operation by the window 65.

As shown by f1 in FIG. 6, when the cycle is shifted by only a few bits and there is no change in the circuit operation unit, that is, when the expected synchronization pattern detection pulse 63 is true, the synchronization pattern detection position 46, Consider the case where the values of 48 and 50 are different.

In FIG. 6E, the ID cannot be detected normally due to the influence of the disorder of the periodicity of the synchronous block length.

The synchronization pattern detection and protection circuit 19 detects the synchronization pattern in the priority order shown in (Table 1), giving priority to the detection of the synchronization pattern at the position expected by the output 43 of the delay circuit. I do. Therefore, the detection of the synchronization block existing in the output 43 of the delay circuit can be normally detected without being affected by the disorder of the periodicity of the synchronization block length.

Further, as shown by f2 in FIG. 7, a case is considered where the synchronization pattern is detected at a place where the period of the synchronization block is largely shifted and the expected synchronization pattern detection pulse 63 is shifted from the true position.

The above-mentioned period shift is a case where the period of the synchronous block becomes large. In this case, due to the operation of the window 65, only the synchronous block indicated by Error in FIG. Therefore, the influence of the period shift of the synchronous block can be reduced as compared with the conventional example.

As described above, the synchronous pattern is detected from the 5-bit width at three positions separated by the synchronous block length interval in the reproduced digital data, and the three synchronous patterns are detected. The position of the synchronization block is predicted based on three synchronization pattern detection positions indicating whether or not a synchronization pattern exists at the position, and I is determined from three positions separated by a synchronization block length interval corresponding to the predicted position of the synchronization block.
D and ID parity are detected, three synchronous pattern detections, synchronous pattern detection positions, three detection IDs and three I
The above operation can be realized by detecting three synchronization blocks with D parity.

Next, FIG. 8 shows a circuit according to another embodiment of the first invention in order to prevent a malfunction due to the above-mentioned synchronous block cycle deviation. This circuit differs from the circuit of FIG. 2 in a synchronous block detection circuit 120, a mask circuit 121, and a demodulation circuit 122.

The synchronous block detecting circuit 120 operates almost the same as the synchronous block detecting circuit 20 of the previous embodiment, except that the synchronous block detecting circuit 120 determines that a synchronous block exists and outputs a synchronous block detecting pulse 60. When neither a synchronization pattern nor an ID is detected at the output 41 of the / parallel conversion circuit, a last 2 synchronization block pulse 85 indicating the possibility that a synchronization block does not exist is output.

The mask circuit 121 operates in the same manner as the mask circuit 21 when the last 2 synchronization block pulse 85 is false.

If the synchronous block detection pulse 60 and the last 2 synchronous block pulse 85 are simultaneously true, the window 65
Only the following operation different from the mask circuit 21 is performed. When the synchronous block detection pulse 60 is generated, the window 65 is set to false, and is set to true once only at the timing when the synchronous block is expected to be subsequently detected by the synchronous block detection circuit 120. Thereafter, it is always true after one synchronous block length. And

FIG. 9 shows the operation timing. If the above operation causes a shift in the period of the synchronous block as shown by f2 in FIG. 9, an erroneous synchronous block is detected in q in FIG. In addition to the above, when the same ID is detected in a synchronous block occurring at a very close cycle, the function of adopting the synchronous block detected later in time is added to increase the cycle of the synchronous block. The synchronization block can be normally detected without being affected by the occurrence of the synchronization block.

With this operation, while outputting three synchronous blocks, there is a possibility that there is no last synchronous block appearing from the output 43 of the delay circuit among the three synchronous blocks. A new synchronization block is searched for by setting the value to true from the timing at which appears. If a synchronization block is found, the synchronization block output last is invalidated and a newly detected synchronization block is adopted.

As a result, the synchronization pattern is detected from the 5-bit width at three positions separated by the synchronization block length interval in the reproduced digital data, the three synchronization patterns are detected, and the synchronization pattern is detected. The position of the synchronous block is predicted based on three synchronous pattern detection positions indicating which position the synchronous pattern exists, and the ID and the ID are determined from three positions separated by a synchronous block length interval corresponding to the predicted synchronous block position. ID parity is detected, three synchronous pattern detections, three synchronous pattern detection positions, and three detection I
Based on D and three ID parities, two or three synchronous blocks are detected.

Next, in the second embodiment of the first invention, as shown at f3 in FIG. 10, the synchronization pattern is shifted when the expected synchronization pattern detection pulse 63 is shifted from the true position with a large period shift. Consider the case where it is detected.

The period shift occurs when the period of the synchronous block is reduced. In this case, a synchronous block indicated by Error in FIG. 10 is erroneous.

To prevent this, the mask circuit 121 is used.
In the above, the problem is solved by slightly advancing the timing at which the window is always true. FIG. 11 shows the operation timing. In the example of FIG. 11, the timing of making the window always true is advanced by two circuit operation units. By this operation, even if the periodicity of the synchronous block is shifted in the direction in which the period of the synchronous block is reduced, the operation is normal.

According to the above circuit configuration, since the information of the synchronous block is detected from the 5-bit width at three positions separated by the synchronous block length interval in the reproduced digital data, the position where the same synchronous block exists is determined by at least three positions. Times, there is an opportunity to be determined as a synchronous block three times. Further, since it has a width of 5 bits, it is possible to detect even a period shift of the synchronous block.

Therefore, the effect of improving the accuracy of correcting a missing sync pattern or an ID error and eliminating false sync blocks, and improving the accuracy of the cycle of the sync pattern in the reproduced digital data due to a malfunction of the reproduced clock, etc. An effect that a synchronous block can be normally detected can be obtained.

In this embodiment, one for every 24 bits of data
Although this is a modulation method for adding bit modulation data, it is not necessary to separately limit to this method, and it is effective for all modulation methods.

The synchronous block length is 1175 bits, which is a multiple of 5, and is a serial / parallel conversion circuit, so that the data is 5-bit parallel data. However, the number of bits of the parallel data need not be limited separately. However, from the viewpoint of the circuit configuration, the number of bits that can completely divide the synchronization block length is preferable.

In this embodiment, the synchronous block is detected by the two delay circuits from the output of the serial / parallel conversion circuit and the output of the two delay circuits, that is, a total of three signals. Generally, x-1 (x is an integer of 2 or more)
The same effect can be obtained by detecting a synchronous block from the outputs of the serial / parallel conversion circuit and the outputs of the (x-1) delay circuits by x delay circuits. .

The width of the data extracted from the x location is set to 5 bits of the parallel data by utilizing the fact that the output of the serial / parallel conversion circuit becomes 5-bit parallel data. I just need.

In the ID detection circuit, an error is detected by the ID parity. However, if an error correction function is added to the ID detection circuit by the ID parity, an ID error flag may be generated for the uncorrectable ID. Good.

Also, with the above configuration using the delay circuit,
Although the above operation is realized, even if the above configuration is not used, two or more x's separated by a synchronization block length in the reproduced digital data can be used.
The same effect can be obtained by extracting the information of the synchronization block from the width of m bits before and n bits after the center of the position of the location.

Further, in the above configuration, the position of the synchronization block is estimated based on the synchronization pattern detected from the x places, and thereafter, the information of the x synchronization patterns, the x IDs detected from the estimated synchronization block position, and the x synchronization blocks are estimated. The synchronous block is detected by the information of the ID parity. The synchronous pattern and the ID are detected from x places, and the synchronous block is detected by the information of the x synchronous patterns, the information of the x IDs, and the information of the ID parity. Even if it is detected, the same effect can be obtained.

That is, the center of the reproduction digital data is set at the position of two or more x positions separated by the synchronization block length interval.
A synchronization pattern is detected from the width of n bits after the bit, and the synchronization block length interval corresponding to the position of the synchronization pattern existing at a width of n bits after the preceding m bits is centered on the position of x places separated by the synchronization block length interval. ID and ID parity are detected from the width of the preceding m bits and the subsequent n bits centering on the x positions, and the x synchronization patterns are detected and the (m +
x synchronization pattern detection positions indicating where the synchronization pattern exists in the width of n), x detection IDs, and where the detection ID exists in the width of (m + n). The same effect can be obtained by detecting y synchronization blocks equal to or less than x based on the x ID detection positions and x ID parities shown.

Next, a second embodiment of the present invention will be described.
As a block diagram of the digital signal processing circuit of the embodiment,
FIG. 2 of the first embodiment of the first invention is used.

[0086]

[Table 4]

The difference from the operation is that the following synchronous block determination conditions are added to the synchronous block detection circuit 20. As shown in (Table 4), the synchronization pattern detection state 59
, One or more synchronization patterns are detected, and
If an error is detected in all three ID error flags 52, 54, and 56 and the relationship among the three detected IDs 51, 53, and 55 is satisfied, three consecutive locations (data 41, 42, 43).

In Table 4, STATE indicates a synchronous pattern detection state 59, CK0 indicates an ID error flag 52, C
K1 is an ID error flag 54, CK2 is an ID error flag 56, ID0 is a detection ID 51, and ID1 is a detection ID 5
3, ID2 is detection ID55, COR0 is ID correction information 8
2, COR1 is ID correction information 83, COR2 is ID correction information 84, and H_ID2 is a representative protection ID 81.

As a result, as shown in FIG.
Even when an error occurs in the parity portion of one ID, the ID itself is normal, so that the synchronous block can be detected by utilizing the continuity of the ID. Thus, it is possible to prevent the detection accuracy from deteriorating due to an ID detection error. In FIG. 12, the numbers in [] indicate the numbers of the conditions of (Tables 2, 3, and 4). Since the synchronous block cannot be detected using the representative protection ID 81 and the ID correction information 82, 83, 84 at the initial stage when the protection circuit of the synchronous block has not been pulled in yet, the detection accuracy of the synchronous block is improved by the above circuit configuration. Can be.

In this embodiment, one for every 24 bits of data
Although this is a modulation method for adding bit modulation data, it is not necessary to separately limit to this method, and it is effective for all modulation methods.

In this embodiment, the synchronous block is detected by the two delay circuits from a total of three signals of the output of the serial / parallel conversion circuit and the output of the two delay circuits. Generally, x-1 (x is an integer of 2 or more)
The same effect can be obtained by detecting a synchronous block from the outputs of the serial / parallel conversion circuit and the outputs of the (x-1) delay circuits by x delay circuits. .

In the ID detection circuit, an error is detected by the ID parity. However, if an error correction function is added to the ID detection circuit by the ID parity, an ID error flag may be generated for an ID that cannot be corrected. Good.

Also, with the above configuration using the delay circuit,
Although the above operation is realized, the same effect can be obtained without using the above configuration by extracting information of the synchronous block from two or more x positions separated by the synchronous block length interval in the reproduced digital data.

[0094]

According to the first aspect of the present invention, the information of the synchronous block is obtained from the width of the preceding m bits and the subsequent n bits centering on two or more x positions separated by the synchronous block length interval in the reproduced digital data. In order to detect the position, the position where the same synchronous block exists is detected at least x times, and there is an opportunity to be determined to be a synchronous block x times. Also, (m +
n) Since it has a bit width, it can be detected including a period shift of the synchronous block.

The operation described above has the effect of improving the accuracy of correction of missing sync patterns and ID errors and the elimination of false sync blocks, and the effect of the malfunction of the reproduction clock that the period of the synchronization pattern in the reproduced digital data changes. An effect that a synchronous block can be normally detected can be obtained.

Next, according to the configuration of the second invention, all I
Even if an error occurs in the parity part of D,
Since D itself is normal, synchronous block detection can be performed using the continuity of ID. With this, the ID
, It is possible to prevent the detection accuracy from deteriorating due to the detection error of.
This is very effective especially at the initial stage when the protection circuit of the synchronous block has not been pulled in yet.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing a synchronization block according to an embodiment of the present invention.

FIG. 2 is a block diagram of a digital signal processing circuit according to the embodiment of the first invention;

FIG. 3 is a timing chart for explaining the operation of the synchronous pattern detection and protection circuit according to the embodiment of the first invention;

FIG. 4 is a timing chart for explaining the operation of the synchronous pattern detection and protection circuit according to the embodiment of the first invention;

FIG. 5 is a timing chart for explaining the operation of the synchronous block detection and protection circuit according to the embodiment of the first invention;

FIG. 6 is a timing chart for explaining the operation of the embodiment of the first invention;

FIG. 7 is a timing chart for explaining the operation of the embodiment of the first invention;

FIG. 8 is a block diagram of a digital signal processing circuit according to a second embodiment of the first invention;

FIG. 9 is a timing chart for explaining the operation of the embodiment of the first invention;

FIG. 10 is a timing chart for explaining the operation of the embodiment of the first invention;

FIG. 11 is a timing chart for explaining the operation of the embodiment of the first invention;

FIG. 12 is a timing chart for explaining the operation of the embodiment of the second invention;

FIG. 13 is a schematic view showing an example of a conventional track pattern.

FIG. 14 is a schematic diagram showing an example of a conventional synchronous block.

FIG. 15 is a block diagram of a conventional digital signal processing circuit.

FIG. 16 is a timing chart for explaining the operation of a conventional digital signal processing circuit.

FIG. 17 is a timing chart for explaining the operation of a conventional digital signal processing circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Serial / parallel conversion circuit 11, 12 Delay circuit 13, 14, 15 Synchronization pattern detection circuit 16, 17, 18 ID detection circuit 19 Synchronization pattern detection protection circuit 20, 120 Synchronous block detection circuit 21, 121 Mask circuit 22, 122 Demodulation circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G11B 20/10 G11B 20/14 G11B 20/18 H04L ^7/ 00-7/10

Claims (15)

(57) [Claims] 1. k mounted on a cylindrical cylinder
The number of heads, the synchronization pattern indicating the beginning of the block of digital data recorded as an oblique track on the tape, the ID indicating the position of the data as an information signal and indicating the order of the blocks, and the error of the ID A digital signal processing circuit of a digital signal reproducing apparatus for reproducing data of one or more signal areas formed by connecting a plurality of synchronous blocks each including data including an ID parity to be detected or corrected. A sync pattern is detected from the width of the preceding m bits and the subsequent n bits centering on the positions of two or more x locations separated by the middle synchronization block length interval, and the preceding m bits are centered on the x locations separated by the synchronization block length interval. X corresponding to the position of the synchronization pattern existing in the width of the last n bits and separated by the synchronization block length interval
ID from the width of m bits before and n bits after
And the ID parity, and detects x synchronization pattern detection positions and x synchronization pattern detection positions indicating where the synchronization pattern exists in the (m + n) width; x detection IDs; By using x ID detection positions indicating where the detection ID is located in the (m + n) width and x ID parities, y less than or equal to x is consecutive.
Have the sync block detection means for detecting the number of sync blocks
And the synchronous block detecting means operates at the (m + n) width.
Priority for determining where the synchronization block exists
The higher the number of detected synchronization patterns, the more error-free
The larger the number of detection IDs, the earlier in the x locations
From the position where the last synchronization block was detected
The synchronization pattern is detected at the same synchronization pattern detection position as the expected position.
The more the turn is detected, the more the previous synchronization block is detected
The same ID detection position as the expected position from the
A digital signal processing circuit wherein the higher the number of IDs detected, the higher the ID . 2. k mounted on a cylindrical cylinder
The number of heads, the synchronization pattern indicating the beginning of the block of digital data recorded as an oblique track on the tape, the ID indicating the position of the data as an information signal and indicating the order of the blocks, and the error of the ID A digital signal processing circuit of a digital signal reproducing apparatus for reproducing data of one or more signal areas formed by connecting a plurality of synchronous blocks each including data including an ID parity to be detected or corrected. A synchronization pattern is detected from the width of the preceding m bits and the subsequent n bits centering on two or more x positions separated by the middle synchronization block length interval, and the x synchronization patterns are detected and the (m +
The position of the synchronous block is predicted based on x synchronous pattern detection positions indicating at which position in the width of n) the synchronous pattern exists, and the synchronous block length interval corresponding to the predicted synchronous block position An ID and an ID parity are detected from x positions apart from each other, and x consecutive sync patterns are detected by the x synchronous pattern detections, the synchronous pattern detection positions, the x detected IDs, and the x ID parities.
It has a synchronous block detecting means for detecting the following y synchronous blocks, and the synchronous block detecting means has a width of (m + n).
Priority for determining where the synchronization block exists
The higher the number of detected synchronization patterns, the more error-free
The larger the number of detection IDs, the earlier in the x locations
From the position where the last synchronization block was detected
Synchronous pattern at the same synchronous pattern detection position as expected
The more blocks that were detected, the earlier the synchronization block was detected
There is no error in the same ID detection position as the position expected from the position
A digital signal processing circuit wherein the higher the ID is, the higher the ID is . 3. A synchronization block for detecting y synchronization blocks.
When the y detecting unit detects y synchronous blocks,
Among the detected y synchronization blocks or y synchronizations
Synchronized blocks are detected for data sandwiched between blocks.
Characterized in that it has a mask means for preventing it from coming out.
3. A digital signal processing circuit according to claim 1, wherein 4. The k mounted on a cylindrical cylinder
Head as a diagonal track on the tape.
The beginning of recorded digital data
Indicates the synchronization pattern and the position of the data as an information signal.
ID indicating the block order and the error of the ID are detected.
Data including the ID parity to be output or corrected.
One or more signals composed of multiple synchronized blocks
Of a digital signal reproducing device that reproduces data in the
Digital signal processing circuit,
Is the position of two or more x points separated by the same synchronization block length interval?
Detection of x synchronization patterns detected from the same and x detection IDs
And x ID parities, the number of y synchronous blocks less than x
When determining if a lock exists, x detected
Error in all x IDs due to the ID and ID parity
Even if detected, z or more of the above-mentioned detections that are not less than 2 and not more than x
If the continuity of the ID is satisfied, the y synchronization blocks
2. A digital signal processing circuit comprising: a synchronous block detecting means for determining that a block has been detected . 5. Synchronizing reproduced digital data with (x-1) synchronization
Delay the block length, and start data from x points at the synchronous block length interval.
Delay means for taking out data, and from the x position of the delay means
According to the extracted data, the synchronization pattern is calculated from the width of (m + n).
And the synchronous pattern detection pulse and the (m +
n) where the synchronization pattern exists in the width
X synchronization patterns that output the synchronization pattern detection position indicated
Extracted from the x point of the delay detection means and the delay means.
According to the data, the width at which the synchronization pattern was detected is
ID and ID parity detected from corresponding (m + n) width
And an ID error flag based on the detection ID and the ID parity.
Or wherein the ID to the position of etc. the width (m + n) is present
X ID detection means for outputting the ID detection position shown,
x synchronization patterns detected and x synchronization patterns
Detection position, x number of the detection IDs and x number of the ID parities
Y and x or less ID detection positions,
Output from the delay circuit
Demodulate the y synchronization blocks in the data, and
Having a synchronous block detecting means for correcting the ID
2. The digital signal processing circuit according to claim 1, wherein: 6. A delay means for delaying reproduced digital data by (x-1) synchronization block length and extracting data from x locations at a synchronization block length interval, and (m + n) The synchronization pattern is detected from the width, and the synchronization pattern detection pulse and the (m +
x synchronization pattern detection means for outputting a synchronization pattern detection position indicating at which position in the width of n) the synchronization pattern exists; x synchronization pattern detection pulses and x synchronization pattern detection pulses Depending on the detection position, (m
+ N) The position where the synchronization pattern exists within the width of (n) is predicted, and the synchronization pattern detection protection pulse and the protection synchronization pattern detection position indicating at which position in the (m + n) width the synchronization pattern exists and the protection A synchronous pattern detection protection unit for outputting synchronization pattern detection state information indicating a detection state of x synchronization patterns detected at the synchronization pattern detection position; and data obtained from the x position of the delay unit. X number of ID detecting means for detecting an ID and an ID parity at a position corresponding to the detected position and outputting an ID error flag in which an error has been detected based on the detected ID and the ID parity; A synchronous pattern detection position, the synchronous pattern detection state information, x pieces of the detection IDs, and x pieces of the I
A synchronous block detecting means for detecting y synchronous blocks equal to or less than x based on the D error flag, demodulating the y synchronous blocks in the data output from the delay circuit, and correcting an erroneous ID. Yes, and the synchronization block detection means, the width of the (m + n)
Priority for determining where the synchronization block exists
The higher the number of detected synchronization patterns, the more error-free
As the number of detected IDs increases, the reproduced data is acquired from the delay circuit.
Of the x locations that are close to the last stage,
The same synchronization pattern as the position expected from the position where the
The more the synchronization pattern is detected at the
The same I as the position predicted from the position where the synchronous block was detected
The higher the ID with no error at the D detection position, the higher the
Digital signal processing circuit according to claim 2, wherein the Kusuru. 7. The synchronous block detecting means comprises: (m + 1)
Determine where in the width the sync block is located
The higher the number of detected synchronization patterns, the higher the priority
The larger the number of detected IDs without
Of the x locations where the
Synchronization with the expected position from the position where the initial block was detected
If a synchronization pattern is detected at the pattern detection position,
The position predicted from the position where the last synchronous block was detected
An error-free ID is detected at the same ID detection position as
The digital signal processing circuit according to claim 5, wherein the higher the value, the higher the value . 8. The synchronous pattern detection and protection means comprises (m +
where in the width of n) the synchronization pattern exists
The priority of the judgment is
Out of the x locations where the reproduced data is extracted from the delay circuit
Near the end of the stage, from the position where the last synchronization block was detected
To the same sync pattern detection position as the expected position.
The higher the number of detected patterns, the higher the
The digital signal processing circuit according to claim 6 . 9. A synchronous block detecting means, comprising:
Is determined to exist, the representative protection ID value and y
Correct the ID in the wrong part of the ID
And holds the x pieces of ID correction information shown in the previous synchronization block.
To the same position as expected from the detected position.
Before the last representative, to determine if there is a
Protection ID value, x pieces of the ID correction information, and x pieces of synchronization
Pattern detection and x synchronization pattern detection positions and x detection
The output block and the x number of ID error flags cause
Judge whether a block exists and detect the previous synchronization block
Synchronization block at a position different from the expected position
When it is determined whether or not there are x synchronization patterns,
And x number of the synchronous pattern detection positions and x
The detected ID and the x number of the ID error flags indicate the same.
Is determined whether or not there is an
Synchronization block to the same position as expected from the position where the
If it is determined that the lock does not exist, the representative protection ID is
ID of next synchronization block predicted from current protection ID
The correction information of x IDs is shifted backward,
D Modification information, protection ID value, and detected synchronous block position
Demodulates the output data of the delay circuit
6. The method according to claim 5, wherein the ID is corrected and output.
Digital signal processing circuitry of the mounting. 10. When the synchronous block detecting means determines that a synchronous block exists, a representative protection ID value and y
The locations are incorrect among the pieces of ID to hold the x pieces of ID correction information indicating to modify the ID, the coercive the same position as the expected location from position detected last synchronization block
If the protection synchronization pattern exists, the protection ID value of the previous representative, x pieces of the ID correction information, and the synchronization pattern
Based on the detection protection pulse, the synchronization pattern detection state information, the x detection IDs, and the x ID error flags, it is determined whether or not a synchronization block is present. If a synchronization pattern exists at a different position, the synchronization pattern detection
Based on the protection pulse , the synchronization pattern detection status information, the x detection IDs, and the x ID error flags, it is determined whether or not a synchronization block exists, and the same as the position predicted from the position where the previous synchronization block was detected. If it is determined that no synchronous block exists at the position, the representative protection ID is set to the ID of the next synchronous block predicted from the current protection ID.
The correction information of x IDs is shifted backward,
D Modification information, protection ID value, and protection synchronization pattern detection position
By the location, demodulates the output data of the delay circuit, erroneously correct the ID and and outputs claim 6 digital signal processing circuit according. 11. The synchronous block detecting means includes: y synchronous blocks;
When it is determined that a block exists, the output of the delay circuit
Until all the y synchronization blocks have been output,
Only at the timing of receiving the information of the synchronous block
Open the window, and then always open after one synchronization block length
When the window is open
A determination of a synchronous block only when
7. The digital signal processing circuit according to claim 5 or claim 6 . 12. When the synchronous block detecting means determines that there are y synchronous blocks, a final stage of the delay circuit
Output also detects the synchronization pattern in the y synchronization blocks
Until all of the synchronous blocks that have been detected and have no error in the detection ID are output, the window is opened only at the timing at which y pieces of information of the synchronous blocks can be received, and thereafter, after one synchronous block length, there is provided a masking means that is always opened. 7. The digital signal processing circuit according to claim 5 , wherein the determination of the synchronization block is made only when the window is open. 13. sync block detection means, when it is determined that the y-number of sync blocks are present, until the output of the final stage of the delay circuit y-number of sync blocks are output total, y-number of the synchronization open the window only at the timing when receive information of the block, after its has a mask means to open always-on, claim 5 and characterized in that only the determination of the synchronization block when the window is open
A digital signal processing circuit according to claim 6 . 14. When the synchronous block detecting means determines that there are y synchronous blocks , the synchronous pattern in the y synchronous blocks is also detected by the output of the last stage of the delay circuit.
Until all the synchronous blocks that have been detected and have no error in the detection ID are output, the window is opened only at the timing at which the information of the y synchronous blocks can be received. 請, characterized in that only the determination of the synchronization block when open
The digital signal processing circuit according to claim 5 or claim 6 . 15. sync block detection means has detected
The same ID exists in one track of the synchronous block
In this case, it is advisable to adopt the synchronization block detected later.
7. The digital signal processing circuit according to claim 5, wherein: