JP2912096B2 - Binary signal reproduction method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for generating a binary digital signal recorded on an optical disk carrier, and particularly to a method for generating a binary signal when the detection of a data mark pattern as a starting point for reproducing a data string has failed. The present invention relates to a signal reproducing method.

[0002]

2. Description of the Related Art Conventionally, a data structure for recording data in an optical disk apparatus for optically recording and reproducing a binary digital signal generally includes an initial phase of a reproduced clock extracting phase synchronization circuit as shown in FIG. A phase pull-in pattern 1 having a constant frequency for pull-in, a data mark pattern 2 indicating the head start position of the recording data following the phase pull-in pattern 1, a data pattern 3 which has been subjected to recording modulation following this data mark pattern 2, and It is composed of

[0003] Such a data structure is widely used in an optical disk device which is one of auxiliary storage devices in a computer system. For example, the international standard IS
It is disclosed as follows in O / TC97 / SC23N.

As shown in FIG. 5B, the data structure of the data portion in the continuous servo 1K sector format is a 12-data byte phase subtraction pattern (VF) composed of a repetition pattern of 010010.
O3), a data mark pattern (referred to as SYNC) 2 having a length of 3 data bytes composed of a special pattern, a data pattern 3 having a length of 1200 data bytes composed of data and an error correction code, and 20. 59 resynchronization patterns (RESYNC) inserted for each data byte length and composed of a special pattern of one data byte length
4).

The data mark pattern 2 indicates the start position of reproduction of data from the optical disk carrier, that is, the start of digital demodulation, and 48 channel bits (a channel bit is one data bit in one unit of recording-modulated recording). 2) which is a pattern of channel bits.
Generally, in detecting the data mark pattern 2, 4
The whole is divided into a plurality of parts, and a method is adopted by majority logic operation of each pattern matching result so that detection is successful even if a part of eight channel bits is missing.

The resynchronization pattern 14 is the data pattern 3
When a demodulation timing shift occurs during reproduction of the data, the signal is prepared for repairing the timing, and is generally detected by pattern matching.

[0007]

In an optical disk apparatus using the above-described data structure, a mistake in detecting the data mark pattern 2 during the reproduction of the data directly leads to a failure in the reproduction of the data. Therefore, as described above, the whole is divided into a plurality of parts and a method based on a majority logic operation of each pattern matching result is adopted so that detection is successful even if a part of the data mark pattern 2 is missing.

However, it is not possible to completely eliminate the lack of a pattern due to a medium defect or the like.
The probability of occurrence of a medium defect of about 25 μm corresponding to 48 channel bits at the innermost circumference of the optical disc carrier disclosed in the aforementioned international standard is generally said to be 10 ⁻⁶ to 10 ⁻⁷ . Therefore, the verify read is performed immediately after the data recording, and an alternative recording operation is performed when a failure occurs.

However, due to the progress of medium defects and the subsequent scratches on the optical disk carrier surface, the data mark pattern 2
Detection may fail. At this time, as one of the retry processes, there is a method in which the first resynchronization pattern 4 arranged 20 bytes after the data mark pattern 2 is used as a starting point of data reproduction in place of the data mark pattern 2, Since digital demodulation for 20 bytes is not performed, data recovery is expected by error correction processing (the method is disclosed in the above-mentioned international standard), or there are some media defects even after the first 20 bytes of data. On the other hand, there is a possibility that the data in the sector can be completely reproduced, which may be a fatal obstacle.

[0010]

According to the present invention, there is provided a binary digital signal recorded on an optical disk carrier, comprising: a phase locking pattern having a constant frequency for initial locking of a phase locked loop circuit for extracting a reproduction lock; Following the pattern, a data mark pattern indicating the head start position of the recording data, a data pattern modulated following the data mark pattern, and a data pattern inserted at every fixed length of m bytes and indicating a data delimiter. In a data string reproduction method including a plurality of n-byte length resynchronization patterns, when a part of the data mark pattern is missing and detection fails, detection of a first resynchronization pattern following the data mark pattern Day by was a starting point, and said data sequence was the m + n byte delayed signal
In the binary signal reproduction method for starting reproduction of the data pattern, the reproduction of the data pattern is started by a majority decision between the first resynchronization pattern and a data mark pattern from a signal obtained by delaying the data sequence by m + n bytes. It is characterized by timing detection by a logical operation as a starting point.

Furthermore, when said part of the data mark pattern and the first resync pattern detection part missing fails, the subsequent before Symbol data mark pattern 2
The data by the a starting point to detect the resync pattern, and the data sequence 2 (m + n) signal obtained by bytes delayed
In the binary signal reproduction method for starting reproduction of the data pattern, the reproduction of the data pattern is started by the first resynchronization from the second resynchronization pattern and a signal obtained by delaying the data sequence by m + n bytes. It is characterized in that timing is detected by a majority logic operation of a pattern and a data mark pattern from a signal obtained by delaying the data string by 2 (m + n) bytes.

[0012]

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1A is a block diagram showing a first embodiment of a binary signal reproducing system according to the present invention, and FIG. 1B is a time chart thereof. In the present embodiment, 21 data bytes corresponding to a data sequence 101 composed of channel bit sequences reproduced from an optical disk carrier are input, that is, 3 data bytes.
A shift register 12 for 36 channel bits, and a resynchronization pattern detection circuit 14 which receives output signals 103 of 16 registers S1 to S16 from the first to sixteenth of the shift register 12 and outputs a demodulation start timing signal 104 And a delay output signal 102 from the 336th register S336 of the shift register 12, that is, a data sequence delayed by 21 data bytes and a demodulation start timing signal 104 to output demodulation data 105. It is composed of

The resynchronization pattern detection circuit 14 is adapted to the international standard ISO / TC97 / SC in the optical disc device described above.
Pattern matching is performed for all 16 channel bits of the resynchronization pattern 4 (pattern arrangement is “0010 0000 0001 0010”) disclosed in 23N.

Next, the timing of each part in the block diagram of FIG. 1A will be described with reference to FIG. First, a data sequence 101 from the optical disk carrier is shifted by 336 channel bits by the shift register 12 to become a delayed output signal 102. The timing of the first byte of the data portion of the delayed output signal 102 is
At the 21st byte of the data portion following the first resynchronization pattern R1.

Therefore, by demodulating the delayed output signal 102 starting from the demodulation start timing signal 104 based on the first resynchronization pattern R1, it is possible to demodulate from the first byte of the data portion, that is, from the beginning.
Demodulated data 105 is obtained.

In this embodiment, only the circuit block diagram corresponding to the case where the data mark pattern 2 cannot be detected is shown. However, when the data mark pattern 2 is normally detected, the demodulation circuit of another system is used. Or a demodulation start timing signal 104 based on the data string 101, the delay output signal 102, and the resynchronization pattern R1 at the input of the demodulation circuit 15, and a demodulation start timing signal based on the data mark pattern 2 (not shown). And are used by switching between them. Further, the binary signal reproduction method of the present embodiment may be applied in the first read processing of the corresponding data, or may be applied as one of retry processing.

Next, a second embodiment of the present invention will be described. FIGS. 2A and 2B are block diagrams showing a second embodiment of the present invention, and FIG. 2C is a time chart thereof. In the present embodiment, the shift register 22 for 24 data bytes, that is, 384 channel bits, to which the data sequence 101 composed of the channel bit sequence generated from the optical disc carrier is input, and the first to sixteenth shift registers 22 are used. And the delay output signal 203 of the 16 registers S1 to S16 and the output signal 206 of the 48 registers S337 to S384 of the shift register 22 from the 337th to 384th, and outputs the demodulation start timing signal 204. Complex synchronous pattern detection circuit 2
4 and the 336th register S of the shift register 22
The demodulation circuit 15 receives the delayed output signal 202 from the 336, that is, the data sequence delayed by 21 data bytes and the demodulation start timing signal 204 and outputs the demodulated data 105.

The composite synchronous pattern detection circuit 24 is adapted to the international standard ISO / TC97 /
Resynchronization pattern 4 disclosed in SC23N (pattern arrangement is “0010 0000 0001 001
0) and data mark pattern 2 (pattern arrangement is “0100 0010 01”).
00 0010 0010 0010 0100 01
00 1000 0010 0100 1000 ") to obtain a demodulation start timing signal 204.

FIG. 2B shows a composite synchronous pattern detecting circuit 2.
4 is a diagram illustrating an example of FIG. Composite synchronous pattern detection circuit 2
4 indicates that the input 64 channel bits are divided into four groups, that is, signals 203 from S1 to S16, S337 to S352, S353 to S368, and S369 to S38.
4 which are divided into four signals 206 and input, and perform pattern matching of the respective signals 206, 242, 243, 244
And comparison signals C1, C2, C
3 and C4, and a majority logic circuit 245 for obtaining a demodulation start timing signal 204.

Next, the timing of each part in each block diagram of FIGS. 2A and 2B will be described with reference to FIG. First, the data sequence 10 from the optical disk carrier
1, data pattern 3 is 3 in shift register 22.
Delayed output signal 202 shifted by 36 channel bits
Becomes The timing of the first byte of the data portion of the delayed output signal 202 matches the timing of the 21st byte of the data portion following the first resynchronization pattern R1 of the data string 101. Also, the data mark pattern 2 which is input prior to the data pattern 3 by 48 channel bits is 33
It is shifted by six channel bits and coincides with the detection timing of the first resynchronization pattern R1.

In this embodiment, the number of divisions of the resynchronization pattern R1 and the data mark pattern 2, or the circuit realizing method of the majority logic circuit 245 and the judgment threshold value may be changed.

Next, a third embodiment of the present invention will be described. FIG. 3A is a block diagram showing a third embodiment of the present invention, and FIG. 3B is a time chart thereof. In the present embodiment, a data sequence 101 composed of a channel bit sequence reproduced from an optical disc carrier is input 42.
The shift register 32 corresponding to data bytes, that is, 672 channel bits, and the output signals 303 of the 16 registers S1 to S16 from the first to the sixteenth of the shift register 32 are input and the demodulation start timing signal 304 is output. The resynchronization pattern detection circuit 34 and the delay output signal 302 from the 672nd register S672 of the shift register 32, that is, the data sequence delayed by 42 data bytes and the demodulation start timing signal 304 are input to the demodulation data 105. And an output demodulation circuit 15.

Next, the timing of each part in the block diagram of FIG. 3A will be described with reference to FIG. First, the data sequence 101 from the optical disk carrier is shifted by 672 channel bits by the shift register 32 to become a delayed output signal 302. This delayed output signal 302
The timing of the first byte of the data portion of
This coincides with the timing of the 41st byte of the data part following the second resynchronization pattern R2.

In this embodiment, a circuit corresponding to the case where the data mark pattern 2 and the first resynchronization pattern R1 cannot be detected is shown by a block diagram.
A circuit switching method when the data mark pattern 2 is normally detected and a method of applying the processing are described in the first embodiment of the present invention.
This is the same as the embodiment.

Next, a fourth embodiment of the present invention will be described. 4A and 4B are block diagrams showing a fourth embodiment of the present invention, and FIG. 4C is a time chart thereof. In the present embodiment, a shift register 42 for 45 data bytes, that is, 720 channel bits, to which a data sequence 101 composed of a channel bit sequence reproduced from an optical disk carrier is input, and first to sixteenth shift registers 42 The output signal 403 of the 16 registers S1 or S16 to the 16th register S337 to S352 of the shift register 42 from the 337th to the 352nd.
Output signal 406 of the shift register 42 and the sixth
A composite synchronous pattern detection circuit 44 which receives the output signals 407 of 48 registers S673 to S720 from 73 to 720 and outputs a demodulation start timing signal 404.
And the 672nd register S6 of the shift register 42
The demodulation circuit 15 receives the delayed output signal 402 from the P.72, that is, the data sequence delayed by 42 data bytes and the demodulation start timing signal 404 and outputs the demodulated data 105.

FIG. 4B shows a composite synchronous pattern detecting circuit 4.
4 is a diagram illustrating an example of FIG. Composite synchronous pattern detection circuit 4
4 represents the input 80 channel bits in five groups, that is, the signals 403 from S1 to S16 and the signals from S337 to S337.
352 signal 406 and S673 to S688, S68
9 to S704 and comparison circuits 441, 442, 443, 444, and 445, which are divided and input into signals 407 of S705 to S720 and compare respective patterns.
Comparison signals C from the respective comparison circuits 441 to 445
1, C2, C3, C4, C5 and a majority logic circuit 446 for obtaining a demodulation start timing signal 404.

Next, the timing of each part in each block diagram of FIGS. 4A and 4B will be described with reference to FIG. First, the data sequence 10 from the optical disk carrier
Data pattern 3 of 1 is shifted by shift register 42 to 67
The signal is shifted by two channel bits to become a delayed output signal 402. The timing of the first byte of the data portion of the delayed output signal 402 matches the timing of the 41st byte of the data portion following the second resynchronization pattern R2 of the data string 101. Also, the data mark pattern 2 input 48 data bits ahead of the data pattern 3 is shifted by 672 channel bits, and is shifted by the detection timing of the second resynchronization pattern R2 of the data string 101 and by 336 channel bits. This coincides with the detection timing of the first resynchronization pattern R1 in the signal.

Therefore, demodulation is performed by the second resynchronization pattern R2 of the data stream 101, the first resynchronization pattern R1 of the signal shifted by 336 channel bits, and the data mark pattern 2 shifted by 672 channel bits. By demodulating the delayed output signal 402 with the start timing signal 404 as a starting point, it is possible to demodulate from the first byte of the data part, that is, from the head, and obtain demodulated data 105.

The number of divisions of the resynchronization pattern R1, the resynchronization pattern R2 and the data mark pattern 2 in this embodiment,
Alternatively, the circuit realizing method of the majority logic circuit 446 and the determination threshold include the possibility of change.

In the binary signal reproducing system of the present invention, the data mark pattern 2 and the first resynchronization pattern R
Although the first detection error is described, it can be easily inferred that the present method can be applied to the second and subsequent resynchronization pattern detection errors.

[0032]

According to the binary signal reproducing method of the present invention, the recovery capability of a data mark pattern or a resynchronization pattern detection error due to a scratch or medium defect appearing later on the optical disk carrier is improved. In addition, it is possible to reduce the risk of a catastrophic failure in which data cannot be reproduced. Also, when a resynchronization pattern is detected with a delayed data pattern, reproduction from the first byte can be performed, and the load on the error correction processing can be reduced.

[Brief description of the drawings]

FIG. 1A is a block diagram showing a first embodiment of the present invention, and FIG. 1B is a timing chart thereof.

FIGS. 2A and 2B are block diagrams showing a second embodiment of the present invention, and FIG. 2C is a timing chart thereof.

FIG. 3 (a) is a block diagram showing a third embodiment of the present invention, and FIG. 3 (b) is a timing chart thereof.

FIGS. 4A and 4B are block diagrams showing a fourth embodiment of the present invention, and FIG. 4C is a timing chart thereof.

FIGS. 5A and 5B are diagrams showing a configuration of recording data in an optical disk device.

[Explanation of symbols]

Reference Signs List 1 phase pull-in pattern 2 data mark pattern 3 data pattern 4 resynchronization pattern 12, 22, 32, 43 shift register 14, 34 resynchronization pattern detection circuit 15 demodulation circuit 24, 44 composite synchronization pattern detection circuit 101 data sequence 102, 202, 302, 402 Delayed output signal 103, 203, 303, 403 Output signal 104, 204, 304, 404 Demodulation start timing signal 105 Demodulated data 241 to 244, 441 to 445 Comparison circuit 245, 446 Majority logic circuit

──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Sumi Nakajima Gunma Nippon Electric Co., Ltd. 32, Nishi-Yajima, Ota City, Gunma Prefecture (56) References JP-A-63-63172 (JP, A) JP-A-2- 230561 (JP, A) (58) Field surveyed (Int. Cl. ⁶ , DB name) G11B 20/14 G11B 20/10 G11B 7/00

Claims (2)

(57) [Claims] 1. A binary digital signal recorded on an optical disk carrier, wherein the phase lock-in pattern has a constant frequency for initial lock-in of a phase lock circuit for extracting a reproduction lock.
Following this phase pull-in pattern, a data mark pattern indicating the head start position of the recording data, a data pattern that has been subjected to recording modulation following this data mark pattern, and a data pattern that is inserted at a fixed length of m bytes, and A data string reproduction method comprising a plurality of n-byte length resynchronization patterns indicating a delimiter, wherein when a part of the data mark pattern is missing and detection fails, a first data mark pattern following the data mark pattern as a starting point a resync pattern detection, and in a binary signal reproducing system to start the reproduction of the data pattern by the signal data sequence delayed m + n bytes, the start of reproduction of the data pattern, again the first Majority decision between a synchronization pattern and a data mark pattern from a signal obtained by delaying the data sequence by m + n bytes A binary signal reproducing method characterized by using timing detection by a logical operation as a starting point. 2. A binary digital data recorded on an optical disk carrier.
This is the initial signal of the phase locked loop for playback lock extraction.
A constant frequency phase pull-in pattern for
Start of recording data following this phase pull-in pattern
Data mark pattern indicating the position and this data mark
The data pattern that was recorded and modulated following the pattern
The data pattern is inserted every fixed length m bytes,
Pattern of multiple n-byte resynchronization patterns
A reproduction method of the data sequence consisting of over emissions, when the portion of the data mark pattern and the first resync pattern detection part missing fails, the subsequent before Symbol data mark pattern 2, starting reproduction of the data pattern by a signal obtained by delaying the data sequence by 2 (m + n) bytes starting from the detection of the resynchronization pattern 2
In the value signal reproducing method, the reproduction of the data pattern is started when the second re-synchronization pattern and the first re-synchronization pattern and the data sequence from the signal obtained by delaying the data sequence by m + n bytes are used.
A binary signal reproduction system characterized by starting timing detection by majority logic operation with a data mark pattern from a signal delayed by (m + n) bytes.