JPH06124547A - Binary signal reproducing system - Google Patents

Abstract

PURPOSE:To improve the recovery capability of a detection miss by starting a reproduction with the signal in which a data train is delayed for equivalent to the prescribed number of bytes while making the detection of a first resynchronization pattern as a starting point when a data mark pattern detection is failed. CONSTITUTION:A data train 101 from an optical disk carrier is delayed for equivalent to (m+n) bytes (where m is a constant length of a data pattern and n is a resynchronization pattern length) by as shift register 12 and is made to a signal 102. The signal 102 is demodulated by using a demodulation start timing signal 104 as the starting point by a first resynchronization pattern that follows the data mark pattern outputted from a resynchronization pattern detecting circuit 14. Thus, even though the detection of a data mark pattern is failed, the data section is demodulated by a demodulating circuit 15 from the top and the recovery capability against a data mark pattern detection miss is improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of generating a binary digital signal recorded on an optical disk carrier, and particularly when the detection of a data mark pattern which is a starting point for reproducing a data string fails. The present invention relates to a signal reproduction method.

[0002]

2. Description of the Related Art Conventionally, as shown in FIG. 5 (a), the data structure for recording in an optical disk device for optically recording / reproducing a binary digital signal is generally as shown in FIG. A phase pull-in pattern 1 having a constant frequency for pull-in, a data mark pattern 2 following the phase pull-in pattern 1 and indicating a head start position of recording data, and a data pattern 3 following the data mark pattern 2 and subjected to recording modulation. It is composed of.

Such a data structure is widely used in an optical disk device which is one of auxiliary storage devices in a computer system. For example, the international standard IS
The following is disclosed in O / TC97 / SC23N.

The data structure of the data portion in the continuous servo 1K sector format is, as shown in FIG. 5B, a phase pulling pattern (VF) of 12 data bytes in length, which is composed of a repeating pattern of 010010.
1 called O3), a data mark pattern (called SYNC) 2 having a length of 3 data bytes composed of a special pattern, a data pattern 3 having a length of 1200 data bytes composed of data and an error correction code, etc. 59 resynchronization patterns (RESSYNC) that are inserted for each data byte length and consist of a special pattern of 1 data byte length
It is called 4).

The data mark pattern 2 indicates the starting position of the reproduction of data from the optical disk carrier, that is, the digital demodulation, and is 48 channel bits (each channel bit is one data bit in one recording-modulated recording). 2)) channel bit pattern.
Generally, in detecting the data mark pattern 2, 4
A method is adopted in which the whole is divided into a plurality of pieces and the majority logic operation of the respective pattern matching results is performed so that the detection can be successful even if a part of the 8 channel bits is lost.

The resynchronization pattern 14 is the data pattern 3
When a demodulation timing shift occurs during the reproduction of the above, it is prepared to restore the timing and is generally detected by pattern matching.

[0007]

In the optical disc device using the above-mentioned data structure, the detection error of the data mark pattern 2 at the time of reproducing the data directly leads to the data reproduction failure. Therefore, as described above, in order to detect the data mark pattern 2 even if a part of the data mark pattern 2 is missing, the whole is divided into a plurality of patterns and the method of the majority logic operation of the respective pattern matching results is adopted.

However, it is impossible to completely eliminate the pattern loss due to a medium defect or the like. For example, the size where most of the data mark pattern 2 is lost, that is,
The probability of occurrence of a medium defect of about 25 μm corresponding to 48 channel bits at the innermost circumference of the optical disc carrier disclosed in the above-mentioned international standard is generally said to be 10 ⁻⁶ to 10 ⁻⁷ . Therefore, the verify read is performed immediately after the data recording, and the alternative recording operation is performed to deal with the defect.

However, due to the progress of medium defects and the subsequent scratches on the surface of the optical disc carrier, the data mark pattern 2
May fail to detect. At this time, as one of the retry processes, there is also a method in which the first resynchronization pattern 4 arranged 20 bytes after the data mark pattern 2 is used as a substitute for the data mark pattern 2 as a starting point of data reproduction, but Since 20 bytes of digital demodulation are not performed, data recovery is expected by error correction processing (method is disclosed in the above-mentioned international standard), or there are medium defects even after the first 20 bytes of data. On the other hand, the data in that sector may not be reproduced at all, which may be a fatal obstacle.

[0010]

SUMMARY OF THE INVENTION The present invention is a binary digital signal recorded on an optical disc carrier, and a phase pull-in pattern of a constant frequency for initial pull-in of a phase lock circuit for reproducing lock extraction, and this phase. Following the pull-in pattern, a data mark pattern indicating the head start position of recording data, a data pattern obtained by recording and modulating the data mark pattern, and a constant length m of this data pattern.
In a reproducing method of a data string which is inserted for each byte length and includes a plurality of re-synchronization patterns having an n-byte length indicating data delimiters, when a part of the data mark pattern is missing and detection fails, Starting from the detection of the first re-synchronization pattern following the data mark pattern, the reproduction is started by a signal obtained by delaying the data string by m + n bytes. In addition, when the reproduction is started, the first resynchronization pattern and the data string are m + n.
Timing detection by a majority logic operation with a data mark pattern from a signal delayed by bytes may be used as a starting point.

Further, when a part of the data mark pattern and a part of the first resynchronization pattern are missing and the detection fails, the start of the reproduction is followed by a second resynchronization. It is characterized in that the reproduction is started by a signal having the pattern detection as a starting point and the data string delayed by 2 (m + n) bytes. Also,
The start of the reproduction is the first signal from the signal obtained by delaying the second resynchronization pattern and the data string by m + n bytes.
The timing detection by the majority logic operation of the re-synchronization pattern and the data mark pattern from the signal obtained by delaying the data string by 2 (m + n) bytes may be the starting point.

[0012]

Next, the present invention will be described in detail with reference to the drawings.

FIG. 1A is a block diagram showing a first embodiment of the binary signal reproducing system of the present invention, and FIG. 1B is a time chart thereof. In this embodiment, 21 data bytes corresponding to the data string 101 composed of the channel bit string reproduced from the optical disc carrier, that is, 3
A shift register 12 for 36 channel bits and a resynchronization pattern detection circuit 14 for inputting the output signals 103 of 16 registers S1 to S16 of the first to sixteenth shift registers 12 and outputting a demodulation start timing signal 104 And the delay output signal 102 from the 336th register S336 of the shift register 12, that is, the data string delayed by 21 data bytes and the demodulation start timing signal 104 are input, and the demodulation circuit 15 that outputs the demodulation data 105 is input. Composed of and.

The resynchronization pattern detecting circuit 14 is an international standard ISO / TC97 / SC in the optical disc device described above.
The pattern matching of all 16 channel bits of the resynchronization pattern 4 (the pattern arrangement is “0010 0000 0001 0010”) disclosed in 23N is performed.

Next, the timing of each part in the block diagram of FIG. 1A will be described with reference to FIG. First, the data string 101 from the optical disc carrier is shifted by 336 channel bits in the shift register 12 and becomes the delayed output signal 102. The timing of the first byte of the data portion of the delayed output signal 102 is the data string 101
It coincides with the timing of the 21st byte of the data part following the first re-synchronization pattern R1.

Therefore, by demodulating the delayed output signal 102 starting from the demodulation start timing signal 104 according to the first resynchronization pattern R1, it becomes possible to demodulate from the first byte of the data portion, that is, from the beginning.
The demodulated data 105 is obtained.

In this embodiment, only the corresponding circuit block diagram when the data mark pattern 2 cannot be detected is shown, but when the data mark pattern 2 is normally detected, a demodulation circuit of another system is shown. , Or the demodulation circuit 15 at the input, the demodulation start timing signal 104 by the data string 101, the delayed output signal 102 and the resynchronization pattern R1, and the demodulation start timing signal by the data mark pattern 2 (not shown). Used by switching between and. Further, the binary signal reproducing method of the present embodiment may be applied in the first read processing of the corresponding data or may be applied as one of the retry processing.

Next, a second embodiment of the present invention will be described. 2A and 2B are block diagrams showing a second embodiment of the present invention, and FIG. 2C is a time chart thereof. In this embodiment, a shift register 22 for 24 data bytes, that is, 384 channel bits, which receives a data string 101 composed of a channel bit string generated from an optical disc carrier, and the first to 16th shift registers 22 of the shift register 22. Up to 16 registers S1 to S16 of the delayed output signal 203 and the shift register 22 of the 337th to 384th register of the 48th register S337 to S384 output signal 206 are input and the demodulation start timing signal 204 is output. Composite sync pattern detection circuit 2
4 and the 336th register S of the shift register 22
It is composed of a delayed output signal 202 from 336, that is, a demodulation circuit 15 which inputs a data string delayed by 21 data bytes and a demodulation start timing signal 204 and outputs demodulated data 105.

The composite sync pattern detection circuit 24 is the international standard ISO / TC97 / in the above-mentioned optical disk device.
Resynchronization pattern 4 disclosed in SC23N (the pattern arrangement is "0010 0000 0001 001
16 channel bits of "0") and data mark pattern 2 (pattern array is "0100 0010 01").
00 0010 0010 0010 010 01
00 1000 0010 0100 1000 ″) of 48 channel bits are input to obtain the demodulation start timing signal 204.

FIG. 2B shows a composite sync pattern detection circuit 2
It is a figure which shows an example of No. 4. Composite sync pattern detection circuit 2
4 is a group of four input 64 channel bits, that is, the signals 203 of S1 to S16, S337 to S352, S353 to S368, and S369 to S38.
Comparing circuits 241, 242, 243, and 244, which are divided into four signals 206 and input to perform pattern matching for each.
And comparison signals C1, C2, C from the respective comparison circuits
3 and C4 to obtain the demodulation start timing signal 204 and a majority logic circuit 245.

Next, the timing of each part in each block diagram of FIGS. 2A and 2B will be described with reference to FIG. First, the data string 10 from the optical disk carrier
Data pattern 3 of 1 is 3 in the shift register 22.
Delayed output signal 202 shifted by 36 channel bits
Becomes The timing of the first byte of the data portion of the delayed output signal 202 matches the timing of the 21st byte of the data portion following the first resynchronization pattern R1 of the data string 101. In addition, the data mark pattern 2 which is inputted 48 bits ahead of the data pattern 3 is also 33
It is shifted by 6 channel bits and coincides with the detection timing of the first resynchronization pattern R1.

In the present embodiment, the number of divisions of the resynchronization pattern R1 and the data mark pattern 2, or the circuit implementation method of the majority logic circuit 245 and the determination threshold value may be changed.

Next, a third embodiment of the present invention will be described. FIG. 3A is a block diagram showing a third embodiment of the present invention, and FIG. 3B is a time chart thereof. In this embodiment, a data string 101 composed of a channel bit string reproduced from an optical disc carrier is input 42.
A shift register 32 for data bytes, that is, 672 channel bits and an output signal 303 of 16 registers S1 to S16 of the first to sixteenth shift register 32 are input and a demodulation start timing signal 304 is output. The resynchronization pattern detection circuit 34 and the delay output signal 302 from the 672nd register S672 of the shift register 32, that is, the data string delayed by 42 data bytes and the demodulation start timing signal 304 are input and the demodulation data 105 is input. And a demodulation circuit 15 for outputting.

Next, the timing of each part in the block diagram of FIG. 3A will be described with reference to FIG. First, the data string 101 from the optical disk carrier is shifted by 672 channel bits in the shift register 32 to become the delayed output signal 302. This delayed output signal 302
The timing of the first byte of the data part of
This coincides with the timing of the 41st byte of the data portion following the 1st second resynchronization pattern R2.

In the present embodiment, the corresponding circuit when the data mark pattern 2 and the first resynchronization pattern R1 cannot be detected is shown in a block diagram.
The circuit switching method and the processing application method when the data mark pattern 2 is normally detected are the same as those of the first aspect of the present invention.
This is the same as the case of the embodiment.

Next, a fourth embodiment of the present invention will be described. 4A and 4B are block diagrams showing a fourth embodiment of the present invention, and FIG. 4C is a time chart thereof. In the present embodiment, a shift register 42 for 45 data bytes, that is, 720 channel bits for which a data string 101 composed of a channel bit string reproduced from an optical disc carrier is input, and the first to sixteenth shift registers 42. Output signal 403 of 16 registers S1 or S16 up to 16th register S337 to S352 of shift register 42 from 337th to 352nd
Output signal 406 of the shift register 42 and the sixth signal of the shift register 42
A composite sync pattern detection circuit 44 which inputs the output signals 407 of the 48 registers S673 to S720 from 73 to 720 and outputs the demodulation start timing signal 404.
And the 672nd register S6 of the shift register 42
A delay output signal 402 from 72, that is, a data train delayed by 42 data bytes and a demodulation circuit 15 which inputs the demodulation start timing signal 404 and outputs the demodulated data 105.

FIG. 4B shows the composite sync pattern detection circuit 4.
It is a figure which shows an example of No. 4. Composite sync pattern detection circuit 4
4 is a group of input 80 channel bits in 5 groups, that is, the signals 403 from S1 to S16 and S337 to S.
352 signal 406 and S673 to S688, S68
The comparison circuits 441, 442, 443, 444, and 445, which divide and input the signals 407 from 9 to S704 and S705 to S720, and compare the respective pattern matches.
Comparison signal C from each comparison circuit 441 to 445
1, C2, C3, C4 and C5 are input to obtain a demodulation start timing signal 404 and a majority logic circuit 446.

Next, the timing of each part in each block diagram of FIGS. 4A and 4B will be described with reference to FIG. First, the data string 10 from the optical disk carrier
The data pattern 3 of 1 is 67 in the shift register 42.
The delayed output signal 402 is shifted by two channel bits. The timing of the 1st byte of the data portion of the delayed output signal 402 matches the timing of the 41st byte of the data portion following the second resynchronization pattern R2 of the data string 101. Further, the data mark pattern 2 input preceding the data pattern 3 by 48 channel bits is also shifted by 672 channel bits, and is also shifted by the detection timing of the second resynchronization pattern R2 of the data string 101 and 336 channel bits. This coincides with the detection timing of the first resynchronization pattern R1 in the signal.

Therefore, demodulation by the second resynchronization pattern R2 of the data string 101, the first resynchronization pattern R1 in the signal shifted by 336 channel bits, and the data mark pattern 2 shifted by 672 channel bits. By demodulating the delayed output signal 402 with the start timing signal 404 as a starting point, it becomes possible to demodulate from the first byte of the data portion, that is, from the beginning, and demodulated data 105 is obtained.

The number of divisions of the resynchronization pattern R1, the resynchronization pattern R2, and the data mark pattern 2 in this embodiment,
Alternatively, the circuit implementation method of the majority logic circuit 446 and the determination threshold include the possibility of change.

In the binary signal reproducing system of the present invention, the data mark pattern 2 and the first resynchronization pattern R
Although the detection error of No. 1 has been described, it can be easily inferred that the present method can be applied to the detection error of the second and subsequent resynchronization patterns.

[0032]

According to the binary signal reproducing method of the present invention, the recovery capability of the detection error of the data mark pattern or the resynchronization pattern due to scratches or medium defects appearing subsequently on the optical disk carrier is improved. , It is possible to reduce the risk of falling into a fatal failure in which data cannot be reproduced. Further, even when the data pattern is delayed and the resynchronization pattern is detected, the reproduction from the first byte can be performed, and the burden on the error correction processing can be reduced.

[Brief description of drawings]

FIG. 1A is a block diagram showing a first embodiment of the present invention, and FIG. 1B is a timing chart thereof.

2A and 2B are block diagrams showing a second embodiment of the present invention, and FIG. 2C is a timing chart thereof.

FIG. 3A is a block diagram showing a third embodiment of the present invention, and FIG. 3B is a timing chart thereof.

FIGS. 4A and 4B are block diagrams showing a fourth embodiment of the present invention, and FIG. 4C is a timing chart thereof.

5A and 5B are diagrams showing the structure of recording data in the optical disc device.

[Explanation of symbols]

1 phase pull-in pattern 2 data mark pattern 3 data pattern 4 resynchronization pattern 12, 22, 32, 43 shift register 14, 34 resynchronization pattern detection circuit 15 demodulation circuit 24, 44 composite synchronization pattern detection circuit 101 data string 102, 202, 302, 402 Delayed output signal 103, 203, 303, 403 Output signal 104, 204, 304, 404 Demodulation start timing signal 105 Demodulation data 241-244, 441-445 Comparison circuit 245, 446 Majority decision logic circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Sumi Nakajima 32, Nishiyajima, Ota-shi, Gunma Gunma Nippon Electric Co., Ltd.

Claims (4)

[Claims] 1. A binary digital signal recorded on an optical disk carrier, a phase pull-in pattern of a constant frequency for initial pull-in of a phase lock circuit for reproducing lock extraction, and a head of recorded data following this phase pull-in pattern. A data mark pattern indicating the start position, a data pattern obtained by recording and modulating the data mark pattern,
In a reproducing method of a data string which is inserted every fixed length m bytes of this data pattern and which is composed of a plurality of re-synchronization patterns each having an n-byte length and indicating a data delimiter, a part of the data mark pattern is missing. When the detection fails, the detection of the first resynchronization pattern following the data mark pattern is used as a starting point, and the data string is m + n.
A binary signal reproduction method characterized in that reproduction is started by a signal delayed by bytes. 2. The start of reproduction is started from timing detection by majority logic operation of the first resynchronization pattern and a data mark pattern from a signal obtained by delaying the data string by m + n bytes. Claim 1
Binary signal reproduction method described. 3. A second resynchronization in which the start of the reproduction follows the data mark pattern when a part of the data mark pattern and a part of the first resynchronization pattern are missing and detection is unsuccessful. 2. The reproduction according to claim 1, wherein the reproduction is started by a signal having the pattern detection as a starting point and the data string delayed by 2 (m + n) bytes.
Value signal reproduction method. 4. The reproduction starts when the second resynchronization pattern and the data string are delayed by m + n bytes and the first resynchronization pattern and the data string are delayed by 2 signals.
4. The binary signal reproducing system according to claim 3, wherein a timing detection by a majority logic operation with a data mark pattern from a signal delayed by (m + n) bytes is used as a starting point.