JPS6292170A - Data recording and reproducing device - Google Patents

Abstract

PURPOSE:To attain the reading/reproduction of a data by selecting the pattern of a reproduced synchronizing signal as a pattern inexisting in a data and recording the result and detecting the reproduced synchronizing signal from a synchronizing signal and the data respectively so as to use the detected reproduced synchronizing signal. CONSTITUTION:The pattern of the reproduced synchronizing signal is selected as a pattern 30 inexisting in the data and in detecting the reproducing synchronizing signal from the data stored in a bit memory 54, when no read error exists in an input read signal from a terminal 49, the reproducing synchronizing signal is not detected from the data and the reproduced synchronizing signal by a microprocessor 59 is detected easily and accurately. As the pattern of the reproduced synchronizing signal, a 11-bit pattern, e.g., 7 consecutive pieces of 0s, next one 1, next two pieces of 0s and next one 1, may be arranged in any location of the reproduced synchronizing signal in, e.g., 16-bit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data recording/reproducing device, and in particular to resynchronization of data in a device that records and reproduces data serially, such as an optical disk device or a magnetic disk device. The present invention relates to a device for detecting a signal.

[Behind the scenes of invention]

If a decoder that starts decoding with a synchronization signal indicating the start position of data experiences a timing shift due to noise or the like, all subsequent data will be decoded incorrectly. To prevent this, conventionally, a resynchronization signal indicating a break is inserted into the data, and the resynchronization signal returns the decoder timing to normal, thereby limiting errors caused by timing deviations to only the specific section in which they occur. A recording/reproducing apparatus is known (for example, Japanese Patent Laid-Open No. 161111/1983). The above resynchronization signal is as described in Japanese Patent Application Laid-Open No. 58-161111,
In order to prevent erroneous detection, a pattern is selected such that a resynchronization signal is not detected at timings before and after a normal resynchronization signal detection position.

However, when reading a data block, if the synchronization signal indicating the reading start position cannot be detected, and when the resynchronization signal in the data is detected and the data block is read, the resynchronization signal pattern is also applied to the data itself. This poses a problem in that it may be difficult to accurately detect the resynchronization signal.

[Purpose of the invention]

An object of the present invention is to provide a data recording and reproducing device that can easily detect a resynchronization signal and read a data block when a synchronization signal indicating a reading start position cannot be detected when reading a data block. There is a particular thing.

[Summary of the invention]

In order to achieve the above object, the data recording/reproducing device according to the present invention selects and records a resynchronization signal pattern that does not exist in the data, and detects the resynchronization signal separately from the synchronization signal and the data. The feature is that data is read and reproduced using the detected resynchronization signal.

[Embodiments of the invention] Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block system diagram of an embodiment of the main part of the recording system of the apparatus of the present invention. In the figure, pie 1 to data 10 are set in a register 12 by a clock pulse A (denoted as CLKA) from an input terminal 11. The byte data set in the register 12 is supplied in parallel to the shift register 13, where the clock pulse B (C
LKB) is shifted by the modulation circuit 15 in series.
supplied to After the shift register 13 has shifted eight times, the next byte data 10 is set in the register 12 by CLKA. Thereafter, the same operation as above is repeated, and byte data is serially and continuously supplied to the modulation circuit 15.

The modulation circuit 15 converts the input data into two signals as shown in FIG.
-7 modulation and encoded data, a synchronization signal, and a resynchronization signal are output to the output terminal 16. In FIG. 2, item numbers are assigned to mutually different patterns of 2 to 4 bits of input data (for example, item number 1 is rlO
J, item number 2 is “010”, item number 3 is roloJ). The combination of output items 1 to 7 of the modulation circuit in FIG. ” is 2
, and then one “1”, an 11-bit pattern [
00000001001J does not exist. Therefore, in order to use this non-existent pattern as a resynchronization signal, the output of the resynchronization signal writing position detection circuit 17 is supplied to the modulation circuit 15 as shown in FIG. 1, and the output write data of the modulation circuit 15 is modified. and output to the output terminal 16.

FIG. 3 shows the data recording format of one block on the optical disk medium, and the 10th part 21 is a part where a number indicating the position of the block on the optical disk medium is recorded. The synchronization signal 22 is a signal indicating the data start position. Between each of the n+1 pieces of data 23-1 to 23-(n+1),
Resynchronization signals 24-1 to 24-n for resynchronizing the reading circuit during data reading are arranged at n positions. The resynchronization signals 24-1 to 24-n are selected to have a 16-bit pattern, as shown at 30 in FIG. 4, and include the 11-bit pattern described above.

FIG. 5 shows a block system diagram of an embodiment of the reproduction system of the apparatus of the present invention. A read signal from a read head (not shown) is supplied to a variable frequency oscillator (VFO) 51 through an input terminal 49 and a read amplifier 50, respectively, and the VFO clock 6
2 and a read signal 63 synchronized with this is output.

A read start signal 64 from the microprocessor 59 is supplied through a gate circuit 61 to a synchronization signal detection circuit 52 and a resynchronization signal detection circuit 53, respectively, and these circuits 52 and 53 start operating, respectively. The synchronizing signal detection circuit 52
A synchronization signal is detected using the FO clock 62 and the read signal 63, and when a synchronization signal is detected, the demodulation circuit 55
starts the resynchronization signal detection circuit 53 and outputs the signal 65 to send the detection result of the synchronization signal to the microprocessor 59.
Report to.

The resynchronization signal detection circuit 53 is supplied with the VFO clock 62 and a read signal 63 synchronized therewith, and detects a resynchronization signal in the read signal. If a resynchronization signal is detected, the resynchronization signal is sent to the demodulation circuit 55. Output the signal and demodulate circuit 5
5 recovers the synchronization shift of the demodulation circuit 55 caused by the phase shift caused by the VFO 51. data memory 56
stores the byte data output from the demodulation circuit 55.

The FCC circuit 57 corrects error data in the output from the demodulation circuit 55 and the data stored in the data memory 56 . The data after the modification IE is sent as the final read data to the host device (not shown) via the output terminal 68.

If the bit memory 54 cannot detect the same signal, it starts storing the read signal 63 in synchronization with the VF◯ clock 62 using the signal 65. The data stored in pin 1-memory 54 is transferred to microprocessor 9 by signal 66.
can be read. The microprocessors 5 operate according to control commands from the memory 60, read data stored in the bit memory 54 in response to a signal 66, and determine in which position in the bit memory 54 the resynchronization signal is stored.
It is also determined which resynchronization signal among the resynchronization signals 24-1 to 24-n shown in FIG. 3 the first detected inter-page lll1 signal is. With the above determination, the microprocessor J-59 can add the synchronization signal 22 to the head of the data in the bit memory 54, and further correct the resynchronization signal due to a read error.

The timing generation circuit 58 determines the timing for reading data from the bit memory 54 and the synchronization signal detection circuit 52. Re-synchronization signal detection circuit 53. The timing of the demodulation circuit 55 is generated. The timing generation circuit 58 is activated by the signal 67 from the five microprocessors, and the synchronization signal detection circuit 52 and the resynchronization signal detection circuit 53 are activated, and in the same way as reading data from the output signal of the VFO 51, Data is read by the microprocessor 59 based on the outputs of the timing generation circuit 58 and the bit memory 54.

According to this embodiment, the pattern of the resynchronization signal is shown in FIG.
By selecting a pattern that does not exist in the data, as shown by 0, when detecting a resynchronization signal from the data stored in the bit memory 54, if there is no reading error in the input read signal of the terminal 49, The resynchronization signal is not detected in the data, and the microprocessor 59 can easily and accurately detect the resynchronization signal.

Note that the pattern of the resynchronization signal is not limited to the above example;
An 11-bit pattern of 1, then 2 rOJs, then 1 1 may be placed anywhere in the 16-bit resynchronization signal, for example. Furthermore, although it does not follow the 2-7 modulation method, it is a pattern in which there is only one rOJ between "1" and "1", or "0" between "1" and "1".
It is also possible to use a pattern having 8 or more as a resynchronization signal.

〔Effect of the invention〕

As described above, according to the present invention, the synchronization signal cannot be detected;
When performing a read operation by detecting a resynchronization signal in a bit memory, the resynchronization signal can be detected easily and accurately, and the data reliability during the above read operation can be improved. It is something that you have.

[Brief explanation of drawings]

Fig. 1 is a block system diagram showing an embodiment of the main part of the recording system of the present invention, Fig. 2 is a diagram explaining the data modulation method, and Fig. 3 is a diagram showing one block of data on the optical disk medium. FIG. 4 is a diagram showing an embodiment of the reproduction synchronization signal pattern in the recording format shown in FIG. 3; FIG. 5 is a block diagram showing an embodiment of the reproduction system of the apparatus of the present invention. It is.

Claims (1)

[Claims] A recording medium having a data block composed of encoded data, a synchronization signal for indicating the start point of the data, and a resynchronization signal discretely arranged in the data for resynchronizing after the start of data reading. In a recording and reproducing apparatus for recording and reproducing data, a means for selecting and recording a pattern of the resynchronization signal as a pattern that does not exist in the data, and a means for distinguishing the resynchronization signal from the synchronization signal and the data, respectively. What is claimed is: 1. A data recording and reproducing apparatus comprising: detecting means, and reading and reproducing data based on the detected resynchronization signal.