JPH0419875A - Information recording and reproducing device - Google Patents

Abstract

PURPOSE:To shorten the processing time of a verify check by delaying a recording data in order to coincide with a reproducing data in timing and comparing afterward both data. CONSTITUTION:A DM detecting signal, the recording data and a recording clock are received by a shift register 3, and its shift operation is commenced by the DM detecting signal, and then the recording data is shifted at plural stages by the recording clock. By a selector 5 based on an output of a latch circuit 11, the recording data that is coincident with the reproducing data in timing is selected out of outputs shifted stepwise by the shift register 3, and is outputted to an exclusive-or circuit (EOR circuit) 13. The recording data selected by the selector 5 and the reproducing data separated by a data separator 9 are compared with each other in a unit of bit by the EOR circuit 13. By this method, the verify check can be performed at high speed without needing a RAM but in about real time.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an information recording and reproducing device that records and reproduces information using a recording medium such as an optical disk, and in particular, an information recording and reproducing device that records and reproduces information using a recording medium such as an optical disk. This invention relates to a data verification check device that checks whether recording has been completed.

[Prior Art] Conventionally, optical disks and magneto-optical disks (hereinafter collectively referred to as disks) have a large storage capacity, but are known to have a high error rate. Therefore, immediately after data is recorded on a disc, a verify check process is performed to reproduce the recorded data and verify whether or not the data was recorded correctly.

This verification check process generally involves holding the data string to be recorded in a memory such as RAM, and comparing this held data with the data string played back immediately after recording.
The error part was detected.

[Problems to be Solved by the Invention] However, in such a conventional verify check method, in order to compare data held in memory with data reproduced immediately after recording, an expensive RAM for data storage is required.
Not only is this necessary, but it is also necessary to wait until the data held in memory is played back.As a result, continuous data recording processing cannot be performed, which is an obstacle to speeding up the process.

The present invention was made with attention to such circumstances, and
The purpose is to provide an information recording/reproducing device which uses a simple circuit and can perform a verification check at high speed.

[Means for Solving the Problems 1] In order to achieve the above object, there is provided a means for delaying the recorded data so that the timing matches the reproduced data reproduced after being recorded on a recording medium, and the delayed recorded data and the There is provided an information recording and reproducing apparatus characterized by having means for comparing reproduced data and means for counting a mismatched portion between the two pieces of data based on the comparison result.

Effect] According to the present invention, by delaying the recorded data so that the timing matches the reproduced data and comparing the subsequent data, a verification check can be performed at high speed almost in real time without requiring a RAM. This is how it was done.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, a driver 1 is a drive circuit that drives a recording section such as an optical head in order to record record data on a disk (not shown). The DM detector 2 is a circuit that detects a DM (data mark) included in a recorded data string, and sends a detection signal to a shift register 3 and a counter 4.
Output to.

DM is located at the beginning of the recording data string and indicates the beginning of the data string. Shift register 3 is D
Upon receiving the M detection signal, recording data, and recording clock, a shift operation is started by the DM detection signal, and the recording data is shifted in multiple stages by the recording clock. In this embodiment, the shift register 3 shifts in four stages as shown as W-DATAO~3, and outputs the data shifted in stages according to the recording clock.

The preamplifier 6 is an amplifier that amplifies the signal reproduced immediately after recording data on the disk, and the peak detector 7 is a data reproducing circuit that detects the peak point of the reproduced signal and reproduces the reproduced signal into the original recorded data. be. The PLL circuit 8 is
The data separator 9, which is a circuit that creates a read lock from the data reproduced by the peak detector 7, is a circuit that separates the outputs of the peak detector 7 and the PLL circuit 8 into read data and read lock. The read data and read lock separated here are output to a control section (not shown).

The synchronization unit 10 is a circuit that creates a synchronization clock that synchronizes the recording clock and the read lock of the PLL circuit 8. This synchronization clock is output to the counter 4 and an error pulse generation circuit to be described later. The counter 4 mentioned above is
This counter starts counting the clock output from the synchronization section 10 in response to the DM detection signal of the DM detector 2.

The latch 11 latches the count value of the counter 4, and its latch timing is determined by the latch clock output from the 0M detector 12.

That is, the 0M detector 12 includes the data separator 9 and the PLL circuit 8.
The above-mentioned DM receives the read data and read lock from
Similar to the detector 2, DM is detected from the read data.

Therefore, the latch 11 latches the count value of the counter 4 at the timing of the DM detection signal of the 0M detector 12, and outputs the latch result to the selector 5.

The selector 5 is a selection circuit that selects one of the outputs shifted in stages by the shift register 3 based on the output of the latch 11. In this case, the selector 5 selects recording data whose timing matches the reproduced data based on the latch result of the latch 11, and outputs it to an exclusive OR circuit (hereinafter abbreviated as EOR circuit) 13.

The EOR circuit 13 is a circuit that compares the recorded data selected by the selector 5 and the reproduced data separated by the data separator 9 on a bit-by-bit basis. The error pulse generation circuit 14 is a circuit that receives the output from the EOR circuit 13 and the synchronization clock of the synchronization section 10, and outputs a mismatch signal between recorded data and reproduced data. Further, the error counter 15 is a circuit that counts mismatch signals. This counting operation is started by a latch signal from the latch 11, and the count result is output to a control section (not shown).

Next, the operation of this embodiment will be explained in detail with reference to the time chart shown in FIG. 2. FIG.
), FIG. 2(b) is the recording clock (W-CLK). At the beginning of the recording data, a data mark pattern signal is included, as shown as DMP in the figure. This recording data is recorded onto the disk by driving the driver 1. FIG. 2(c) shows the DM detection signal of the DM detector 2, that is, the detection signal when the first DMP of the recorded data is detected. In response to this detection signal, the counter 4 starts counting the synchronous clock as shown in FIG. 2(d). Further, the shift register 3 similarly starts the shift operation of recording data in response to the DM detection signal.

The output of the shift register 3 is shown in FIGS. 2(g) to 2(i). In this embodiment, the recording data is sequentially shifted in four stages by the recording clock, and each output is sent to the selector 5, as shown as W-DATAO~3. Figure 2 (
m) indicates a synchronization clock output from the synchronization section 10,
The counter 4 counts this synchronous clock as shown in FIG. 2(d). Further, FIG. 2(h) shows the reproduced data (R-DATA) separated by the data separator 9.

Naturally, the reproduced data lags slightly behind the recorded data. The DM detector 12 detects the DMP at the beginning of the reproduced data, and outputs the detection signal to the latch 11 as a latch signal (LATCH-CLK) as shown in FIG. 2(e).

The latch 11 latches the count value of the counter 4 using the latch signal, and outputs the result to the selector 5. In this embodiment, as shown in FIG. 2(d), the count value "2" is used.
is latched and output to the selector 5. That is, the counter 4 and the latch 11 detect the delay time between recorded data and reproduced data using the DMP as a reference, and output the detection result to the selector 5. The selector 5 receives the output of the latch 11 and selects data whose timing matches the reproduced data from among the outputs of the shift register 3. That is, data matching the delay amount of the reproduced data is selected from among the data obtained by shifting the recorded data in a stepwise manner. In this embodiment, the selector 5 is configured as W-D as shown in FIG. 2(f).
ATA 2 is selected. Thereby, the recorded data and the reproduced data are outputted to the FOR circuit 13 in a state where the timings match.

The EOR circuit 13 performs an exclusive OR operation on the recorded data and the reproduced data, and outputs the signal shown in FIG. 2 (1) as a result. In this example, the playback data (k> shown in FIG.
R-DATA) includes defects A and B caused by disk defects.

Defect A is a bit data that should originally be here, but is missing, and defect B is a bit data that is not originally there, but is caused by noise or the like.

The error pulse generator 14 receives the output of the EOR circuit 13 and the synchronization clock, and outputs a mismatch signal as shown in FIG. 2(n). That is, using the synchronous clock, the difference portion between the recorded data and the reproduced data is extracted from the comparison data of the EOR circuit 13, and a mismatch signal for each different bit is output. The error counter 15 counts the mismatch signals, as shown in FIG. 2(0). In this example, as described above, since defects A and B are different bits, the mismatch signals output in response to these are counted. Note that the error counter 15 is connected to the latch 11 as shown in FIG. 2(p).
The counting operation starts at the output timing of the latch signal. Further, the count result of the error counter 15 is output to a higher-level control unit (not shown), and a pass/fail determination is made based on the count result.

In the above embodiments, the verification check device is explained using an optical disk, a magneto-optical disk, etc. as a recording medium, but the verification check device is not limited to this (such as a magnetic disk, a floppy disk, or a magnetic tape). Of course, it can also be applied to a verify check device.Also, based on the DM at the beginning of recorded data,
Although the delay amount of reproduced data has been detected, in a recording medium that is managed on a sector-by-sector basis, an SM (sector mark) signal indicating the beginning of a sector may be detected and used as a reference.

[Effects of the Invention] As explained above, according to the present invention, the recorded data is delayed so that the timing matches that of the reproduced data, and the subsequent data is compared, so that the delay time of the reproduced data with respect to the recorded data is substantially reduced. Verification checks can be performed in real time with only a small increase in time. Therefore,
Since there is no need to wait for data reproduction as in the past, there is an effect that the verification check processing time can be significantly shortened compared to the past.

Moreover, not only is an expensive RAM not required, but also a verification check can be performed at high speed by simply providing a simple data delay means.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIGS. 2(a) to 2(p) are time charts showing the operation of the embodiment. 1... Driver, 2, 12... DM detector, 3...
・Shift register, 4... Counter, 5... Selector, 9... Data separator, 10... Synchronization section, 11.
...Latch, 13...EOR circuit, 14...Error pulse generation circuit, 15...Error counter. Agent Patent attorney Seki Yamashita Heisen Relationship Patent applicant name (100) Canon Co., Ltd. 4, agent 〒1
05 ffi 03 (431) 5゜6゜Date of amendment order August 28, 1999 Column for brief explanation of drawings of the specification subject to amendment 7゜Contents of amendment Page 1 2 of the specification, line 4 [ Figure 2 (a) (p)'' is corrected to ``Figure 2''.

Claims (2)

[Claims] (1) For playback data that is played back after being recorded on a recording medium,
It is characterized by comprising means for delaying the recorded data so that the timings match, means for comparing the delayed recorded data and the reproduced data, and means for counting the mismatched portion of the two data from the comparison result. Information recording and reproducing device. (2) The delay means includes means for shifting the recorded data in multiple stages, means for detecting the amount of delay between the recorded data and the reproduced data, and based on the detection signal, reproduced data and timing are selected from the output of the shifting means. 2. The information recording and reproducing apparatus according to claim 1, further comprising means for selecting data in which the data coincide with each other.