JPH05234254A - Threshold level decision circuit - Google Patents

Abstract

PURPOSE:To reduce error occurrence probability by deciding a threshold level so as to always keep the maximum margin in the direction of amplitude even if a phase of a reproducing clock is deviated. CONSTITUTION:Reference data for deciding a threshold level is recorded in a disk 100. A reproducing RF signal from an optical head 2 is clamped for every segments in a clamping circuit 11, and converted to a digital signal in a A/D converter 12, also waveform equalization is performed in a equalizer 13 so as to approach a shape of a cosine filter adapted to PR (1, 1) and it is supplied to a data detecting circuit 14 adopting PR (1, 1). Levels SL and SH required for three values sampling in the detecting circuit 14 is decided in a threshold decision circuit 15. Plural signals which regulate amplitude direction of eye of an eye pattern are obtained from the reproduced RF signal corresponding to the reference data in the decision circuit 15, the level SL and SH are decided so as to locate at the center of eye.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a threshold level determining circuit in a partial response applied to data detection in a reproducing system such as a magneto-optical disk.

[0002]

2. Description of the Related Art Due to high density recording on an optical disk, a method of applying a partial response to data detection has been increasing. The partial response positively uses intersymbol interference and has an advantage that data can be detected with a sufficient phase margin even when high density recording is performed. Among them, the partial response class 1-PR (1,1) is often adopted from the optical MTF.

When data is detected by applying a partial response, it is necessary to determine a threshold level required for extracting three values.

Here, the principle of partial response (duobinary) will be described. Recording timing and 180 °
The reproduced RF signal in the shifted phase is divided into three parts H, M, L by the combination of the bit strings Bn, Bn + 1 (see FIG. 9). Therefore, one between H and M, one between M and L
If one slice level is decided, three values of H, M and L can be detected. As a result, the combination of Bn and Bn + 1 is known, and the bit string is determined by reading continuously.

[0005]

FIG. 10A shows a reproduction RF.
The eye pattern of the signal is shown, and RFH, RFM, and RFL described on the left side correspond to H, M, and L, respectively. As shown in FIG. 9B, when the phase of the reproduction clock PCK is proper, the threshold levels SL and SH are simply used by using the values of 1/4 and 3/4 of RFH.
Can be determined as follows.

SL = RFH × 1/4 SH = RFH × 3/4 However, if the phase of the reproduction clock PCK is shifted as shown in FIG. 6C, the center of the eye in the amplitude direction moves, and SL, S
If H is fixed to the above value, the margin in the amplitude direction cannot be maximized. As a result, the phase margin of the reproduction clock PCK is narrowed and the error occurrence probability is increased.

Therefore, in the present invention, the margin in the amplitude direction is always maximized even if the phase of the reproduced clock is deviated, and the error occurrence probability is reduced.

[0008]

According to the present invention, when determining a threshold level for data detection in a partial response, a reproduced signal from a reference area is sampled at a plurality of timings to regulate the eye amplitude direction of an eye pattern. A plurality of signals are obtained, and the threshold level is determined so as to be located at the center of the eye based on the plurality of signals.

[0009]

When the phase of the reproduction clock is deviated, the sampling timing of the reproduction signal from the reference area changes, and the values of a plurality of signals that regulate the eye amplitude direction also change. Therefore, the threshold levels SL and SH are determined so that they are always located at the center of the eye, and the margin in the amplitude direction is always the maximum. As a result, the phase margin of the recovered clock is widened and the error occurrence probability is reduced.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. This example is an example applied to a magneto-optical disk reproducing apparatus.

In the figure, 1 is a spindle motor, and the magneto-optical disk 100 is rotationally driven by the motor 1 at a constant angular velocity. Recording data is recorded on the disc 100 by being modulated into NRZI series data. Although not described, a well-known sample servo system is adopted as the servo system of the disk 100.

The signal reproduced by the optical head 2 from the disk 100 is supplied to the matrix amplifier 3.
The reproduction RF signal (sum signal) output from the amplifier 3 is supplied to the PLL circuit 5 via the clamp circuit 4. PLL
In the circuit 5, a reproduction clock PCK synchronized with the reproduction signal from the clock pit of the servo byte SB preformatted on the disk 100 is formed.

The output signal of the clamp circuit 4 is A / D.
The signal is converted into a digital signal by the converter 6 and supplied to the PLL circuit 5, and the PLL circuit 5 in the segment synchronization signal SGD.
Is formed. The reproduction clock PCK output from the PLL circuit 5 is supplied to the A / D converter 6 for sampling.

The output signal of the A / D converter 6 is supplied to the address decoder 7. Disk 1 for decoder 7
The sector synchronization signal SCD is formed based on the reproduction signal from the address area preformatted to 00. The reproduction clock PCK output from the PLL circuit 5 is also supplied to the decoder 7.

A reproduction clock P formed by the PLL circuit 5
CK, the segment sync signal SGD, and the sector sync signal SCD formed by the decoder 7 are the timing generator 8
Is supplied to.

The reproduced RF signal (difference signal) output from the amplifier 3 is supplied to the clamp circuit 11. The clamp circuit 11 performs the clamp process on all the segments, and removes the low frequency interference generated by the fluctuation of the reflected light from the disc 100.

The reproduction RF signal clamped by the clamp circuit 11 is supplied to the A / D converter 12 and converted into a digital signal, and then supplied to the digital equalizer 13. The A / D converter 12 and the equalizer 13 have P
A reproduction clock PCK formed by the LL circuit 5 is supplied.

The pass frequency characteristic of the equalizer 13 is shown in FIG.
It is set so as to have a cos characteristic as shown in A, and the reproduced RF signal is made to be as close as possible to the partial response (1, 1) as shown in FIG.

The reproduced RF signal output from the equalizer 13 is a partial response class 1-PR (1,
The data is supplied to the data detection circuit 14 that performs the data detection of 1), and is also supplied to the threshold determination circuit 15 that determines the threshold levels SL and SH necessary for extracting three values in the data detection circuit 14. The reproduction RF signal output from the PLL circuit 5 is supplied to the data detection circuit 14 and the threshold determination circuit 15.

In the decision circuit 15, as shown in FIG. 10, RF11 and RF1 which limit the amplitude direction of the eye of the eye pattern.
Threshold level S from the values of 0, RF01, RF00
L and SH are determined. RF11, RF10, RF01, RF
The value of 00 can be obtained, for example, from a reproduction RF signal of a recording pattern of two or more consecutive pits and an isolated pit.

Although not described above, FIG. 3 shows the sector format of the disc 100, in the reference area,
For example, reference data having a pattern as shown in FIG. 4C is recorded. A in the figure is a reproduction RF signal reproduced corresponding to the reference data, and B in the figure is a recording clock WC.
K and D in the figure are reproduction clocks PCK.

In the decision circuit 15, RF11, RF10 ', RF10 ", RF0 sampled from the reproduced RF signal.
Threshold levels SL and SH are determined from the values of 1 ', RF01 ", RF00', and RF00" as in the following equation.
As a result, even if the phase of the reproduction clock PCK is deviated, the threshold levels SL and SH are always determined at the eye center position. max (A, B) means that the larger one of A and B is taken, and min (A, B) means that the smaller one of A and B is taken.

SL = {max (RF00 ', RF00 ") + min
(RF01 ′, RF01 ″)} / 2 SH = {RF11 + max (RF10 ′, RF10 ″)} / 2 Here, the calculation of max (A, B) and min (A, B) is required for the reproduction clock PCK. This is because the sampling positions of the values of RF00, RF01, and RF10 differ depending on whether the phase shifts to the front or back.

For example, when the phase of the reproduction clock PCK is shifted forward as shown in FIG.
By adopting 0 ″, RF01 ″, and RF10 ″, the threshold levels SL, SH are determined by the following equations.
Indicates a reproduction RF signal.

SL = (RF00 ″ + RF01 ″) / 2 SH = (RF11 + RF10 ″) / 2 Fig. 6 is a diagram showing a specific configuration of the threshold decision circuit 15. In the figure, the reproduction RF output from the equalizer 13 is shown. The signal is supplied to the registers 151 to 157. The reproduction clock PCK is supplied to these registers 151 to 157, and RF11,
RF10 ', RF10 ", RF01', RF01", RF00 ',
The enable signals EN1 to EN7 are supplied at the timing when the value of RF00 ″ is sampled (see FIGS. 4E to 4E).
K). The enable signals EN1 to EN7 are generated by the timing generator 8.

The value of RF11 output from the register 151 is supplied to the adder 158. Registers 152 and 153
The output values of RF10 'and RF10 "are supplied to the maximum value selection circuit 159, and the larger value is output as the value of RF10 and supplied to the adder 158.

In the adder 158, the values of RF11 and RF10 are added, and the added signal is supplied to the 1/2 coefficient unit 160 to obtain the threshold level SH. Coefficient unit 160
The threshold level SH output from the output is output via the averaging circuit 161.

R output from the registers 154 and 155
The values of F01 ′ and RF01 ″ are supplied to the minimum value selection circuit 162, and the smaller one is output as the value of RF01, and the adder 1
63. The values of RF00 ′ and RF00 ″ output from the registers 156 and 157 are supplied to the maximum value selection circuit 164, and the larger value is output as the value of RF00 and supplied to the adder 163.

In the adder 163, the values of RF01 and RF00 are added, and the added signal is supplied to the 1/2 coefficient unit 165 to obtain the threshold level SL. Coefficient unit 165
The threshold level SL that is output is output via the averaging circuit 166.

Although not described above, the reference data as shown in FIG. 4C is recorded in each sector a plurality of times, for example. In the averaging circuits 161, 166 described above, the threshold levels SH, SL found corresponding to each reference data are averaged. As a result, it is possible to prevent the reliability from decreasing due to the influence of defects or the like.

In the circuit of FIG. 6, the averaging is performed in the state of the threshold levels SH and SL, but the averaging may be performed in the previous stage.

Further, the maximum value and the minimum value selection circuit 159,
Although 162 and 164 are used, a pit for determining the phase delay or advance of the reproduction clock PCK is prepared, and based on this pit (for example, by comparing the left and right sizes of isolated pits, the phase delay or advance is determined Can be determined), RF1
0'and RF10 "(RF01 'and RF01", RF00' and RF0
0 ") may be uniquely selected. For example, when the phase is advanced, RF10",
RF01 ″ and RF00 ″ are selected.

Returning to FIG. 1, the threshold decision circuit 1
The threshold levels SL and SH determined by 5 are supplied to the data detection circuit 14. The data detection circuit 14 uses the threshold levels SL and SH to perform ternary sampling. From the data detection circuit 14, N
An RZ signal is output and is used as reproduction data Dout.

FIG. 7 shows a specific structure of the data detection circuit 14. In the figure, the reproduction RF signal is the register 14
1 and are sequentially latched in synchronization with the reproduction clock PCK. The output signal of the register 141 is the comparator 14
2, 143 is supplied to the A-side input terminal. Comparator 14
Threshold levels SL and SH are supplied to the B-side input terminals of 2 and 143, respectively.

At the output side of the comparators 142 and 143, if the level VA of the reproduction RF signal supplied to the A side is higher than the threshold levels SL and SH supplied to the B side, respectively, a signal of logical level "1". And vice versa, a signal of logical level "0" is obtained.

The output signals of the comparators 142 and 143 are supplied to the exclusive OR gate 144. Gate 14
From 4, the logical level "0" is output as the detection data (NRZ data) when VA <SL or VA> SH, and the logical level "1" when SL <VA <SH.

In this example, RF11, RF10 ', RF10 ", RF01', RF0 for controlling the amplitude direction of the eye of the eye pattern sampled by the reproduction clock PCK from the reproduction RF signal corresponding to the reference data.
The threshold levels SL and SH are determined so as to be located at the center of the eye based on the values of 1 ″, RF00 ′ and RF00 ″. In this case, the sampling timing changes when the phase of the reproduction clock PCK deviates, and RF11 and RF1
0 ', RF10 ", RF01', RF01", RF00 ', RF0
The value of 0 ″ also changes, and the threshold level is determined so that it is always located at the center of the eye (see FIG. 10).

Therefore, according to this example, the margin in the amplitude direction can always be maximized regardless of the phase shift of the reproduced clock, the phase margin of the reproduced clock is widened, the error occurrence probability is reduced, and the system reliability is improved. Can be raised.

In the above-mentioned embodiment, the reproduction RF signals from the pit portions where two or more consecutive pits are used are RF11 and RF.
The values of 10 'and RF10 "are obtained, but these values can also be obtained from the reproduced RF signal from a portion in which two or more consecutive pits are consecutive at two or more with a 1-bit interval. Reference data having a pattern as shown in FIG. 8C, for example, is recorded in the area.
A in the figure is a reproduction RF signal reproduced corresponding to the reference data, B in the figure is a recording clock WCK, and D in the figure is a reproduction clock PCK.

[0040]

According to the present invention, the threshold level is determined so as to be located at the center of the eye based on a plurality of signals that limit the amplitude direction of the eye of the eye pattern sampled from the reproduction signal from the reference area. It When the phase of the reproduction clock shifts, the sampling timing of the reproduction signal from the reference area changes,
The values of a plurality of signals that regulate the eye amplitude direction also change.
Therefore, the threshold level is always determined to be located in the center of the eye, the margin in the amplitude direction is always the maximum, the phase margin of the recovered clock is expanded, the error occurrence probability can be reduced, and the system reliability can be improved. ..

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment.

FIG. 2 is a diagram for explaining characteristics of a digital equalizer.

[Figure 3] Sector format (data format)
FIG.

FIG. 4 is a diagram showing a reproduction RF signal corresponding to reference data and various timings.

FIG. 5 is a diagram showing a reproduction RF signal and a reproduction clock corresponding to reference data when the phases are deviated.

FIG. 6 is a block diagram showing a specific configuration example of a threshold determination circuit.

FIG. 7 is a block diagram showing a specific configuration example of a data detection circuit.

FIG. 8 is a diagram showing another example of reference data.

FIG. 9 is a diagram for explaining the principle of partial response.

FIG. 10 is a diagram showing a relationship between a reproduced clock and an eye pattern.

[Explanation of symbols]

 1 Spindle Motor 2 Optical Head 5 PLL Circuit 6, 12 A / D Converter 7 Address Decoder 8 Timing Generator 13 Digital Equalizer 14 Data Detection Circuit 15 Threshold Determination Circuit

Claims (3)

[Claims] 1. When determining a threshold level for data detection in a partial response, a reproduction signal from a reference area is sampled at a plurality of timings to obtain a plurality of signals for regulating the eye amplitude direction of an eye pattern, A threshold level determining circuit for determining the threshold level so as to be located at the center of the eye based on the plurality of signals. 2. The reference area has at least two or more consecutive pits recorded therein and isolated pits recorded therein, and a reproduction signal associated with these pits is sampled at a plurality of timings. 1. The threshold level determination circuit described in 1. 3. In the reference area, at least two or more continuous pits are continuously recorded at two or more with a 1-bit interval, and isolated pits are recorded,
2. The threshold level determining circuit according to claim 1, wherein the reproduction signals related to these pits are sampled at a plurality of timings.