JP2000003550A - Circuit and method for detecting synchronizing signal of optical disk device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a detection circuit to perform a synchronous detection high in reliability and to reproduce a signal with an original correct format by changing or not changing the width of a window pulse when synchronous patterns can not be detected due to burst defects such as scratches or random defects such as small scratches and fingerprints on an optical disk. SOLUTION: When the synchronization detecting circuit 2 can not detect synchronous patterns because of burst defects due to scratches existing on the optical disk, a decoder 6 increases a decoded value S5. As a result, a window signal generating circuit 7 expands the width of a window pulse S7 gradually, the out of synchronism is hardly caused during a front protection operation and the synchronism is easily obtained even when the out of synchronism is caused. Moreover, even when the circuit 2 can not detect the synchronous patterns, the circuit 7 does not expand the width of the window pulse S7 when there is not a scratch detection signal in the envelope component of the reproduced signal of the optical disk. Thus, the reliability of the synchronization detection is enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization signal detecting circuit and method for an optical disk device, and more particularly, to an optical disk which is hard to be out of synchronization during a forward synchronization protection state even when a scratch is present on the disk, and is easily synchronized. The present invention relates to a synchronization signal detection circuit and method for an apparatus.

[0002]

2. Description of the Related Art In an optical disk device, a synchronization pattern included in a recording signal is detected (synchronization detection) so that the recording signal can be reproduced in an original correct format.

[0003] Among the information read from the optical disc,
There may be a case where the same pattern as the synchronization pattern happens to be present in the data portion which is not the synchronization pattern. The circuit for detecting the synchronization pattern detects the synchronization only during a period including a fixed time before and after the timing at which the synchronization pattern appears, in order to prevent a malfunction due to the appearance of such a pseudo pattern. This period is called a window period. Further, the occurrence position of the synchronization pattern is predicted from the number of channel bits constituting one frame (synchronization detection prediction). If the synchronization pattern cannot be detected, a pseudo synchronization pattern detection signal is generated and interpolated (particularly). See Japanese Unexamined Patent Publication No. Hei 10-50002).

In addition, a synchronization protection circuit is provided at the subsequent stage of the synchronization signal detection circuit, and after it is confirmed that the synchronization pattern is repeated several times in a predetermined cycle, it is determined that synchronization has been achieved for the first time. Also, once the synchronization is established, even if the synchronization pattern does not arrive at the predicted position of the predetermined repetition period thereafter, it is determined that the synchronization has been lost only if the synchronization does not arrive immediately and the predetermined number of times does not arrive. Forward protection is provided (see Japanese Patent Application Laid-Open No. 9-8793).

FIG. 5 shows a synchronizing signal detecting circuit using the above-described conventional technique. This synchronization signal detection circuit is provided in a signal processing unit of the optical disk device. In this synchronization signal detection circuit, a signal (serial data) recorded on an optical disk is read out, a synchronization detection circuit 102 detects a synchronization pattern that does not appear in modulated data through a window control circuit 101 composed of an AND circuit, and detects a synchronization pattern. If detected, the synchronization pattern detection pulse S1
01 is generated. In the frame counter 103,
By counting a reference signal (channel clock) reproduced from the optical disk, a synchronization pattern prediction pulse S102 is generated by assuming a prediction position of the next synchronization detection from the previous synchronization detection position. The synchronization pattern prediction pulse S102 is a count overflow output of the frame counter 103. If a defect in the synchronization pattern occurs due to a scratch on the optical disk and the synchronization pattern cannot be detected in the window and S101 is not output, the S102 is output. Are used as pseudo-synchronous pattern detection pulses. Then, the frame counter 103 generates a synchronization pattern detection pulse S101 and a synchronization pattern prediction pulse S
It is reset by the output of the OR circuit 111 which is the logical sum with the signal 102. The frame clock generation circuit 108 outputs the detection pulse S101 when the synchronization pattern detection pulse S101 is generated, and outputs the synchronization pattern prediction pulse S102 when the detection pulse S101 is not generated, thereby starting the data. Is generated.

[0006] The rear protection counter 104 is an AND circuit 1
09, the logical product of the synchronization pattern detection pulse S101 and the synchronization pattern prediction pulse S102 is counted up, that is, the detection pulse S101 and the prediction pulse S102.
Are simultaneously output, and when counting up to an arbitrarily set value, a count overflow output S103 is generated assuming that synchronization has been established (synchronization established state).

The front protection counter 105 uses the count overflow output S103 of the rear protection counter 104 as an enable signal, and outputs a synchronization pattern detection pulse S101 and a synchronization pattern prediction pulse S1 by the EXOR circuit 110.
The exclusive OR with 02 is counted up. That is, when synchronization is established, the synchronization pattern detection pulse S
When only one of the signal 101 and the synchronization pattern prediction pulse S102 is generated (synchronization protection state), it is counted up to perform the synchronization protection, and when it counts up to an arbitrarily set synchronization protection set number, the synchronization is lost. To generate a count overflow output S104 (hunting state). Based on the count overflow output S104, it is determined that synchronization has been lost, and the rear protection counter 104 is reset. Also, the forward protection counter 105
Is reset when the synchronization pattern detection pulse S101 is generated.

The timing generator 107 decodes the count value of the frame counter 103 and sends a fixed-width pulse S106 having a specific width arbitrarily set before and after the synchronization detection predicted position to the window signal generation circuit 106. Output. Window signal generation circuit 106
Generates a window pulse S107 from the pulse S106. The window signal generation circuit 106 receives the synchronization pattern detection pulse S101 and falls the pulse S106 from the timing generator S107 at the timing of the detection pulse S1.

In the OR circuit 112, the window pulse 10
7 and the output S104 of the forward protection counter 105 indicating an out-of-synchronization, and a window control circuit 101
To enter. When the output S104 occurs, the output S104
The window is widened very wide by the pulse width of 104, so that the synchronization pattern is detected and the synchronization is quickly drawn.

[0010]

The channel clock counted by the frame counter of the above-mentioned conventional synchronous signal detection circuit is generated by a PLL circuit. FIG. 6 is a diagram showing a configuration of a signal reproducing system of the optical disk device. FIG.
As shown in FIG.
The RF signal read out at 1 and generated by the RF amplifier 122 is subjected to noise removal and waveform equalization by the filter circuit 123. The RF signal is binarized by the data binarization circuit 124,
A PLL circuit 125 generates a channel clock synchronized with the channel bits from the digitized RF signal. After synchronization is obtained by the synchronization signal detection circuit 126, the signal is demodulated by the demodulation circuit 127.

In such a signal reproducing system, the PLL circuit 125 forcibly generates a channel clock even when a channel bit cannot be detected due to a burst defect such as a scratch on the optical disk. In such a case, the forcibly generated channel clock may be shifted from the channel bit timing. In this case, the position of the synchronization pattern prediction pulse generated by the frame counter, that is, the prediction position of the synchronization pattern is shifted as shown in FIG. As a result, the generation position of the window pulse is shifted, and it may happen that the synchronization pattern cannot be detected in the window. Therefore, it is impossible to perform highly reliable synchronization detection, and data cannot be reproduced in the original correct format.

In order to prevent this, it is conceivable to widen the width of the window pulse from the beginning after the synchronization is established. However, since the probability of erroneously detecting the synchronization pattern increases, this method is adopted. Can not. Exceptionally, when the signal of S104 indicating the above-mentioned out-of-synchronization is output, the width of the window pulse is very widened so that the synchronization pattern is reliably detected. However, since forward protection is performed, a period for confirming that synchronization cannot be detected a predetermined number of times at the position of the synchronization pattern prediction pulse is required before it is determined that synchronization is lost. Conventionally, although normal serial data can be read during this period, normal synchronization has not been achieved during this period. Therefore, during this period, the frame clock indicating the beginning of the data is not normal, the correct data section is not shown, and the incorrect data section is notified to the subsequent circuit, and the subsequent circuit processes the incorrect data. There was a problem.

An object of the present invention is to increase the width of a window pulse even when the position of a synchronization pattern prediction pulse is shifted due to a shift of a channel clock and the synchronization pattern cannot be detected. It is an object of the present invention to provide a method for detecting a synchronization signal of an optical disk device which enables detection and performs highly reliable synchronization detection.

Another object of the present invention is to provide a synchronization signal detecting circuit for performing the above method.

[0015]

According to the present invention, in a synchronous signal detecting method for detecting a synchronous pattern of an optical disk in a window, the synchronous pattern is detected due to a burst defect caused by a scratch existing on the optical disk. If this is not possible, the width of the window is gradually increased so that synchronization is less likely to be lost during the forward protection operation, and resynchronization is facilitated if synchronization is lost.

Such a method is implemented by a synchronous signal detecting circuit having the following configuration. That is, the synchronization signal detection circuit of the present invention reads a signal recorded on the optical disk of the optical disk device, and, based on the read signal and the window, detects a synchronization signal through a window control circuit. A frame counter that counts a reference signal reproduced from the optical disc from a previous synchronization detection position, and assumes a predicted position for the next synchronization detection, comprising: an output from the synchronization detection circuit; a count overflow output of the frame counter; A frame counter that is reset by the logical sum of the above, a timing generator that decodes a counter value of the frame counter to generate a timing of a window signal generation circuit described later, an output from the synchronization detection circuit, and a count overflow output of the frame counter. AND with and ,
This AND is counted, a rear protection counter reset by the front protection counter described later, and enabled by the count overflow output of the rear protection counter, reset by the output of the synchronization detection circuit, and output from the synchronization detection circuit. An exclusive OR with the count overflow output of the frame counter, a forward protection counter that counts the exclusive OR, and a decoder that decodes the count value of the forward protection counter;
An output of the timing generator is controlled by a logical product value of a decode value of the decoder and a flaw detection signal generated from an envelope component of the read signal,
A window signal generation circuit that generates a window pulse in association with the timing of the predicted position of synchronization detection, and an OR circuit that generates a logical sum of the window pulse and an overflow output of the forward protection counter to generate the window. Have.

[0017]

FIG. 1 is a circuit diagram showing an embodiment of a synchronization signal detection circuit according to the present invention. This synchronization signal detection circuit adds a decoder 6 for decoding the count value of the front protection counter to the detection circuit shown in FIG. 5, and further adds a decoder based on the output value S5 of the decoder 6 to the window signal generation circuit of FIG. Added the function to expand the width of window pulse. FIG. 2 shows the configuration of the window signal generation circuit 7 of FIG.

The configuration and operation of the synchronization signal detection circuit shown in FIGS. 1 and 2 will be described with reference to the timing chart of FIG.

In this synchronization signal detecting circuit, a signal (serial data) recorded on an optical disk is read out, and A
A synchronization pattern that does not appear in the modulation data is detected by a synchronization detection circuit 2 through a window control circuit 1 composed of an ND circuit, and when a synchronization pattern is detected, a synchronization pattern detection pulse S1 is generated.

FIG. 3 shows an example of the synchronization pattern detection pulse S1. In the figure, “Bit Slip Under”
"Bit Slip Over" indicates that the synchronization pattern in the serial data appears earlier than the expected position, and "Bit Slip Over" indicates that the synchronization pattern appears later than the expected position.
“Sync” and “Miss Trac” respectively indicate cases where the synchronization pattern cannot be detected due to a scratch existing on the optical disc.

The frame counter 3 counts the channel clock reproduced by the PLL circuit,
Assuming a predicted position for the next synchronization detection from the previous synchronization detection position, a synchronization pattern prediction pulse S2 is generated. The synchronization pattern prediction pulse S2 is a count overflow output of the frame counter 3. If a synchronization pattern defect occurs due to a scratch on the optical disk and the synchronization pattern cannot be detected in the window, the pseudo synchronization pattern detection is performed. Used as a pulse. Then, the frame counter 3 is reset by the logical sum of the synchronization pattern detection pulse S1 and the synchronization pattern prediction pulse S2 by the OR circuit 12. The frame clock generation circuit 9 generates a frame clock indicating the start of data by using the synchronization pattern detection pulse S1 and the synchronization pattern prediction pulse S2.

The rear protection counter 4 counts up the logical product of the synchronization pattern detection pulse S1 and the synchronization pattern prediction pulse S2 by the AND circuit 10, that is, counts up when the detection pulse S1 matches the prediction pulse S2. When the count value is m, when m is counted up to an arbitrarily set value, a count overflow output S3 is generated assuming that synchronization has been established (synchronization established state). FIG. 3 shows the timing of the output S3 when the setting value = 2. It rises to high (H) at m = 2.

The front protection counter 5 uses the count overflow output S3 of the rear protection counter 4 as an enable signal, and counts up the exclusive OR of the synchronization pattern detection pulse S1 and the synchronization pattern prediction pulse S2 by the EXOR circuit 11. That is, when only one of the synchronization pattern detection pulse S1 and the synchronization pattern prediction pulse S2 is generated when the synchronization is established (synchronization protection state), the counter is counted up to perform the synchronization protection and arbitrarily set. When counting up to the set number of synchronization protections, it is determined that synchronization has been lost. Count overflow output S
4 is generated (hunting state). FIG. 3 shows the timing of the output S4 when the synchronous protection set number = 4, where n is the count value. High (H) when n = 4
Standing up.

Based on the count overflow output S4, it is determined that synchronization has been lost, and the rear protection counter 4 is reset. The front protection counter 5 is reset when the synchronization pattern detection pulse S1 is generated. In FIG.
The front protection counter 5 is reset by the first synchronization pattern detection pulse A after "Miss Trac", and as a result, the output S4 immediately falls to low (L).

The decoder 6 decodes the count value n of the forward protection counter 5 and sends the value S5 to the window signal generation circuit 7. The decoder 6 is of a type that generates decode values shown in Table 2 below when the number of forward protection settings is generally 4i (i = 1, 2, 3,...).

[0026]

[Table 2] Here, α is a value that is a minimum unit when the width of the window pulse is expanded at the leading edge and the trailing edge, respectively.

In the example of FIG. 3, since i = 1, the decoded values are as shown in Table 3.

[0028]

[Table 3] Value of n Decode value n = 0, 4 → ± 0 n = 1 → ± α n = 2 → ± 2α n = 3 → ± 3α In the example of the synchronization pattern detection pulse S1 shown in FIG. Is shifted from the predicted position.
In the case of “ndr” and “Bit Slip Over”, the count value of the forward protection counter 5 becomes “1” and the decoded value ± α is output.

Also, “No Syn” having no synchronization pattern
Also in the case of "c", the count value of the forward protection counter 5 becomes "1" and outputs a decoded value ± α.

In the case of “Miss Trac”, the forward protection counter 5 counts “1”, “2”,
"3" and "4" are output. As a result, the decoder 6 sequentially outputs ± α, ± 2α, ± 3α, ± 0. These decoded values are sent to the window signal generation circuit 7.

On the other hand, the timing generator 8 decodes the count value of the frame counter 3 and outputs a fixed-width pulse S6 having a specific width arbitrarily set before and after the synchronization detection predicted position as a center. 7
Output to The pulse S6 shown in FIG. 3 has a constant width T. The width of the pulse indicated by B is reduced because the frame counter 3 is reset by the synchronization pattern detection pulse S1.

As shown in FIG. 2, the window signal generation circuit 7 performs a logic operation between the output value S5 of the decoder 6 and the flaw detection signal generated from the envelope component of the RF signal generated by the RF amplifier 122 shown in FIG. The product is formed by the AND circuit 15, and the output pulse S6 of the timing generator 8 is controlled by the logical product to generate a window pulse S7 having an increased pulse width. The logical product of the window detection signal and the flaw detection signal is obtained when the width of the window pulse S7 is increased in the synchronous protection state due to a factor other than the burst defect such as a flaw, for example, a random defect called a fingerprint on the light source irradiation surface of the optical disk. This is because there is a high possibility that the synchronization detection circuit 2 will erroneously detect the synchronization pattern, and it is necessary to control only when a flaw detection signal is generated.

Here, a burst defect refers to a defect in which a flaw detection signal is output without reading correct data for a relatively long period of time due to a large scratch or dust on the optical disk, and a random defect refers to a burst defect. A defect in which correct data cannot be read for a relatively short period of time due to a small scratch or a fingerprint (fingerprint) as compared with a defect, but no flaw detection signal is output.

The decoded value S5 passed through the AND circuit 15,
The pulse S6 from the timing generator 8 is applied to a pulse width control circuit 16, and the control circuit 16
A window pulse S7 in which the leading edge and the trailing edge of are expanded by the decode value is generated.

FIG. 4 shows that the pulse width control circuit 16
When the pulse S6 having the width T is equal to the decoded value S5 ± α,
A window pulse S7 in which the leading edge and the trailing edge are respectively extended by α is shown. The width of this window pulse is (T
+ 2α). The window pulse expanded to this width is indicated by C in FIG. Similarly, when the decode value is ± 2α, the width of the window pulse is (T + 4α)
This window pulse is indicated by D in FIG. When the decoded value is ± 3α, the width of the window pulse is (T + 6α), and this window pulse is indicated by E in FIG.

When the decoded value is ± 0, the pulse S6
Are output from the control circuit 16 with the width T.

The window pulse S 7 output from the pulse width control circuit 16 is sent out through the gate circuit 17. This gate circuit is reset by the synchronization pattern detection pulse S1, and blocks the passage of subsequent pulses.
Therefore, as shown in FIG.
Falls to low (L) at the timing of the synchronization pattern detection pulse S1.

The window pulse S7 from the window signal generation circuit 7 is ORed with the output S4 of the forward protection counter 5 by the OR circuit 13 as shown in FIG. 1, and is used as a window (see FIG. 3). Given to. The reason for taking the logical sum is that it is necessary to increase the width of the window so that the next synchronization pattern can be reliably detected in a state where synchronization is lost. The F in the timing diagram of FIG. 3 shows the ORed and widened window. This window is displayed as “Miss Tra
c ”after the synchronous pattern detection pulse A is generated,
Row (L) is falling.

With the generation of the synchronous pattern detection pulse A,
The frame counter 3 is reset, counts up the channel clock, and generates a synchronization pattern prediction pulse S2 (shown by G in FIG. 3).

In the synchronization signal detection circuit described above,
Usually, the window pulse S7 is the same pulse as the pulse S6 (however, as shown in FIG. 3, the window pulse S7 falls to L when the synchronization pattern detection pulse S1 is generated). If the sync pattern cannot be detected in the window due to a defect in the sync pattern due to scratches on the optical disc,
The frame counter 3 outputs the synchronization pattern prediction pulse S2 as a pseudo synchronization pulse, counts up the front protection counter 5, and increases the value S5 of the decoder 6.

In this case, as described in the prior art,
The predicted position of the synchronous pattern may deviate from the position of the synchronous pattern due to the deviation of the channel clock due to a scratch on the optical disk. As a result, the position where the window pulse S7 is generated is shifted. As a result, if the width of the window pulse is unchanged, there is a possibility that the synchronization pattern cannot be detected in the window.

However, in the synchronous signal detecting circuit of the present invention,
Synchronization pattern cannot be detected and synchronization pattern detection pulse S1
Does not occur, the decoded value output from the decoder 6 increases. At this time, the window signal generation circuit 7 outputs a window pulse S7 in which the pulse width at the predicted position of the next synchronization pattern is changed to be wider than the initial set value by increasing the value S5 of the decoder 6. . When the synchronization pattern cannot be detected even when the width of the window pulse S7 is widened (synchronization protection state), the window signal generation circuit 7 further widens the width of the window pulse S7 at the predicted position of the next synchronization pattern. Output. That is, as the value S5 of the decoder 6 increases, the width of the window pulse S7 is sequentially increased at the predicted position of the next synchronization pattern. When the synchronization pattern can be detected by the synchronization detection circuit 2 with the width of the expanded window pulse S7, the front protection counter 5 is reset, and the width of the window pulse S7 becomes the initial set value T. By changing the width of the window pulse S7 in this manner, resynchronization can be performed even when synchronization cannot be detected due to a deviation of the window pulse due to a scratch on the optical disk.

In the above embodiment, the synchronous protection set number of the forward protection counter is set to 4, and the decode value is increased every time the count is incremented by 1. However, the decode value may be increased every set number of times in a certain range. Good. This example is shown in the following table for the case where the number of synchronization protection settings = 16.

[0044]

[Table 4] Value of n Decode value n = 0-3,16 → ± 0 n = 4-7 → ± α n = 8-11 → ± 2α n = 12-15 → ± 3α

[0045]

According to the present invention, when a synchronous pattern cannot be detected due to a burst defect such as a scratch on the optical disk, the width of the window pulse is changed, and when a synchronous defect cannot be detected due to a random defect such as a fingerprint, By keeping the width of the window pulse unchanged, highly reliable synchronization detection can be performed, and reproduction can be performed in the original correct format.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a synchronization signal detection circuit of the present invention.

FIG. 2 is a diagram illustrating a configuration of a window signal generation circuit of FIG. 1;

FIG. 3 is a timing chart for explaining the operation of the synchronization signal detection circuit.

FIG. 4 is a diagram showing expansion of a window pulse width.

FIG. 5 is a diagram showing a conventional synchronization signal detection circuit.

FIG. 6 is a diagram showing a configuration of a signal reproducing system of the optical disc device.

FIG. 7 is a diagram illustrating a state where the position of a synchronization pattern prediction pulse is shifted due to a shift of a channel clock.

[Description of Signs] 1 Window control circuit 2 Synchronous signal detection circuit 3 Frame counter 4 Back protection counter 5 Forward protection counter 6 Decoder 7 Window signal generation circuit 8 Timing generator 9 Frame clock generation circuit 10, 15 AND circuit 11 EXOR circuit 12, 13 OR circuit 16 Pulse width control circuit 17 Gate circuit 120 Optical disk 121 Pickup 122 RF amplifier 123 Filter circuit 124 Data binarization circuit 125 PLL circuit 126 Synchronous signal detection circuit 127 Demodulation circuit

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Claims (8)

[Claims] In a synchronization signal detecting method for detecting a synchronization pattern of an optical disk in a window, when the synchronization pattern cannot be detected due to a burst defect due to a scratch existing on the optical disk, the width of the window is reduced. A synchronization signal detection method characterized in that it is difficult to lose synchronization during forward protection operation by expanding in a stepwise manner, and it is easy to resynchronize when synchronization is lost. 2. The synchronization according to claim 1, wherein the width of the window is not increased when a synchronization pattern cannot be detected due to a random defect existing on a light source irradiation surface of the optical disk. Signal detection method. 3. The synchronous signal detecting method according to claim 2, wherein if there is no flaw detection signal generated from the envelope component of the signal reproduced by the optical disk, the defect is determined to be a random defect. 4. A synchronization signal detecting apparatus for detecting a synchronization pattern of an optical disk in a window, wherein when the synchronization pattern cannot be detected due to a burst defect due to a scratch existing on the optical disk, the width of the window is reduced. A synchronization signal detecting device characterized in that synchronization is hardly lost during forward protection operation by expanding in a stepwise manner, and resynchronization is easily performed when synchronization is lost. 5. A synchronizing signal detecting circuit for reading a signal recorded on an optical disc of an optical disc device, detecting a synchronizing signal through a window control circuit based on the read signal and a window; A frame counter that counts a reference signal reproduced from the optical disk from the optical disk and assumes a predicted position of the next synchronization detection, and is reset by a logical sum of an output from the synchronization detection circuit and a count overflow output of the frame counter. A frame counter, a timing generator that decodes a counter value of the frame counter, and generates a timing of a later-described window signal generation circuit; and a logical product of an output from the synchronization detection circuit and a count overflow output of the frame counter. , Count this AND A rear protection counter that is reset by a front protection counter described later; and a count overflow output of the synchronization detection circuit, which is enabled by a count overflow output of the rear protection counter, and an output from the synchronization detection circuit and a count overflow of the frame counter. An exclusive OR with an output, a forward protection counter that counts the exclusive OR, a decoder that decodes the count value of the forward protection counter, an envelope of the decoded value of the decoder and the read signal The output of the timing generator is controlled by a logical product value of the component and a flaw detection signal,
A window signal generation circuit that generates a window pulse in association with the timing of the predicted position of the synchronization detection, and a logical sum circuit of the window pulse and an overflow output of the forward protection counter to generate the window, A synchronization signal detection circuit for an optical disc device, comprising: 6. The synchronization signal detection circuit according to claim 5, wherein the control of the output of the timing generator expands the width of the window pulse based on the decoded value when the flaw detection signal is present. 7. The decoder according to claim 1, wherein the count value of the forward protection counter is n and the forward protection set number is 4i (i = 1, 2).
2, 3 ...), the value of n is shown in the following table. 7. The synchronization signal detecting circuit according to claim 6, wherein α is a value that is a minimum unit when the width of the window pulse is expanded at the leading edge and the trailing edge, respectively. 8. An optical disk according to claim 5, further comprising a frame clock generation circuit for generating a frame clock based on an output from said synchronization detection circuit and a count overflow output of said frame counter. Synchronous signal detection circuit of the device.