JPH1050002A - Device for detecting synchronizing signal and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the synchronizing signal detecting device capable of high speed recovery of synchronization detecting even when the signal is out of synchronism. SOLUTION: When a synchronous pulse is detected during a detecting period stipulated by a window signal S16 by a decision circuit 15, an output signal FP including this synchronous pulse is outputted. On the other hand, when the synchronous pulse is not detected during this detecting period, the synchronous pulse is interpolated based on an interpolation FP16. Afterward, when the synchronous pulse is detected during a fixed period, then, based on an interpolation FP17 and a window signal 17 from a counter 17 with this detected synchronous pulse as a reference, the synchronous pulse is detected and interpolated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a synchronous signal detecting apparatus and method for detecting a synchronous signal included in a recording signal in an optical disk reproducing apparatus such as a CD.

[0002]

2. Description of the Related Art For example, a signal recorded on a compact disk (CD) has 588 channel bits as one frame, and a synchronization signal is included at the beginning. CD
Has a synchronization signal detection circuit for detecting the synchronization signal. When the synchronization signal detection circuit detects the synchronization signal during the reproduction of the CD, the next synchronization signal should appear after 588 channel bits. Therefore, the synchronization detection is performed by providing a window only for a certain time before and after the timing. . By providing such a window, it is possible to prevent erroneous detection of the synchronization signal due to signal degradation or noise at the timing when the synchronization signal does not appear. In the synchronization signal detection circuit, for example, when the synchronization signal cannot be detected due to the influence of dust or the like attached to the disc,
Even when the timing of generation of the synchronization pulse is shifted due to track jump, disk vibration, etc.
Processing for properly performing reproduction is required.

FIG. 5 is a block diagram of a conventional synchronous signal detecting circuit 1, FIG. 6 is a flowchart of processing in the conventional synchronous signal detecting circuit, and FIG. 7 is a timing chart of the conventional synchronous signal detecting circuit. As shown in FIG. 5, the synchronization signal detection circuit 1 includes an edge detector 2, a shift register 3, a pattern detector 4, a determination circuit 5, and a counter 6.
In the synchronization signal detection circuit 1, the edge of the binarized RF signal S0 is detected by the edge detector 2, and is output to the pattern detector 4 via the shift register 3 having a synchronization pattern length of 23 bits. The pattern detector 4 detects a synchronization pattern included in each frame of the RF signal S0, and outputs a frame pulse signal (detection FP) including a synchronization pulse corresponding to the detection to the determination circuit 5.
At this time, the detection FP always includes a synchronization pulse for each frame, that is, for every 588 channel bits, unless there is a synchronization shift or lack of a synchronization signal.

The counter 6 counts based on the frame pulse signal (FP) from the determination circuit 5 and generates an interpolation frame pulse signal (interpolation FP) including a synchronization pulse 588 channel bits after the generation of the synchronization pulse. I do.
The counter 6 then outputs the frame pulse signal (FP)
Then, a window signal S6 indicating the timing at which the synchronization pulse is generated, that is, the window signal S6 indicating a predetermined interval before and after the position 588 channel bits from the position where the synchronization pulse was previously detected is output to the determination circuit 5. The determination circuit 5 outputs the window signal S6
When a synchronization pulse is detected in the detected FP within the period defined by the above, an FP including the detected synchronization pulse is output, and when the synchronization pulse is not detected within the period, the FP is included in the interpolation FP. An FP including a synchronization pulse corresponding to the synchronization pulse is output.

Next, the operation of the synchronization detecting circuit shown in FIG. 5 will be described with reference to FIGS. 6 and 7. For example,
When a detection FP as shown in FIG. 7B is input from the pattern detector 4 to the determination circuit 5, the window signal S
In the period of the pulse 10a, the determination circuit 5 detects the detection FP.
Since the synchronization pulse 10b included in the synchronization pulse 10b is detected, the F including the synchronization pulse 10c corresponding to the synchronization pulse 10b is detected.
Outputs P. On the other hand, pulse 10 of window signal S6
In the period d, the determination circuit 5 does not detect a synchronization pulse from the detection FP (SP1). At this time, it is determined whether the number of consecutive interpolations of the interpolation FP is equal to or less than “N” (SP2),
If it is determined to be less than or equal to “N”, an FP in which the synchronization pulse 10 e is interpolated based on the interpolated FP is output (SP
3). At this time, for example, “N” is 13. By the way, in the example of the detection FP shown in FIG. 7B, even if the synchronization pulse is missing during the period of the pulse 10d of the window signal S6, the synchronization pulse 10e is inserted into the FP based on the interpolation FP. , A desired frame pulse (FP) can be obtained.

[0006]

However, detection F
If a synchronization error occurs in P, re-synchronization is performed after a synchronization signal is inserted "N" times based on the interpolation FP, so that recovery after the synchronization error occurs can be quickly performed. There is a problem that can not be. For example, the detection FP is shown in FIG.
In the case shown in (1), the synchronization pulse is not detected during the period of the pulse 10d of the window signal S6 even though the synchronization pulse 10h of the detection FP is shifted (SP1). If "N" or less, the synchronization pulse S10i is interpolated, and thereafter, a total of "N" synchronization pulses including the synchronization pulses 10j and 10k are interpolated at 588 channel bit intervals. Then, since the number of interpolations of the synchronization pulse is not less than “N” (S
P2), the window signal S6 always becomes high level,
The window is opened until the synchronization pulse included in the detection FP is detected (SP4). A similar problem occurs not only when reproducing not only CDs but also optical disks such as DVDs (Digital Video Disks).

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned prior art, and is capable of detecting synchronization at high speed when a deviation of an optical pickup from a track due to vibrations or a track jump for forward / reverse fast-forward by trick play occurs. It is an object of the present invention to provide a synchronization detection circuit and a method thereof that can be restored to the original state.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art and to achieve the above-mentioned object, a synchronization signal detecting apparatus according to the present invention comprises a first synchronizing signal detecting apparatus for reproducing a first signal at an interval of one frame of a reproduction signal of an optical disk. First interpolating sync pulse generating means for generating an interpolating sync pulse, and second interpolating sync pulse generating means for generating a second interpolating sync pulse at one frame interval of a reproduction signal of the optical disc; First detection effective period defining means for defining a first synchronization pulse detection effective period having a predetermined time width based on the first interpolation synchronization pulse;
A second detection effective period defining means for defining a second synchronization pulse detection effective period having a predetermined time width based on the interpolation synchronization pulse, and the first synchronization pulse detection effective period and the first When the detection of the synchronization pulse included in the reproduction signal and the interpolation of the synchronization pulse into the output signal are performed based on the insertion synchronization pulse, the detection of the synchronization pulse within a predetermined period after the first synchronization pulse detection valid period has elapsed When a synchronization pulse is detected, the second synchronization pulse is detected with reference to the detected synchronization pulse.
, And based on the second synchronization pulse detection valid period and the second interpolation synchronization pulse, detection of a synchronization pulse included in the reproduction signal and conversion of the synchronization pulse to an output signal. Determining means for performing insertion.

In the synchronization signal detecting device of the present invention, for example,
First, the determination means detects a synchronization pulse included in the reproduction signal and interpolates the synchronization pulse into an output signal based on the first synchronization pulse detection valid period and the first interpolation synchronization pulse. ing. At that time, the determination means:
When a synchronization pulse is detected within a predetermined period after the elapse of the first synchronization pulse detection effective period, the second detection effective period defining means is controlled based on the detected synchronization pulse, and Generate an interpolation synchronization pulse. And
Thereafter, the determination means performs detection of a synchronization pulse included in the reproduction signal and interpolation of the synchronization pulse into an output signal based on the second synchronization pulse detection valid period and the second interpolation synchronization pulse. . That is, according to the synchronization signal detecting device of the present invention, when a synchronization shift occurs, unlike the conventional synchronization signal detecting device, resynchronization is performed immediately after inserting a synchronization pulse 13 times, for example. Is possible.

[0010] In the synchronization signal detecting apparatus according to the present invention, preferably, when the determination unit does not detect a synchronization pulse included in the reproduction signal within the first synchronization pulse detection effective period, One interpolation pulse is interpolated into the output signal.

In the synchronization signal detecting device according to the present invention, preferably, the determination means is included in the reproduction signal based on the first synchronization pulse detection effective period and the first interpolation synchronization pulse. When detecting the synchronization pulse and performing the interpolation of the synchronization pulse to the output signal, the detection of the synchronization pulse within a predetermined period after the elapse of the first synchronization pulse detection valid period is performed twice or more consecutively. Generating the second interpolation synchronization pulse on the basis of the detected synchronization pulse, and includes the second interpolation synchronization pulse in the reproduction signal based on the second synchronization pulse detection effective period and the second interpolation synchronization pulse. The synchronization pulse is detected and the synchronization pulse is interpolated into the output signal.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a synchronization detection circuit and a method thereof according to an embodiment of the present invention will be described. First Embodiment FIG. 1 is a configuration diagram of a synchronization signal detection circuit 11 of this embodiment, FIG. 2 is a flowchart of processing in the synchronization signal detection circuit 11 shown in FIG. 1, and FIG. 3 is a synchronization signal detection circuit 11 shown in FIG.
6 is a timing chart of FIG. As shown in FIG. 1, the synchronization signal detection circuit 11 includes an edge detector 2, a shift register 3, a pattern detector 4, a determination circuit 15, and a counter 1.
6 and 17. In the synchronization signal detection circuit 11, 2
The edge of the digitized RF signal S0 is detected by the edge detector 2, and is output to the pattern detector 4 via the shift register 3 having a synchronous pattern length of 23 bits.
The pattern detector 4 detects a synchronization pattern included in each frame of the RF signal S0, and outputs a frame pulse signal (detection FP) including a synchronization pulse corresponding to the detection to the determination circuit 15. At this time, the detection FP always includes a synchronization pulse for each frame, that is, for every 588 channel bits, unless there is a synchronization shift or lack of a synchronization signal.

The counter 16 counts based on a reset signal rst15a from the determination circuit 15, and outputs an interpolation FP 16 and a window signal S16 according to the count result. The counter 17 counts based on the reset signal rst15b from the determination circuit 15, and outputs an interpolation FP17 and a window signal S17 according to the count result. The determination circuit 15 selectively uses the window signals S16 and S17 and detects a synchronization pulse included in the detection FP within a period defined by the selected window signal, as described later.
And outputs an FP including the detected synchronization pulse.
If no synchronization pulse is detected within the period, interpolation FP16, FP17 corresponding to the selected window signal
Including sync pulse corresponding to sync pulse included in FP
Is output.

Next, the operation of the synchronization detecting circuit 11 shown in FIG. 1 will be described with reference to FIGS. In this example, as an initial state, the determination circuit 15 detects a synchronization signal based on the window signal S16 from the counter 16. For example, when a detection FP as shown in FIG. 3C is input from the pattern detector 4 to the determination circuit 15, the determination circuit 15 outputs the window signal S
Since the synchronization pulse 20b included in the detection FP is detected during the period of the 16 pulses 20a, the synchronization pulse 20b is detected.
An FP including a synchronization pulse 20c corresponding to b is output.
The period of the pulse 20a is, for example, the synchronization pulse 20b
Is a period corresponding to ± 28 bits centered at.

Next, the pulse 20 of the window signal S16
In the period d, since the determination circuit 15 does not detect a synchronization pulse from the detected FP (SP11), an FP in which the synchronization pulse 20e is interpolated based on the interpolation FP 16 is output (S11).
P12). At this time, based on rst15b, the counter 17 outputs the window signal S as shown in FIG.
17 is switched to the high level for a predetermined time, and the determination circuit 15 detects the synchronization pulse using both the window signals S16 and S17 (SP12).

Next, the judgment circuit 15 outputs the window signal S
If the synchronization pulse 20n is detected based on the window signal S17 before the signal 16 becomes high level (SP1
3) It is determined that a synchronization shift has occurred, the synchronization pulse 20f is input to the FP at a position corresponding to the synchronization pulse 20n of the detected FP, and the determination circuit 15 thereafter determines the synchronization pulse 2f.
The synchronization detection process is performed based on the interpolation FP17 including the synchronization pulse at a 588 channel bit interval based on 0n and the window signal S17 based on the synchronization pulse 20f (SP14). That is, the counter 16 is switched to the counter 17.

On the other hand, when the synchronizing pulse 20n is not detected by the judging circuit 15 (SP13), the judging circuit 15 continuously performs the synchronizing detection based on the window signal S16, and the window signal S16 becomes high level. During a certain period, it is detected whether or not the detection FP includes a synchronization pulse (SP15). If it is detected, it is determined that the synchronization pulse is missing, the window signal S17 is closed, and synchronization detection is continuously performed based on the window signal S16 (SP16).

For example, in FIG. 3B, when synchronization detection is being performed based on the window signal S17 from the counter 17, a synchronization pulse is included in the detected FP during the period of the pulse 20f of the window signal S17. If not, the synchronization pulse 20e is set to FP based on the interpolation FP17.
Insert At the same time, the window signal S16 is set to the high level, and then it is determined whether or not the synchronization pulse is detected before the window signal S17 goes to the high level. Then, when the synchronization pulse is detected, it is determined that the synchronization is out of synchronization.
6 to perform synchronization detection. If the synchronization pulse is not detected, the determination circuit 15 continues the window signal S1
7 to perform synchronization detection. The window signal S
16 and the window signal S17, if no synchronization is detected, the interpolation FP is interpolated up to N times, and the resynchronization process is performed when the number of interpolations exceeds N times, as in the conventional case. Do.

In the synchronous signal detecting circuit 11, the interpolation of the synchronous pulse is actually performed by, for example, the shift register 3
Is performed in such a manner that an address for extracting, for example, sub-code data existing at a predetermined bit distance from a synchronization signal included in the reproduction signal is calculated.

As described above, the synchronization signal detecting circuit 11
According to the method, even when a deviation occurs from the track of the optical pickup due to vibration or the like, or a track jump for forward / reverse fast-forward due to trick play occurs, synchronization detection using the synchronization pulse of the detection FP is performed. Can be restored at high speed.

Second Embodiment The synchronization signal detection circuit of this embodiment has the same configuration as the synchronization signal detection circuit 11 shown in FIG. 1 described above, but operates differently. That is, in the above-described synchronization signal detection circuit 11, as shown in FIG. 3, the synchronization pulse of the detection FP is not detected during the period of the pulse 20d of the window signal S16.
When the synchronization pulse of the detection FP was detected during the pulse period of the window signal S17, the counter 16 was immediately switched to the counter 17 as shown in FIG. 2 (SP
13, SP14).

On the other hand, in the synchronous signal detecting circuit of the present embodiment, as shown in FIG. 4, when the synchronous pulse included in the detected FP is not detected during the period of the pulse 30a of the window signal S16, as shown in FIG. The interpolation pulse 30b is interpolated by the interpolation FP16 shown in FIG. 1 and the pulse 30c of the window signal S17 rises. During the period of the pulse 30c, the synchronization pulse 3 included in the detection FP is output.
Even when 0d is detected, the synchronization pulse corresponding to the synchronization pulse 30d is not immediately inserted into the FP. That is, even if the synchronization pulse 30d included in the detection FP is detected in the window signal S17, the switching from the counter 16 to the counter 17 is not immediately performed.

Thereafter, window signals S16 and S1
7, the synchronization pulse included in the detection FP is not detected in the next pulse 30e of the window signal S16, and the synchronization detection is performed during the pulse 30f of the window signal S17 based on the detected synchronization pulse 30d. When the synchronization pulse 30g included in the FP is detected, the synchronization pulse 30h corresponding to the pulse 30e is interpolated, and the synchronization pulse 30i corresponding to the pulse 30g is interpolated. At the same time, from counter 16 to counter 1
7 and the determination circuit 15 performs a synchronization detection process based on the window signal S17 and the interpolation FP17 thereafter. That is, when the synchronization signal included in the detection FP is detected twice consecutively in the window signal S17,
Switch from counter 16 to counter 17.

On the other hand, for example, if the detection of the synchronization pulse 30d is an erroneous detection and the synchronization pulse included in the detection FP is detected during the pulse 30e of the window signal S16, the determination circuit 15 continues Window signal S
16 and a synchronization detection process based on the interpolation FP16.

According to the synchronization signal detection circuit of the present embodiment,
The synchronization pulse of the detection FP is generated only once by the window signal S17.
, The counter is not switched at that time, and then the window signal S17 is detected.
The counter is switched when the synchronization pulse of the detected FP is detected in the pulse 30f of the above. Therefore, even if the first detection of the synchronization pulse is erroneous, if the detection is performed appropriately next time, the erroneous counter is detected. Does not occur.

The present invention is not limited to the above embodiment. For example, in the above-described second embodiment, the counter is switched when the synchronization pulse included in the detection FP is detected twice consecutively in the pulses 30c and 30f of the window signal S17. The above may be used.

[0027]

As described above, according to the synchronization signal detecting apparatus and method of the present invention, the deviation of the optical pickup from the track due to vibration or the like, and the track jump for forward / reverse fast-forward by trick play. Even when a synchronization shift occurs due to occurrence or the like, the synchronization detection processing using the synchronization pulse included in the reproduction signal can be restored at high speed. Further, according to the synchronization signal detection device and method of the present invention, when the synchronization pulse is erroneously detected, the detection valid period is prevented from being switched immediately, and the synchronization detection process using the synchronization pulse is performed with high reliability. It can be restored at high speed.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a synchronization signal detection circuit according to a first embodiment of the present invention.

FIG. 2 is a flowchart of a process in a synchronization signal detection circuit shown in FIG. 1;

FIG. 3 is a timing chart of the synchronization signal detection circuit shown in FIG. 1;

FIG. 4 is a timing chart of a synchronization signal detection circuit according to a second embodiment of the present invention.

FIG. 5 is a configuration diagram of a conventional synchronization signal detection circuit.

FIG. 6 is a flowchart of a process in a conventional synchronization signal detection circuit.

FIG. 7 is a timing chart of a conventional synchronization signal detection circuit.

[Explanation of symbols]

 1, 11: Synchronous signal detection circuit 2: Edge detector 3: Shift register 4: Pattern detector 5, 15: Judgment circuit 6, 16, 17: Counter

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication location H04L 7/08 H04L 7/08 Z (72) Inventor Koji Fukuhara 3-6 Kitaaoyama, Minato-ku, Tokyo No. 12 Fuji Aoyama Building Japan Texas Instruments Co., Ltd.

Claims (4)

[Claims] A first interpolation synchronization pulse generating means for generating a first interpolation synchronization pulse at one frame interval of a reproduction signal of an optical disc; and a second interpolation synchronization pulse generating means at one frame interval of a reproduction signal of the optical disc. Second interpolation synchronization pulse generation means for generating an interpolation synchronization pulse, and first detection validity defining a first synchronization pulse detection validity period having a predetermined time width based on the first interpolation synchronization pulse. Period defining means; second detection effective period defining means for defining a second synchronization pulse detection effective period having a predetermined time width based on the second interpolation synchronization pulse; and the first synchronization pulse detection When the detection of the synchronization pulse included in the reproduction signal and the interpolation of the synchronization pulse to the output signal are performed based on the valid period and the first interpolation synchronization pulse, the first synchronization pulse detection is enabled. After the period has passed When a synchronization pulse is detected within the period, the second interpolation synchronization pulse is generated based on the detected synchronization pulse, and the second synchronization pulse detection valid period and the second interpolation synchronization pulse are generated. A sync pulse detection unit for detecting a sync pulse included in the reproduction signal and interpolating the sync pulse into an output signal based on the sync signal. 2. The method according to claim 1, wherein the determining means includes the step of adding the first interpolation synchronization pulse to the output signal when the synchronization pulse included in the reproduction signal is not detected within the first synchronization pulse detection effective period. The synchronization signal detection device according to claim 1, wherein the synchronization signal is inserted. 3. The method according to claim 1, wherein the determining means detects a synchronization pulse included in the reproduction signal and outputs the synchronization pulse to an output signal based on the first synchronization pulse detection valid period and the first interpolation synchronization pulse. When performing interpolation, the first
If the detection of the synchronization pulse is performed two or more times within a predetermined period after the elapse of the synchronization pulse detection effective period, the second interpolation synchronization pulse is generated based on the detected synchronization pulse, 3. The method according to claim 1, wherein detection of a synchronization pulse included in the reproduction signal and interpolation of the synchronization pulse to an output signal are performed based on a second synchronization pulse detection valid period and the second interpolation synchronization pulse. 4. Synchronization signal detection device. 4. A first interpolation synchronization pulse is generated at one frame interval of a reproduction signal of the optical disk, and a second interpolation synchronization pulse is generated at one frame interval of the reproduction signal of the optical disk; The first synchronization pulse detection valid period of a predetermined time width based on the interpolation pulse synchronization is defined, and the second synchronization pulse detection validity of a predetermined time width based on the second interpolation synchronization pulse is defined. Defining a period, based on the first synchronization pulse detection valid period and the first interpolation synchronization pulse, performing detection of a synchronization pulse included in the reproduction signal and interpolation of the synchronization pulse into an output signal. When detecting a synchronization pulse within a predetermined period after the first synchronization pulse detection valid period has elapsed, the second interpolation synchronization pulse is generated based on the detected synchronization pulse, Second synchronization pal A synchronization signal detection method for detecting a synchronization pulse included in the reproduction signal and interpolating the synchronization pulse into an output signal based on a valid detection period and the second interpolation synchronization pulse.