JP3282289B2 - Digital signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing circuit for recording and reproducing digital data.

[0002]

2. Description of the Related Art r mounted on a cylindrical cylinder
In a digital signal recording / reproducing apparatus for recording / reproducing a digital signal as an oblique track on a tape by means of (r is an integer of 1 or more) heads, the recording signal for one track corresponds to the beginning of the block of digital data. It is formed by connecting a plurality of synchronization blocks each including a synchronization pattern shown, an ID indicating a position of a data as an information signal and indicating a block order, and data including an ID parity for detecting or correcting an error of the ID. And one or more signal regions. As an example of the related art, a case is considered where a recording signal for one track is composed of an audio area for an audio signal and a video area for a video signal. FIG. 7 shows a track pattern. Here, Audi
The o area and the Video area are composed of a synchronization pattern indicating the beginning of the block of digital data, an ID indicating the order of the block, an ID parity for detecting an ID error, and a pattern obtained by modulating video signal data or audio signal data. It is composed of synchronous blocks. A gap is provided between each signal area. FIG. 8 shows the configuration of the synchronization block. FIG. 8A shows the configuration of a synchronous block before modulation, which is composed of an ID indicating a position of a data information signal and indicating the order of the synchronous block, and an ID parity for detecting an ID error. FIG. 8B shows the configuration of a synchronous block obtained by modulating the pattern (a) and adding a synchronous pattern.

[0003] Audio area of recorded tape, Vi
When the reproduction process of the deo area is performed, a synchronous block is detected based on the detected synchronous pattern of the reproduced digital data, the ID value and the ID parity, and it is determined whether or not the synchronous block exists.

Hereinafter, the conventional operation will be described with reference to the drawings. FIG. 9 is a block diagram of a conventional digital signal processing circuit. 131 indicates that the reproduced digital signal 151 is 1
A delay circuit 132 outputs a signal 152 delayed by a synchronous block length, and a delay circuit 132 outputs a signal 153 delayed by one synchronous block length from the delayed signal 152. A synchronization pattern detection circuit 133 detects a synchronization pattern in the reproduced digital signal 151 and outputs a synchronization pattern detection pulse 154. A synchronization pattern 134 detects a synchronization pattern in the delay signal 152 and outputs a synchronization pattern detection pulse 155. A detection circuit 135 detects a synchronization pattern in the delay signal 153 and outputs a synchronization pattern detection pulse 156. A detection circuit 136 detects an ID in the reproduced digital signal 151 and outputs the detected ID 157. An ID detection circuit 137 detects an error based on the detected ID 157 and the ID parity and outputs an ID error flag 158. The ID detection circuit 137 detects an ID in the delay signal 152, outputs a detected ID 159, and outputs the detected ID 159 and ID.
An ID detection circuit 138 that detects an error based on the parity and outputs an ID error flag 160,
This is an ID detection circuit that detects D and outputs the detected ID 161, detects an error based on the detected ID 161 and ID parity, and outputs an ID error flag 162. 13
9, when the window 166 is true, the synchronous pattern detection pulses 154, 155, 156 and the detection IDs 157, 15
9, 161 and ID error flags 158, 160, 162
Thus, the reproduction digital data 151 and the delay circuit 13
1 output data 152 and delay circuit 132 output data 1
A synchronous block detection protection circuit which determines whether or not there are three synchronous blocks in 53, generates a three synchronous block detection pulse 163, and outputs the estimated ID of the synchronous block present in the output data 153 as a modified ID 164 It is. 140 is a 3-sync block detection pulse 163
This is a mask circuit that operates when triggered, and operates as follows.

When the three synchronization block detection pulses 163 are output, a synchronization block detection pulse 165 indicating the timing at which the head of the three synchronization blocks detected is output at the output 153 is output for three synchronization blocks.

When the three synchronous block detection pulse 163 is output, the window 166 is set to false, and thereafter, the synchronous pattern detection pulse 154, 1
55, 156, detection IDs 157, 159, 161 and I
At the timing when the D error flags 158, 160, and 162 will be detected, the window 166 is made true twice with a width of 1 bit at intervals of the synchronization block length, and thereafter the window 166 is always made true after one synchronization block. The demodulator 141 demodulates a synchronous block in the data 153 by using the synchronous block detection pulse 165 and the correction ID 164, corrects an erroneous ID, and outputs demodulated data 168 and a synchronous block head pulse 169 indicating the head of the synchronous block. Is output.

The synchronous block detection circuit 139 detects when two or more synchronous pattern detection pulses are detected, and when two or more IDs with no ID error flag are present and the continuity of the IDs is satisfied. It is determined that three synchronous blocks exist, and three synchronous block detection pulses 1
63 is generated. The correction ID 139 is created from an ID with no ID error flag.

FIGS. 10 and 11 show an operation example of a conventional digital signal processing circuit. With the above-described circuit configuration, three consecutive digital signals are output from the reproduced digital data at a synchronous block length interval.
The synchronization pattern, the ID and the ID parity are detected from the locations, and it is determined whether or not a synchronization block exists in data extracted from three locations in the reproduced digital data.

First, the operation of detecting a synchronous block will be described with reference to FIG. By the operation of the synchronous block detection circuit 139 alone, the missing synchronous block is corrected as shown in FIG. 10A, and the false synchronous block whose periodicity is not satisfied as shown in FIG. 10B. To eliminate.

[0010] Further, the synchronous block detecting circuit 139 and the counter 140 eliminate a false synchronous block generated in the synchronous block period as shown in c of FIG.

Next, FIG. 11 shows a case where a malfunction occurs. As shown by d and f in FIG. 11, the case where the period of the synchronization pattern in the reproduced digital data changes due to a malfunction of the reproduction clock or the like will be described.

When the synchronization block period is shortened as shown in d, since the synchronization pattern and ID of the synchronization block after the synchronization block period is shortened cannot be normally detected, an error occurs in the synchronization pattern and the detection ID. It is determined that there is, and the missing of the synchronous block is corrected. Therefore, the synchronous block data (ID = 6) shown in e is erroneous.
Further, the next synchronization block cannot be detected due to the window 167.

If the synchronization block period becomes longer as shown in f, the synchronization pattern and the ID of the synchronization block after the synchronization block period becomes longer cannot be detected normally. It is determined that there is, and the missing of the synchronous block is corrected. Therefore, the synchronous block data (ID = 10) shown in h is erroneous.

[0014]

However, in the conventional digital signal processing circuit, when the period of the synchronization pattern in the reproduced digital data changes due to a malfunction of the reproduction clock or the like, the synchronization cannot be detected normally and an erroneous detection is performed. Sync block is detected. If you make a mistake in the sync block,
All the data in the synchronous block will be erroneous, which will have a very bad effect on the reproduced data.

An object of the present invention is to solve the above-mentioned problems and to provide a digital signal processing circuit which does not adversely affect reproduced data.

[0016]

In order to solve the above-mentioned problems, a digital signal processing circuit according to the present invention is recorded as an oblique track on a tape by r heads mounted on a cylindrical cylinder. A synchronization pattern indicating the beginning of the block of digital data, synchronization indicating the position of the data as an information signal and ID indicating the order of the block, and data including an ID parity for detecting or correcting an error in the ID. A digital signal processing circuit of a digital signal reproducing apparatus for reproducing data of one or more signal areas formed by connecting a plurality of blocks, wherein the digital signal processing circuit is separated from a synchronous block length interval indicated by a first mask means in reproduced digital data. The synchronization pattern is detected from the width of the preceding m bits and the succeeding n bits centering on two or more x positions, and the synchronization block is detected. The width of the preceding m bits n bits behind the x positions centered on the x positions separated by the synchronous block length interval corresponding to the position of the synchronization pattern existing at the width of the preceding m bits n bits after the x positions separated by the center , An ID and an ID parity are detected, x synchronization patterns are detected, and (m +
x synchronization pattern detection positions indicating where the synchronization pattern exists in the (n + 1) -bit width, x detection IDs, and the detection ID in any of the (m + n + 1) -bit widths When the x number of ID detection positions and the x number of ID parities indicate the y number of synchronous blocks, the synchronous block detecting means for detecting y or less y synchronous blocks, and the synchronous block detecting means for detecting y synchronous blocks, The synchronous block detecting means detects whether there is an error in the synchronous pattern among the y synchronous blocks detected previously or the ID detected.
While operating within the range in which a synchronous block determined to be error-free can be detected, a synchronous block is detected only with a width of m bits before and n bits behind the synchronous block position expected from the previously detected synchronous block position. The operation is performed, and the synchronous block detecting means detects whether there is no error in the synchronous pattern among the previously detected
While operating within a range in which only a synchronous block that does not include a synchronous block determined to have no error in D can be detected, i bits before and j bits after the synchronous block position expected from the previously detected synchronous block position Width (i> m,
j> n), the synchronous block detecting operation is performed, and when the synchronous block detecting means operates outside the range in which the previously detected y synchronous blocks can be detected, it is predicted from the previously detected y synchronous block positions. The first mask means capable of always performing the synchronous block detection operation from k bits before the next synchronous block position and the synchronous block detection means simultaneously synchronize two or more signals within a j-bit period shorter than the synchronous block length. When a block is detected, the second mask means adopts only a synchronous block detected later.

[0017]

According to the present invention, the information of the synchronous block is detected from the width of the preceding m bits and the subsequent n bits centering on the positions of two or more x places separated by the synchronous block length interval in the reproduced digital data. The position where the same synchronous block exists is detected at least x times, and there is an opportunity to determine the position as the synchronous block x times. This eliminates a false synchronous block and increases the accuracy of correction of missing synchronous block detection. Can be. In addition, since it has a width of (m + n + 1) bits, it is possible to detect a synchronization block including a period shift from + n bits to -m bits.

Furthermore, the first mask operation eliminates a false synchronous block having periodicity, and changes the window width depending on the state of the synchronous block detected in the first mask operation. When two or more synchronous blocks are detected at the same time within a period shorter than the synchronous block length by the mask operation of (1), only the synchronous block detected later is adopted, thereby increasing the larger + j bit to -i.
It is possible to cope with a period shift of the synchronous block up to the bit.

In the synchronous block detection circuit, (m + n +
1) Detecting with a bit width is effective for a period shift of a synchronous block, but the wider the width, the more complicated and the larger the circuit. Therefore, the first
By the mask operation and the second mask operation, it is possible to cope with the cycle shift of the synchronous block without complicating the circuit.

[0020]

An embodiment of the present invention will be described below with reference to the drawings.

K mounted on a cylindrical cylinder
In a digital signal recording / reproducing apparatus for recording / reproducing a digital signal as an oblique track on a tape by means of (k is an integer of 1 or more) heads, a recording signal for one track corresponds to the beginning of the block of digital data. It is formed by connecting a plurality of synchronization blocks each including a synchronization pattern shown, an ID indicating a position of a data as an information signal and indicating a block order, and data including an ID parity for detecting or correcting an error of the ID. And one or more signal regions. As an example of the related art, a case is considered where a recording signal for one track is composed of an audio area for an audio signal and a video area for a video signal. FIG. 7 shows a track pattern. The track pattern has the same configuration as the conventional example. Here, the audio area and the video area include a synchronization pattern indicating the start of the block of digital data, and an I / O indicating the block order.
It is composed of a synchronization block unit consisting of a D and an ID parity for detecting an ID error and a pattern obtained by modulating video signal data or audio signal data. A gap is provided between each signal area. FIG. 8 shows the configuration of the synchronization block. The configuration of the synchronization block is the same as that of the conventional example.
FIG. 8A shows the configuration of a synchronous block before modulation, which is composed of an ID indicating a position of a data information signal and indicating the order of the synchronous block, and an ID parity for detecting an ID error. FIG. 8B shows the configuration of a synchronous block obtained by modulating the pattern (a) and adding a synchronous pattern.

Audio area of recorded tape, Vi
When the reproduction process of the deo area is performed, a synchronous block is detected based on the detected synchronous pattern of the reproduced digital data, the ID value and the ID parity, and it is determined whether or not the synchronous block exists.

FIG. 1 is a block diagram of a digital signal processing circuit according to one embodiment of the present invention. Reference numeral 1 denotes a delay circuit that outputs a signal 15 obtained by delaying the reproduced digital signal 14 by one synchronous block, and reference numeral 2 denotes a delay circuit that outputs a signal 16 obtained by delaying the delayed signal 15 by one synchronous block. A synchronous pattern detection circuit 3 detects a synchronous pattern in the reproduced digital signal 14 and outputs a synchronous pattern detection pulse 17.
A synchronous pattern detection circuit for detecting a synchronous pattern in the delay signal 15 and outputting a synchronous pattern detection pulse 18;
A synchronous pattern detecting circuit for detecting a synchronous pattern in the delay signal 16 and outputting a synchronous pattern detection pulse 19;
Is an ID detection circuit for detecting an ID in the reproduced digital signal 14 and outputting the detected ID 20, detecting an error based on the detected ID 20 and ID parity, and outputting an ID error flag 21; The ID 22 is detected and the detected ID 22 is output, and the detected ID 22 and the ID 22 are output.
An ID detection circuit 8 detects an error based on parity and outputs an ID error flag 23. An ID detection circuit 8 detects an ID in the delay signal 16 and outputs an ID 24 detected.
Error by ID and ID parity and ID error flag 2
5 is an ID detection circuit that outputs 5.

9 indicates that when the window 29 is true, the synchronous pattern detection pulses 17, 18, 19 and the detection IDs 20, 20,
2, 24 and the ID error flags 21, 23, 25, it is determined whether or not three synchronized blocks exist in the reproduced digital data 14, the output data 15 of the delay circuit 1, and the output data 16 of the delay circuit 2. This is a synchronous block detection protection circuit that generates a 3 synchronous block detection pulse 26 and a bit slip countermeasure pulse 27, and outputs the estimated ID of the synchronous block present in the output data 16 as a modified ID 28. The synchronous block detection protection circuit is true of two or more of the three synchronous pattern detection pulses 17, 18, and 19, and has no continuity due to the detection IDs 20, 22, and 24 and the ID error flags 21, 23, and 25. If there are two or more IDs satisfying the condition (3), it is determined that three synchronous blocks exist, and the three synchronous block detection pulse 26 is set to true. In addition, three synchronous block detection pulses 26
Is true, the synchronous pattern detection pulse 17 is false, the ID error flag 21 is true, and the detection ID 20 is erroneous. The bit slip countermeasure pulse 27 indicating that there is a possibility of being present at the shifted position due to the shift is set to true.

Reference numeral 10 denotes a first mask circuit which is constituted by a counter which is activated by a tri-sync block detection pulse 26 and operates as shown in FIG.

When the three synchronous block detection pulses 26 are true, a synchronous block detection pulse 30 indicating the timing at which the heads of the three detected synchronous blocks are output to the output 16 is output for three synchronous blocks.

When the three-synchronous block detection pulse 26 is true and the bit slip countermeasure pulse 27 is false,
The window 29 is made false, and the synchronous pattern detection pulses 17, 18, 19 and the detection I
D20, 22, 24 and ID error flags 21, 23, 2
5 at the timing expected to detect 5
Is performed twice, and then the synchronous pattern detection pulses 17, 18, and 19, the detection IDs 20, 22, and 24, and the ID error flags 21 and 2 are output from the synchronous block detection and protection circuit.
The window 29 is always true from k bits before the timing when it is expected to detect 3, 25. When the 3 synchronous block detection pulse 26 is true and the bit slip countermeasure pulse 27 is true, the window 29 is set to false, and the synchronous pattern detection pulse 17,
18, 19, the detection IDs 20, 22, 24, and the ID error flags 21, 23, 25 are set to true at the timing expected to detect them. Then, the synchronization pattern detection pulse 17, 18, 19
, Detection IDs 20, 22, 24 and ID error flag 2
The window 29 is made true with a width of i bits before and j bits after the timing expected to detect 1, 23 and 25, and then the synchronous pattern detection pulses 17, 18 and 19 are generated by the synchronous block detection and protection circuit. , Detection IDs 20, 22,
24 and the ID error flags 21, 23, 25 are detected in window 2 k bits before the timing expected to be detected.
9 is always true.

Numeral 11 denotes two or more synchronous block detection pulses 3 simultaneously during a period of j bits shorter than the synchronous block length.
This is a second mask circuit that outputs a masked synchronous block detection pulse 31 by adopting only a synchronous block detection pulse detected later when true exists in 0. FIG.
The following shows a circuit example. Here, j = 6. 36,
37, 38, 39, and 40 are D flip-flops, 41,
Reference numerals 42, 43, 44 and 45 are AND gates, and reference numeral 46 is an inversion gate. 47 is an operation clock.

FIG. 4 shows an operation example. 12 is the data 1 based on the synchronous block detection pulse 31 and the correction ID 28.
6 is a demodulation circuit that demodulates the synchronous block in No. 6 and corrects an erroneous ID, and outputs demodulated data 32 and a synchronous block head pulse 33 indicating the head of the synchronous block.

FIGS. 5 and 6 show an operation example of the digital signal processing circuit according to one embodiment of the present invention. With the above circuit configuration,
From the reproduced digital data, a synchronization pattern, ID and ID parity are detected from three places continuously at a synchronization block length interval, and it is determined whether or not a synchronization block exists in data extracted from three places in the reproduction digital data. judge.

First, the operation of detecting a synchronous block will be described with reference to FIG. By the operation of the synchronous block detection and protection circuit 9 alone, the missing synchronous block is corrected as shown in FIG. 5A, and the false synchronization whose periodicity is not satisfied is shown in FIG. 5B. Eliminate blocks.

The synchronous block detecting circuit 9 and the first mask circuit 10 eliminate a false synchronous block generated in a synchronous block cycle as shown in FIG.

Next, FIG. 6 shows the operation when the period of the synchronous block is shifted. As shown by d and f in FIG. 6, a case where the period of the synchronization pattern in the reproduced digital data changes due to a malfunction of the reproduction clock or the like will be described.

When the synchronization block period is shortened (within i bits) as shown in d, the synchronization block with ID = 6 appears earlier, but FIG. 2B in the first mask circuit. Since the window becomes true earlier as a result of the above operation, it can be detected without error after the synchronous block with ID = 6.

When the synchronization block period becomes long (within j bits) as shown in f, the synchronization pattern and ID of the synchronization block after the synchronization block period becomes long before the synchronization block is normally detected. It is determined that there is a loss, the synchronization block detection pulse 30 is set to true at h, and an erroneous synchronization block is output. The operation of the first mask circuit shown in FIG. 2B can also detect a synchronous block after the synchronous block period has been lengthened, and sets the synchronous block detection pulse 30 to true at g. Therefore, the same ID =
Two synchronous blocks recognized as 10 exist in j bits. However, by masking the synchronous block detection pulse of g by the second mask circuit, normal operation can be performed even when the synchronous block period becomes long.

In this embodiment, the synchronous block detection and protection circuit 9 is used.
Operates assuming that synchronous blocks exist at three positions separated by a synchronous block length interval. However, the present invention is not limited to the detection of three synchronous blocks, and generally, two synchronous blocks are separated by a synchronous block length interval.
Assuming that a synchronous block exists at the above x positions, a similar effect can be obtained by an operation employing y (y <x) synchronous blocks among them.

In the above case, the first masking circuit 10
While outputting the synchronous block data of all the synchronous blocks in which it is determined that there is no error in the synchronous pattern or the detected ID has no error in the synchronous block, the synchronous block is detected only at the detected synchronous block position. While performing the operation and outputting the synchronous block data of the synchronous block which is determined to have an error in the last consecutive synchronous pattern among the y synchronous blocks and to determine that the detected ID is incorrect, The synchronous block detection operation is performed with the width of the preceding i bits and the subsequent j bits centering on the detected synchronous block position, and the data of k bits before the last bit of the detected y synchronous block data is output. Is performed such that the mask operation is performed.

Further, the synchronous block detection / protection circuit 9 is assumed to have a synchronous block having a width of m bits before and n bits after the center of two or more x positions separated by the synchronous block length interval, and y within that, The same effect can be obtained by an operation employing a number of (y <x) synchronous blocks. In the above case, i, j, k of the first mask circuit and the second mask circuit
Is a relation of i> m, j> n, k> m.

Detecting a synchronous block within a range of (m + n + 1) bits centering on x positions separated by the synchronous block length interval requires data from x synchronous block detection positions in consideration of the synchronous block cycle shift. To use
This is an effective detection method for the synchronous block cycle deviation. In particular, it is effective at the time of synchronization block detection pull-in, that is, at the start of a mask operation for eliminating a fake synchronous block having periodicity. However, there is a disadvantage that the wider the width, the more complicated and the larger the circuit.

Therefore, the first mask operation and the second mask operation can cope with a larger period shift of the synchronous block without complicating the circuit.

(M + n +
An example of detection with the width of 1) will be described below.

As a method of reducing the reproduction processing speed, there is a method of converting reproduction data from serial data to q-bit parallel data to reduce the frequency of the operation clock to 1 / q. In this case, in the synchronous block detection protection circuit 9,
The synchronization pattern and the ID are detected with a width of q bits within one clock from two or more x positions separated by the synchronization block length interval. That is, x separated by the synchronization block length interval
A synchronous block is detected with a width of (m + n + 1) = q bits around the position of the point.

In the ID detection circuits 6, 7, and 8,
Although an error is detected by the ID parity, an error correction function may be added to the ID detection circuits 6, 7, and 8 by the ID parity, and an ID error flag may be generated for an ID that cannot be corrected.

Although the above operation is realized by the above configuration using the delay circuits 1 and 2, even if the above configuration is not used, the synchronization block is started from two or more x places separated by the synchronization block length interval in the reproduced digital data. The same effect can be obtained by extracting the information of

[0045]

According to the present invention, two or more x's separated from each other by a synchronous block length interval in the reproduced digital data have the above-mentioned structure.
Since the information of the synchronization block is detected from the width of the preceding m bits and the subsequent n bits centering on the position of the location, the position where the same synchronization block exists is detected at least x times, and there is an opportunity to be determined as the synchronization block x times. As a result, it is possible to eliminate false synchronous blocks and improve the accuracy of correcting missing synchronous block detection. In addition, since it has a width of (m + n + 1) bits, it is possible to detect a synchronization block including a period shift from + n bits to -m bits.

Further, the first mask operation eliminates a false synchronous block having a periodicity, and changes the window width depending on the state of the synchronous block detected in the first mask operation. When two or more synchronous blocks are detected at the same time within a period shorter than the synchronous block length by the mask operation of (1), only the synchronous block detected later is adopted, thereby increasing the larger + j bit to -i.
It is possible to cope with a period shift of the synchronous block up to the bit.

In the synchronous block detection circuit, (m + n +
1) Detecting with a bit width is effective for a period shift of a synchronous block, but the wider the width, the more complicated and the larger the circuit. Therefore, the first
By the mask operation and the second mask operation, it is possible to cope with the cycle shift of the synchronous block without complicating the circuit.

[Brief description of the drawings]

FIG. 1 is a digital signal processing circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first mask circuit;

FIG. 3 is a second mask circuit diagram;

FIG. 4 is a timing chart for explaining the operation of the second mask circuit;

FIG. 5 is a timing chart for explaining the operation of the embodiment of the present invention;

FIG. 6 is a timing chart for explaining the operation of the embodiment of the present invention;

FIG. 7 is a schematic diagram showing an example of a track pattern.

FIG. 8 is a schematic diagram showing an example of a synchronization block.

FIG. 9 is a block diagram of a conventional digital signal processing circuit.

FIG. 10 is a timing chart for explaining the operation of a conventional digital signal processing circuit.

FIG. 11 is a timing chart for explaining the operation of a conventional digital signal processing circuit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 delay circuit 2 delay circuit 3 synchronization pattern detection circuit 4 synchronization pattern detection circuit 5 synchronization pattern detection circuit 6 ID detection circuit 7 ID detection circuit 8 ID detection circuit 9 synchronization block detection protection circuit 10 first mask circuit 11 second mask Circuit 12 Demodulation circuit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-36209 (JP, A) JP-A-3-23731 (JP, A) JP-A-3-112230 (JP, A) JP-A-3-112230 244235 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G11B 20/10 G11B 20/14 G11B 20/18 H04L ^7/ 00-7/10

Claims (2)

(57) [Claims] 1. A synchronization pattern indicating the beginning of a block of digital data recorded on a medium, an ID indicating a position of the data as an information signal and indicating a block order, and detecting or correcting an error in the ID. A digital signal processing circuit of a digital signal reproducing apparatus for reproducing data in a signal area formed by connecting a plurality of synchronous blocks each composed of ID parity and data, wherein a synchronous signal indicated by a first mask means in reproduced digital data is provided. A synchronization pattern is detected from the width of the preceding m bits and the subsequent n bits centering on two or more x positions separated by a block length interval,
The position of the synchronization pattern existing in the width of n bits after the preceding m bits centered on the position of x places separated by the synchronization block length interval, and the front of the m positions by x positions separated by the synchronization block length interval ID and ID parity are detected from the n-bit width, and x synchronization pattern detections and x synchronization pattern detection positions indicating where the synchronization pattern exists in the (m + n + 1) -bit width;
The x number the detection ID of the and (m + n + 1) which position the detection ID of x number of ID detection position and x number indicating whether a exists the ID of the width of the bit parity, the same
The number of synchronization patterns existing at the synchronization pattern detection position is
Paris that is equal to or greater than a fixed value and exists at the same ID detection position
If the number of IDs with no
Synchronous block detecting means for determining that there are y or less y synchronous blocks, and the synchronous block detecting means detecting y synchronous blocks.
The synchronous block detection means detects the
Error in the synchronization pattern among the y synchronization blocks
Is determined to be correct or the detected ID is correct.
As long as the operation is within the range in which the
The synchronization block expected from the synchronization block position
Synchronization with only the width of m bits before and n bits after the clock position
Performing a block detection operation, wherein the synchronous block detection means
Is the synchronization among the previously detected y synchronization blocks.
There is no error in the pattern or no error in the detected ID.
Of the synchronous block that does not include the synchronous block determined to be
As long as it operates within the range where only
The expected synchronous block position from the synchronous block position
The width of the previous i bits and the last j bits at the center (i> m, j> n)
In performs synchronous block detection operation, synchronization block detection means
Can detect the previously detected y synchronization blocks.
If it operates out of the range, the previously detected y
From the next synchronous block position expected from the initial block position
The synchronous block detection operation can always be performed k bits before
And a first mask means . 2. A synchronous block detecting means, comprising:
At the same time, two or more synchronous
If a lock is detected, the synchronization block
Having a second mask means employing only
The digital signal processing circuit according to claim 1.