JPH10199162A - Signal reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a signal reproducing device which can detect and protect synchronizing signal at high speed, surely, and stably even if out-of-synchronism is caused by external disturbance and the like in a synchronizing signal. SOLUTION: Comparison between a reference synchronizing pattern and an input signal is performed by a pattern comparison circuit 10. When the input signal coincides with a reference synchronizing pattern, a coincidence pulse occurs, and inputted to a first detecting window making circuit 11, a second detecting window making circuit 12, and a synchronism detecting and protecting circuit 13. The first detecting window making circuit 11 and the second detecting window making circuit 12 make a first detecting window and a second detecting window of N clocks before and after the counted synchronized period in accordance with a first lock signal and a second lock signal from the synchronism detecting and protecting circuit 13, and inputs it to the synchronism detecting and protecting circuit 13. Further, they generate an output synchronizing signal based on a lock state in a coincidence pulse, the first detecting window, and the second detecting window.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal reproducing apparatus which is used for a digital information storage medium, for example, a compact disk (CD), a digital video disk (DVD), and detects and reproduces a discrete signal. More specifically, the present invention relates to a signal reproducing apparatus having a function of detecting a synchronization signal and protecting the interpolation.

[0002]

2. Description of the Related Art In a digital information storage medium, for example, a compact disk (CD), a digital video disk (DVD), or the like, data cannot be accurately reproduced unless a synchronization signal can be accurately detected. Therefore, measures have been taken to accurately detect the synchronization signal.

FIG. 6 is a block diagram of a conventional signal reproducing apparatus for performing a synchronization detecting process, and FIG. 7 is a timing chart of each circuit. Hereinafter, a synchronization detection process using the signal reproducing device will be described. In FIG. 6, an input signal is input to a pattern comparison circuit 101 and compared with a reference synchronization pattern which is a synchronization pattern. When the input signal matches the reference synchronization pattern, a matching pulse is generated and input to the detection window creation circuit 102 and the synchronization detection protection circuit 104. The detection window creation circuit 102 operates the synchronization period counter based only on the coincidence pulse in the detection window,
The synchronization period is counted, and a detection window for N clocks is created before and after the counted synchronization period. The synchronization detection and protection circuit 104 generates an output synchronization signal based on the coincidence pulse when the coincidence pulse from the pattern comparison circuit 101 and the detection window from the detection window generation circuit 102 include a coincidence pulse in the detection window ( FIG. 7A). If there is no coincidence pulse in the detection window due to disturbance of the synchronization period due to disturbance or the like, the output synchronization signal is interpolated and protected at every prescribed synchronization period using the synchronization period counter of the detection window creation circuit 102 (FIG. 7). (B)).

At the initial stage of operation or when the number of times the interpolation protection of the output synchronization signal continuously exceeds the set number of times, the detection window is opened and kept open until a coincidence pulse is input.
When a coincidence pulse is input, the synchronization cycle counter operates, and creates a detection window for N clocks before and after the synchronization cycle,
Perform a synchronous lock. Further, when a disturbance signal indicating the occurrence of disturbance is input, the detection window is widened from ± N clocks in the narrow window mode to ± M clocks in the wide window mode (M> N) to try to lock synchronously.

[0005]

The purpose of the synchronization detection protection is to reliably detect the synchronization signal, to interpolate and protect the synchronization signal when an error occurs in the input signal, and to reduce the synchronization period when disturbance occurs. In the case where the synchronization signal is disturbed, it is an object of the present invention to reliably detect the synchronization signal while interpolating and protecting the synchronization signal. However, in the conventional synchronization detection protection processing method,
If a disturbance occurs and the synchronization cycle is disturbed, the interpolation signal can be protected but the synchronization signal cannot be reliably detected until the interpolation protection continuously exceeds the set number of times. Therefore,
There was a time constraint from interpolation protection to reliable detection.

In addition, the detection window width is widened from a narrow window mode, which is a steady state, to a wide window mode in response to a disturbance signal. However, when transitioning from the wide window mode to the narrow window mode, which is the steady state, there is a time constraint that it is not possible to transition to the steady state until it is determined that there is no disturbance. There was a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a signal reproducing apparatus capable of detecting and synchronizing a synchronization signal at high speed, reliably and stably, even if the synchronization signal has a cycle shift due to disturbance or the like.

[0008]

According to a first aspect of the present invention, in a signal reproducing apparatus for reproducing a discrete signal recorded on a predetermined medium, an input signal is compared with a reference synchronizing pattern having a constant period to generate a coincidence pulse. A comparison circuit that counts the synchronization period of the coincidence pulse, and creates a first detection window having a predetermined width before and after the synchronization period; and a predetermined detection window before and after another synchronization period of the coincidence pulse. A second detection window creating circuit for creating a second detection window having a width of, and based on the coincidence pulse when the coincidence pulse exists in the detection window, and based on the coincidence pulse when the coincidence pulse no longer exists in the detection window, A synchronization detection protection circuit that performs interpolation protection for each synchronization cycle of the detected coincidence pulse and outputs a synchronization signal. The first
When one of the detection window creation circuits and the second detection window creation circuit creates a detection window at a synchronization cycle of a coincidence pulse,
If the other does not create a detection window and one no longer has a coincidence pulse in the detection window, it creates a detection window only a certain number of times in the previous synchronization cycle and the other detects the coincidence pulse in the synchronization cycle Create a window. The synchronization detection protection circuit performs interpolation protection only when the detection window is created a certain number of times.

According to a second aspect of the present invention, the detection window creation circuit widens the window width of the detection window in response to a disturbance, and reduces the window width when the coincidence pulse is detected in the detection window. 2. The signal reproducing device according to claim 1, wherein

The invention of claim 3 is characterized in that the detection window creation circuit measures the position of the coincidence pulse detected in the detection window, and reduces the window width according to the measured value. A signal reproducing apparatus according to claim 2.

According to a fourth aspect of the present invention, in the signal reproducing apparatus according to the second aspect, the detection window creation circuit widens the width of the detection window in accordance with the number of times of interpolation protection.

[0012] In the first aspect of the present invention, the first detection window,
Using the second detection window, each time the period of the coincidence pulse changes, a detection window is created alternately in synchronization with the synchronization period of the coincidence pulse. For a large period shift of the synchronization signal due to disturbance, etc.,
Synchronous signals can be detected quickly and reliably, and accurate detection can be performed even if the number of times the synchronous signals are protected is reduced.

According to the second aspect of the present invention, the width of the detection window is increased in accordance with a disturbance signal indicating occurrence of disturbance, and the width of the window is reduced when a synchronization signal is detected in the window. The synchronization signal is reliably and stably detected in response to a large period shift of the synchronization signal due to disturbance or the like, and if there is no disturbance, the state can be shifted to a steady detection state (window width).

According to the third aspect of the present invention, the position of the coincidence pulse detected in the detection window is measured, and the window width is reduced according to the measured value. Therefore, the detection window width can be more appropriately brought close to the steady state.

According to the fourth aspect of the present invention, since the width of the detection window is increased according to the number of times of interpolation protection, the synchronization signal can be detected more appropriately and stably.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a signal reproducing apparatus according to the present invention,
FIG. 2 is a timing chart of each circuit. This signal reproducing apparatus has a function of reproducing a synchronous signal which is a discrete signal recorded on a predetermined medium, and includes a pattern comparing circuit 1, a first detection window forming circuit 2, a second detection window forming circuit 3, This is a configuration including the detection protection circuit 4.

A reproduction signal reproduced from a recording medium such as a CD is input to the pattern comparison circuit 10 as an input signal.
A comparison with a reference synchronization pattern, which is a synchronization pattern, is performed. When the input signal matches the reference synchronization pattern, a match pulse is generated and input to the first detection window creation circuit 11, the second detection window creation circuit 12, and the synchronization detection protection circuit 13. The first detection window creation circuit 11 and the second detection window creation circuit 12 create a detection window in accordance with the period of the coincidence pulse, operate the synchronization period counter based only on the coincidence pulse within the detection window, and Count the cycle. Before and after the counted synchronization cycle, a first detection window and a second detection window for N clocks are created according to a first lock signal and a second lock signal from a synchronization detection and protection circuit 13 described later in detail, and the synchronization is performed. Input to the detection protection circuit 13.

When a coincidence pulse exists in the first detection window, the synchronization detection protection circuit 13 inputs a first lock signal indicating that the synchronization is locked to the second detection window creation circuit 12. If a coincidence pulse exists in the second detection window, a second lock signal indicating that the synchronization is locked is input to the first detection window creation circuit 11. 1st or 2nd
The absence of a coincidence pulse within the detection window indicates that the first or second lock signal is in an unlocked state. Further, an output synchronization signal is created based on the coincidence pulse, the first detection window, and the second detection window.

The operation of the synchronization detection protection processing of the signal reproducing apparatus having the above configuration will be described below. The coincidence pulse created by the pattern comparison circuit 10 is input to a first detection window creation circuit 11 and a second detection window creation circuit 12, and serves as a reference for detection window creation. First, the first detection window creation circuit 11
A detection window is created in accordance with the period of the coincidence pulse, and the synchronization period counter is operated based on only the coincidence pulse within the detection window to count the synchronization period. Create a first detection window for N clocks before and after the counted synchronization cycle,
Output to the synchronization detection protection circuit 13. On the other hand, the second detection window creation device keeps the detection window open.

When a coincidence pulse exists in the detection window, the synchronization detection protection circuit 13 counts the number of consecutive occurrences of the coincidence pulse, and outputs a locked Hi signal when the count value becomes equal to or greater than the set number of locks (FIG. In 2, the number of times of lock setting is 2.) However, when the detection window is in the open state, the count value becomes 1, and in FIG. 2, the lock signal outputs a Low signal indicating the unlock state.

Accordingly, the synchronization detection and protection circuit 13 confirms that a coincidence pulse exists in the first detection window, and outputs the first lock signal (H) indicating the locked state to the second detection window creation device 12.
i level). Further, since the second detection window is in the open state, a second lock signal (Low level) indicating an unlocked state is output to the first detection window creation device 11.

Since the second lock signal is not in a locked state, the first detection window creation circuit 11 keeps creating detection windows for N clocks before and after the synchronization cycle. Then, the first detection window is created on the basis of the coincidence pulse until the coincidence pulse exists in the first detection window. If there is no coincidence pulse in the first detection window, first, a first detection window for N clocks is created before and after the next synchronization cycle with reference to a synchronization cycle counter that counts the synchronization cycle. At the same time, the synchronization detection protection circuit 13
The lock signal is unlocked (Low level) and output to the second detection window creation circuit 12.

The second detection window creation circuit 12 creates a detection window in accordance with the period of the coincidence pulse, and operates the synchronization period counter based only on the coincidence pulse within the detection window,
Count the synchronization period. A second detection window for N clocks is created before and after the counted synchronization period, and is output to the synchronization detection protection circuit 13.

The synchronization detection protection circuit 13 confirms that a coincidence pulse exists in the second detection window, and outputs a second lock signal (Hi level) indicating a locked state to the first detection window creation device 11. . Further, since no coincidence pulse exists in the first detection window, a first lock signal (Low level) indicating an unlocked state is output to the second detection window creation device 12.

Here, while the coincidence pulse exists in the first detection window, the synchronization detection and protection circuit 13 creates an output synchronization signal based on the coincidence pulse. For the next synchronization period in which no coincidence pulse exists in the first detection window, the first detection window is created and the second detection window is created at the same time. At this point, the first lock signal changes from Hi to Low,
The lock is also low, and the output synchronization signal is interpolated and protected according to the set number of interpolation protections for each synchronization cycle based on the synchronization cycle counter of the first detection window creation circuit 11 (see FIG. 2).

Since the first lock signal is not in the locked state, the second detection window creation circuit 12 keeps creating N clock detection windows before and after the synchronization cycle. Then, a second detection window is created based on the coincidence pulse until a coincidence pulse exists in the second detection window. On the other hand, the first detection window creation circuit 11
Since the lock signal is in the locked state, the detection window is opened. Therefore, the synchronization detection protection circuit 13 holds the first lock signal in the unlocked state.

If there is no coincidence pulse in the second detection window, first, a second detection window for N clocks is created before and after the next synchronization cycle with reference to a synchronization cycle counter that counts the synchronization cycle. At the same time, the synchronization detection protection circuit 13 sets the second lock signal to the unlocked state (Low level),
Output to the detection window creation circuit 11.

The synchronization detection protection circuit 13 confirms that a coincidence pulse exists in the first detection window, and outputs a second lock signal (Hi level) indicating a locked state to the second detection window creation device 11. . Further, since no coincidence pulse exists in the second detection window, a first lock signal (Low level) indicating an unlocked state is output to the first detection window creation device 12.

Here, while the coincidence pulse exists in the second detection window, the synchronization detection and protection circuit 13 creates an output synchronization signal based on the coincidence pulse. For the next synchronization cycle in which the coincidence pulse no longer exists in the second detection window, the first detection window is created at the same time as the second detection window is created. At this time, the second lock signal changes from Hi to Low, and the first lock signal also changes to Low.
, The output synchronization signal is interpolated and protected according to the set number of interpolation protections for each synchronization cycle. Thus, the operation is repeated.

At the beginning of the operation or when the interpolation protection of the output synchronization signal continuously exceeds the set number of times of the interpolation protection, the first and second detection windows are both opened, and the first detection window receives a coincidence pulse. The second detection window is maintained in the open state until the first lock signal is changed from the locked state to the unlocked state.

By performing the above-described operations, a sufficient error protection can be applied to the burst error of the input signal in accordance with the set number of times of the interpolation protection, and at the same time, a large period of the synchronization signal due to disturbance or the like. Synchronous signals can be detected at high speed even for deviations, and the number of times the synchronous signals are protected can be reduced. That is, the synchronization can be accurately detected at high speed.

The first detection window creation circuit 11 and the second detection window creation circuit 12 are configured so that the detection window width can be freely set from outside. In the normal operation state, the detection window width for ± N clocks is set before and after the synchronization cycle by the synchronization cycle counter. However, when a disturbance signal indicating occurrence of disturbance is input, the detection window width is changed from ± N clocks to ± M clocks. Even if the width is widened by the number of clocks (M> N) and the synchronization period is disturbed, it is attempted to lock the synchronization.

However, there is a possibility that a synchronization pattern is generated in an area which is not originally a synchronization signal depending on an error in the reproduction signal. In particular, when disturbance occurs, the synchronization cycle is disturbed, and at the same time, the error occurrence probability of the reproduced signal itself increases. Then, the probability of occurrence of a synchronization pattern due to an error increases in a region other than the original synchronization signal, and there is a possibility that a synchronization pattern caused by the error is erroneously detected by widening the detection window width. Therefore, the detection window width of the synchronization detection may be widened if the synchronization cycle is disturbed, but it is considered that even if disturbance occurs, the normal state should be approached if the synchronization cycle is not so disturbed.

FIG. 3 is an explanatory diagram showing the setting processing of the detection window width. It is assumed that there is no disturbance before time t, and that a disturbance has occurred at time t. When a disturbance occurs, a disturbance signal indicating the occurrence of the disturbance is input and the detection window width is ± N
The width is expanded from the clock to ± M clocks (M> N). If the next synchronization pattern exists within the widened detection window width of ± M clocks, the detection window width is reduced to ± (M-1), and the next detection pattern width falls within ± (M-1). , The detection window width is further reduced to ± (M−2). If there is no synchronization pattern within the detection window width reduced to ± (M−X), the detection window width remains ± (M−X), and the detection window width becomes ± (M−X). If a synchronization pattern exists, the operation is performed in a direction to be contracted again.

By repeating this operation, the detection window width approaches the steady state, erroneous detection of the synchronization pattern outside the original synchronization signal area due to an error is avoided, and the synchronization signal is not affected by a period shift of the synchronization signal due to disturbance or the like. Can be reliably and stably detected.

FIG. 4 is an explanatory diagram showing another detection window width setting process. As before, it is assumed that a disturbance has occurred at time t. When a disturbance occurs, a disturbance signal indicating the occurrence of the disturbance is input, and the detection window width is increased from ± N clocks to ± M clocks (M> N). If there is a next synchronization pattern within the detection window width of the widened ± M clock, the detected synchronization position in the window is measured. If the synchronization position is located at + a or −a from the center of the detection window, the width of the detection window is reduced to ± (a + i), and the next synchronization pattern exists within the detection window width of ± (a + i) and the measured synchronization position Is located at + b or -b from the center of the detection window, the width of the detection window is further reduced to ± (b + i) (in FIG. 4, i = 0 is described). If the synchronization pattern does not exist within the detection window width, the detection window width maintains the state of ± (X + i). If the synchronization pattern exists within the detection window width of ± (X + i), the detection window width corresponds to the measured value X of the synchronization position. It works in the direction to be shrunk again. When the condition of ± (X + i) <= ± N is satisfied, the detection window width is in a steady state of ± N.

By repeating this operation, the detection window width is brought close to the steady state, erroneous detection of a synchronization pattern other than the original synchronization signal area due to an error is avoided, and the synchronization signal is not affected by a period shift of the synchronization signal due to disturbance or the like. Can be detected quickly and stably. In the above, i is an arbitrary constant of 0 or more.

FIG. 5 is an explanatory diagram showing still another detection window width setting process. In the first detection window creation circuit 11 and the second detection window creation circuit 12, the detection window width can be freely set from outside, and the minimum window width ± N1 and the maximum window width ± N2 are set. First, the maximum window width ± N2 is set as an initial value, and if the next synchronization pattern exists within the detection window width for the set ± N2 clocks, the detected synchronization position in the window is measured. . If the synchronization position is located at + a or −a from the center of the detection window, the detection window width is reduced to ± a, and the next synchronization pattern exists within the detection window width of ± a, and the measured synchronization position is the detection window width. If it is located at + b or -b from the center, the detection window width is further reduced to ± b, and aims at the set minimum window width ± N1.

When the detection window width is ± X and there is no synchronization pattern within the detection window width, the detection window width is ± (X +
If the synchronization pattern does not exist within the window width of ± (X + 1) that has been expanded to 1) and further expanded, the detection window width is ± (X
+2), and is expanded up to the maximum window width ± N2. That is, when the synchronization pattern does not exist in the detection window, it is when the synchronization detection protection circuit 13 performs the interpolation protection, and the width is increased according to the number of times of the interpolation protection.

If a synchronization pattern exists in the detection window,
The window width is reduced to the measured value of the synchronization position detected in the window,
If the synchronization pattern does not exist in the detection window, the operation of gradually increasing the current window width is repeated so that the detection window width is adaptively set between the set minimum window width ± N1 and the maximum window width ± N2. To ensure the synchronization signal in steady state operation,
Can be detected stably.

[0041]

According to the first aspect of the present invention, each time the period of the coincidence pulse fluctuates, the detection window is alternately synchronized with the synchronization period of the coincidence pulse using the first detection window and the second detection window. Therefore, even if the synchronization signal has a large cycle shift due to disturbance or the like, the synchronization signal can be detected quickly and reliably, and the number of times of protection can be reduced.

According to the second aspect of the present invention, the width of the detection window is increased in accordance with a disturbance signal indicating occurrence of disturbance, and the width of the window is reduced when a synchronization signal is detected in the window. In response to a large period shift of the synchronization signal due to
It is possible to perform stable detection and make the detection window width close to a steady state, thereby avoiding erroneous detection of a synchronization pattern other than the original synchronization signal region due to an error.

According to the third aspect of the present invention, the position of the detected synchronization within the detection window is measured and the window width is reduced in accordance with the measured value, so that the detection window width is more appropriately brought close to the steady state. In addition, it is possible to avoid erroneous detection of a synchronization pattern other than the original synchronization signal area due to an error.

According to the fourth aspect of the present invention, the width of the detection window for detecting the recorded synchronization signal and its period is increased in accordance with the number of times of interpolation protection. This has the effect of reliably and stably detecting.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a signal reproducing apparatus according to the present invention.

FIG. 2 is a timing chart of each circuit of the signal reproducing apparatus.

FIG. 3 is an explanatory diagram showing a detection window width setting process.

FIG. 4 is an explanatory diagram showing another detection window width setting process.

FIG. 5 is an explanatory diagram showing still another detection window width setting process.

FIG. 6 is a block diagram showing an example of a conventional signal reproducing device.

FIG. 7 is a timing chart of each circuit of a conventional signal reproducing device.

[Explanation of symbols]

 Reference Signs List 10 pattern comparison circuit 11 first detection window creation circuit 12 second detection window creation circuit 13 synchronization detection protection circuit

Claims (4)

[Claims] 1. A signal reproducing apparatus for reproducing a discrete signal recorded on a predetermined medium, comprising: a comparison circuit for comparing an input signal with a reference synchronization pattern having a constant period to generate a coincidence pulse; And a first detection window creation circuit for creating a first detection window of a predetermined width before and after the synchronization cycle, and a second detection window creation circuit of a predetermined width before and after another synchronization cycle of the coincidence pulse.
A second detection window creation circuit for creating a detection window, and a matching pulse based on the matching pulse when a matching pulse exists in the detection window and a matching pulse detected when no matching pulse exists in the detection window. A synchronization detection and protection circuit that performs interpolation protection for each pulse synchronization cycle and outputs a synchronization signal, wherein the first detection window creation circuit and the second detection window creation circuit include:
If one creates a detection window in the synchronization cycle of the coincidence pulse, the other does not create a detection window, and if one no longer has a coincidence pulse in the detection window, it uses the synchronization cycle up to that point. Along with creating a detection window only a fixed number of times, the other creates a detection window with a synchronization cycle of a coincidence pulse, and the synchronization detection protection circuit performs interpolation protection only when the detection window is created a fixed number of times. Characteristic signal reproducing device. 2. The method according to claim 1, wherein the detection window creation circuit widens the window width of the detection window in response to a disturbance, and reduces the window width when the coincidence pulse is detected in the detection window. The signal reproducing apparatus according to claim 1, wherein 3. The detection window creation circuit according to claim 2, wherein the position of the coincidence pulse detected in the detection window is measured, and the width of the window is reduced in accordance with the measured value. Signal reproduction device. 4. The signal reproducing apparatus according to claim 2, wherein the detection window creation circuit widens the window width of the detection window according to the number of times of interpolation protection.