JP2810288B2 - Clock recovery device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery device.

[0002]

2. Description of the Related Art A clock recovery circuit is used, for example, in an MSK demodulator. FIG. 6 shows a conventional clock recovery circuit. For example, 1.2 kHz as a detection result output from the delay detection circuit of the MSK demodulator
Alternatively, frequency information of 1.8 kHz is applied to each frame by Hi.
gh (“1”) or Low (“0”) (1.2
kHz is “1”, 1.8 kHz is “0”) RDATA
Is input to the edge detection circuit 1 and its rise and fall are detected. The FAST / SLOW control circuit 2 determines that the edge of the output RCLK of the counter 3 is RDATA.
Of the counter 3 is controlled so as to synchronize with the edge of.

[0003]

In the above-described clock recovery circuit, as long as the input data, that is, the frame width of "1" and the frame width of "0" in RDATA from the delay detection circuit are equal to each other, RCLK Is RDATA
, And there is no problem at all.

However, the RDA is affected by the offset and the like of the analog circuit used in the delay detection circuit.
The frame width of “1” and the frame width of “0” in TA may be different. In such a case, FAST /
The SLOW control circuit 2 changes the count number of the counter 3 by, for example, FAST → Synchronization → SLOW → Synchronization → FAST ...
Control is performed in such a manner as to fall into a so-called false lock (FALSE LOCK) state.
K cannot catch up with the edge of RDATA (ie, the edge of RCLK does not lock to the edge of RDATA).

Accordingly, an object of the present invention is to solve the above-mentioned problems and to provide a clock reproducing apparatus which does not perform FALSE LOCK even if the frame widths of input data "1" and "0" are different.

[0006]

According to the present invention, there is provided a reproducing clock generating means for generating a reproducing clock, and the reproducing clock generating means such that an edge of the reproducing clock from the reproducing clock generating means is locked to an edge of input data. A clock reproducing apparatus having a control means for controlling a frequency of the reproduced clock, and a frequency dividing means for generating a frequency-divided clock of the reproduced clock;
First means for outputting an exclusive OR of the divided clock and the input data; and second means for outputting an exclusive OR of the divided clock and the input data at the center of the latter half cycle of the reproduced clock. Means for unilaterally advancing or delaying the edge position of the reproduced clock in the reproduced clock generating means with respect to the edge of the input data until the output of the first means and the output of the second means have a predetermined relationship. Means for controlling the control means as described above.

[0007]

According to the present invention, the input data "1" and "0"
FALS by forced pull-in even if the frame width of
A reproduced clock that follows input data without E LOCK can be obtained.

[0008]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of a clock recovery circuit according to an embodiment of the present invention. 1 is an edge detection circuit, 21
Is a FAST / SLOW control circuit, 31 is a counter, and 41 is a FALSE LOCK prevention circuit. FIG.
Shows details of the clock recovery circuit. Figure 3 is FALSE
The operation of the LOCK prevention circuit will be described.

[0010] As shown in FIG.
NITN is generated every one cycle of RCLK, and FALS
The flip-flops (hereinafter also referred to as “FF”) F1 to F4 in the E LOCK prevention circuit 41 are initialized. As a result, initialization is performed for each cycle of RCLK, and the inverted Q output of F1 (inverted Q1) and the inverted Q output of F2 (inverted Q)
2), the Q output (Q3) of F3 becomes "1" (High),
The Q output (Q4) of F4 becomes "0" (Low). FA
Flip-flop F in LSE LOCK prevention circuit 41
CK600 as the Q output of No. 5 is a clock obtained by dividing the inverted RCLK by 2 (in this example, it changes at the falling edge of RCLK), and EXCLUSIVE- indicated by EX-OR1
The output XOR1 of the OR gate is an exclusive OR output of CK600 and RDATAI from the delay detection circuit. EX
-CLK1 as the output of OR2 indicates the value of XOR1 at the center of the first half cycle and the center of the second half cycle of RCLK as F1,
A clock for sampling to F2, and a clock CLK2 as an output of the NAND gate NAND1,
The 2-bit data (the value of XOR1) sampled in F1 and F2 by LK1 is loaded in parallel to F3 and F4. That is, the rising edge of CLK2 causes the Q output (Q3) of F3 to be at XO at the center of the latter half cycle of ROCK.
As the value of R1, the value of XOR1 at the center of the first half cycle of RCLK is obtained from the Q output (Q4) of F4, and the output FLOCKN of EX-OR3 to which these two values of XOR1 are input is "1". Indicates that the clock recovery circuit is in the normal lock state, and "0" indicates that the clock recovery circuit is in the FAIL LOCK state.

FIG. 3 (a) shows the above timings, and FIG. 3 (b) shows the exclusion of the RCLK and its CK600 which is a frequency-divided clock by 2 and the CK600 at the rising edge of the CLK2. (C) shows the relationship between the RDATAI edge and each position of the RDATAI edge for obtaining the logical OR output (XOR1), and FIG. Here is a truth table of the disjunction. That is, when this exclusive OR (output of EX-OR3) is "0", FALS
E LOCK state (The timing of CLK2A in FIG. 3A indicates this state, and the rising edge of RCLK does not coincide with the rising edge of RDATAI. Similarly, FIG. 4B also shows the FALSE LOCK state. At this time, the clock recovery circuit transitions to the forced pull-in state. In addition, when it is "1", it is in the normal clock state ((a) of FIG. 4).

The FALSE LOCK prevention circuit 41 is connected to the F6
S that detects the phase difference between RDATA and RCLK from
L2 and FA2 are output, and these are supplied to the FAST / SLOW control circuit 21.

According to the above configuration, FALSE LOC
In the K prevention circuit 41, F1 to F4 are initialized at the rise of RCLK, Q3 becomes "1" and Q4 becomes "0", and always transitions to the normal pull-in state, and at the rise of CLK2, Q3 / Q
If 4 is 1/0 or 0/1, FLOCKN remains 1 and does not transition to the forced retraction state. If Q3 / Q4 is 1/1 or 0/0 at the rise of CLK2, FL
Since OCKN becomes 0, the state transits to the forced retraction state, and F
The AST / SLOW control circuit 21 is FALSE
Based on the values of SL2 and FA2 from the LOCK prevention circuit 41, the counter 31 is forcibly SLOW-controlled or FAST-controlled until the next rising edge of RCLK until the Q3 / Q4 becomes 1/0 or 0/1. Continue the forced retraction state.

The above explanation is based on the assumption that CK600 is RCL
Although the circuit is configured to change at the falling edge of K, the circuit may be configured so that CK600 changes at the rising edge of RCLK. In this case, FIG.
As shown in the figure, the values of Q3 and Q4, which are the exclusive OR of CK600 and RDATAI, that is, Q3 / Q4 is 1 /
Since it is in the FALSE LOCK state when it is 0 or 0/1, it is only necessary to make a transition to forced retraction based on FLOCKN = 1, and to make a transition to the normal retraction state when Q3 / Q4 is 0/0 or 1/1. Just do it.

[0015]

As described above, according to the present invention, even if the frame width of "1" and "0" of the input data is different, FA
A clock recovery apparatus that does not perform LSE locking can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram of a clock recovery circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram showing details of the clock recovery circuit.

3A is a diagram showing an operation timing of a FALSE LOCK prevention circuit, and FIG. 3B is a diagram showing RCLK and CK6.
FIG. 9 is a diagram showing the relationship between 00 and each RDATAI, and (c)
FIG. 8 is a diagram showing a truth value of an exclusive OR of Q3 and Q4.

FIG. 4A is a diagram showing a normal clock state;
(B) is a figure showing a FALSE LOCK state.

FIG. 5 shows Q in another relationship between RCLK and CK600.
It is a figure which shows the control aspect based on the value of 3, Q4, and the result.

FIG. 6 is a block diagram of a conventional clock recovery circuit.

[Explanation of symbols]

F1-F5 Flip-flop EX-OR1-EX-OR3 EXCLUSIVE O
R gate 1 Edge detection circuit 21 FAST / SLOW control circuit 31 Counter 41 FALSE LOCK prevention circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-63-45934 (JP, A) JP-A-5-227017 (JP, A) JP-A-53-81056 (JP, A) JP-A-61-1986 66433 (JP, A) JP-A-3-8222 (JP, A) JP-A-56-104542 (JP, A) JP-A-2-121524 (JP, A) JP-A-2-166920 (JP, A) (58) Field surveyed (Int.Cl. ⁶ , DB name) H03L 7/00-7/095 G01R 25/00 H04L 7/00

Claims (1)

(57) [Claims] 1. A reproduction clock generating means for generating a reproduction clock, and control means for controlling the reproduction clock generation means so that an edge of the reproduction clock from the reproduction clock generation means is locked to an edge of input data. A clock regeneration device, wherein: a divide-by-2 means for generating a divide-by-two clock of the reproduced clock; and 1 means, 2nd means for outputting an exclusive OR of the divided-by-2 clock and the input data at the center of the latter half cycle of the reproduced clock, and wherein the output of the first means and the output of the second means are predetermined. The edge of the input clock is unilaterally advanced with respect to the edge of the input data until the relationship of Clock regeneration apparatus is characterized in that and means for controlling said control means so as Luke or delay.