JPH04246939A - Stuff jitter suppressing circuit - Google Patents

Abstract

PURPOSE:To extend a buffer memory capacity without affecting a phase comparing cycle of both a write clock and a read clock. CONSTITUTION:A write side M-divider 5 M-divides the write clock inputted to an input line 10, a read side M-divider 6 M-divides the read clock outputted from a digital PLL circuit 3, the phase of the M-divided write clock is compared with that of the M-divided read clock by an EX-OR circuit 7, and the phase information is outputted to the PLL circuit 3. And also, the read side M-divider 6 transmits the phase information to the write side M-divider 5 so that the M-divided write clock and read clock can be necessarily locked in the same state, and transmits a signal indicating this lock state to a read side N bit counter 4. In the same way, the write side M divider 5 transmits the signal indicating the lock state to a write side N bit counter 2.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention relates to a stuff jitter suppression circuit in a stuff synchronization system, and in particular, a stuff jitter suppression circuit including a digital PLL (phase locked loop) using triangular phase comparison using exclusive OR (EX-OR). Regarding circuits.

0002

[Prior Art] A conventional stuff jitter suppression circuit is shown in FIG.
As shown in the figure, there is a memory 1 that stores N bits of data input to an input line 9, and a write-side N-bit counter 2 that generates a clock for writing data to the memory 1 from a write clock input to an input line 10. and a digital PLL circuit 3 that controls the output frequency according to the input signal.
, a read-side N-bit counter 4 that generates a clock for reading data from the memory 1 from the read-out clock output from the digital PLL circuit 3, and a clock with an N-bit cycle output from the write-side N-bit counter 2. A frequency divider 13 that divides the frequency of the clock, a frequency divider 14 that divides the frequency of the N-bit cycle clock output from the read-side N-bit counter 4 by two, and a signal output from the frequency divider 13 that divides the clock frequency by two. It has an EX-OR circuit 7 that compares the phase with the signal output from the frequency generator 14, and an oscillator 8 that operates a digital PLL circuit.

The data input to the output line 9 is extended by N bits by N clocks generated by the write-side N-bit counter 2 and written into the memory 1, and is synchronized with the write clock by the digital PLL circuit 3. The data in the memory 1 is read out using N clocks generated by the N-bit counter 4 on the read side.

0004

[Problems to be Solved by the Invention] In this conventional stuff jitter suppression circuit, after dividing the N-bit period clocks from the N-bit counter on the writing side and the N-bit counter on the reading side by two, the phase is determined by an EX-OR circuit. For comparison, there was a problem in that expansion of the buffer memory capacity degraded the low-pass filter characteristics of the random walk filter in the digital PLL circuit.

An object of the present invention is to provide a stuff jitter suppression circuit that can expand buffer memory capacity without affecting the phase comparison period between a write clock and a read clock.

[0006]

[Means for Solving the Problems] The stuff jitter suppression circuit of the present invention includes a memory that stores N bits of input data, and a write side that generates a clock for writing data into the memory from an input write clock. N
a bit counter, a digital PLL (phase locked loop) circuit that controls an output frequency based on an input signal, and a read-side N-bit counter that generates a clock for reading data from the memory from a read clock output from the digital PLL circuit. and a write side M which divides the input write clock by M and outputs a signal informing the write side N-bit counter of the lock state.
a frequency divider, a signal that divides the read clock output from the digital PLL circuit by M and notifies the read side N-bit counter of the lock state, and the write side M
A read side M frequency divider outputs a signal informing phase information to the frequency divider, and an M output from the write side M frequency divider.
an exclusive OR circuit that compares the phases of the frequency-divided write clock and the M-divided read clock output from the read-side M frequency divider; and the digital PLL.
This configuration includes an oscillator that operates the circuit.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram of a stuff jitter suppression circuit according to an embodiment of the present invention. The stuff jitter suppression circuit includes a memory 1 that stores N bits of data input to an input line 9, and a write side N that generates a clock for writing data to the memory 1 from a write clock input to an input line 10.
A bit counter 2, a digital PLL circuit 3 that controls the output frequency based on an input signal, and a read side N that generates a clock for reading data from the memory 1 from the read clock output from the digital PLL circuit 3.
The bit counter 4, the write-side M frequency divider 5 which divides the write clock input to the input line 10 by M and outputs a signal informing the write-side N-bit counter 2 of the lock state, and the digital PLL circuit 3. A read-side M frequency divider 6 divides the read clock by M and outputs a signal informing the read-side N-bit counter 4 of the lock state and a signal informing the write-side M frequency divider 5 of phase information.
, the phases of the M-divided write clock output from the write-side M frequency divider 5 and the M-divided read clock output from the read-side M frequency divider 7 are compared.
It is composed of an X-OR circuit 7 and an oscillator 8 that operates the digital PLL circuit 3. 9 and 10 are input lines,
11 and 12 are output lines.

The operation will be explained below. The write-side M frequency divider 5 divides the write clock input into the input line 10 into M
The read-side M frequency divider 6 divides the read clock output from the digital PLL circuit 3 by M, and the M-divided write clock and M-divided read clock are connected to an EX-OR circuit. The phases are compared in step 7 and phase information is output to the digital PLL circuit 3. Also, read side M
The frequency divider 6 sends phase information to the write side M frequency divider 5 so that the write clock divided by M and the read clock divided by M are always locked in the same state, and furthermore, the frequency divider 6 sends phase information to the write side M frequency divider 5. A signal is sent to the bit counter 4 to notify it of this locked state. Similarly, the write-side M frequency divider 5 also sends a signal to the write-side N-bit counter 2 to notify it of the locked state.

The write-side N-bit counter 2 and the read-side N-bit counter 4 each use a signal informing the lock state as a trigger to generate N clocks with an N-bit period, and the write-side N-bit counter 2 uses a signal line 9
The data input to the memory 1 is written to the memory 1 using these N clocks, and conversely, the data input to the read side N bit counter 4 is written to the memory 1 by these N clocks.
reads data from memory 1 using these N clocks.

0010

As explained above, the present invention provides a write side M frequency divider that divides the write clock by M and a read clock that divides the frequency of the read clock by M, independently of the write side N-bit counter and the read side N bit counter. Since the read-side M frequency divider is provided, the buffer memory capacity can be expanded without affecting the phase comparison period between the write clock and the read clock.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram showing a conventional stuff jitter suppression circuit.

[Explanation of symbols]

1 Memory 2, 4 N-bit counter 3 Digital PLL circuit 5, 6 M frequency divider 7 Exclusive OR (EX-OR) circuit 8
Oscillator 9, 10 Input line 11, 12 Output line 13, 14 2 frequency divider

Claims (1)

[Claims] 1. A memory that stores N bits of input data, a write-side N-bit counter that generates a clock for writing data to the memory from an input write clock, and an output frequency that is controlled by an input signal. A digital PLL (phase locked loop) circuit, a read-side N-bit counter that generates a clock for reading data from the memory from the read clock output from the digital PLL circuit, and a read-side N-bit counter that divides the input write clock by M. a write-side M frequency divider that outputs a signal informing the write-side N-bit counter of a lock state; and a signal that divides the read clock output from the digital PLL circuit by M and informs the read-side N-bit counter of a lock state. and a read-side M frequency divider that outputs a signal informing the write-side M frequency divider of phase information; a write clock frequency-divided by M output from the write-side M frequency divider; and the read-side M frequency divider. an exclusive OR circuit that compares the phase with the M-divided read clock output from the digital
A stuff jitter suppression circuit comprising: an oscillator that operates an LL circuit.