JP2697322B2 - Phase locked loop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a phase locked loop (PLL) used for a transmitter, a receiver, and the like of a radio device, and more particularly to an improvement in a PLL frequency synthesizer.

[0002]

2. Description of the Related Art A PLL frequency synthesizer has a function of outputting a frequency which is an arbitrary multiple of a reference frequency.
FIG. 7 shows an example of the configuration.

FIG. 7 shows a reference frequency divider 8A which divides the oscillation frequency output from the crystal oscillator 5 and generates a reference frequency.
A phase comparison circuit 9 for detecting a phase difference between the reference frequency and the comparison frequency and outputting an error signal corresponding to the phase difference;
Charge pump circuit 10 for converting the error signal
A low-pass filter 11 for smoothing an output signal from the charge pump circuit 10 to generate a DC signal, a voltage-controlled oscillator 12 for changing an oscillation frequency according to the voltage level of the DC signal, and dividing and comparing the oscillation frequency. And a comparison frequency divider 8B for generating a frequency. Further, assuming that the division ratio is set in the reference divider 8A and the comparison divider 8B, a shift register 6 for serially inputting data of the division ratio and a data latch 7 for temporarily storing the data of the shift register 6 are provided.
A, 7B, a control register 31 for storing instruction data for selecting data transfer to one of the data latches 7A, 7B, a gate circuit LE for receiving a signal LE for instructing change of the frequency division ratio and information of the control register 31 1
3A and 13B.

The operation of the PLL frequency synthesizer will be described with reference to FIG. In the figure, in an initial state T0 after the power is turned on, the frequency division ratio data and the instruction data are simultaneously and serially written to the shift register 6 and the control register 31 in synchronization with the clock CK. At T1, the switching signal LE becomes high level, the data is transferred to the data latch 7A based on the instruction data, and the frequency division ratio of the reference frequency divider 8A is set. At T2, the frequency division ratio data set in the comparison frequency divider 8B is written into the shift register 6. T3
In this case, the division ratio data is transferred to the data latch 7B at the high level of the switching signal LE, and the division ratio is set to the comparison divider 8B.

During the period from T3 to T4, the phase comparison circuit 9 → the charge pump circuit 10 → the low pass filter 11 → the voltage controlled oscillator 12 → so that the output frequencies of the reference frequency divider 8A and the comparison frequency divider 8B match. The operation of shifting to the locked state is performed by the loop of the comparison frequency divider 8B. afterwards,
Output terminal frequency fv, which is the output of voltage controlled oscillator 12
To change co, during the period of T3 to T4, that is, during the lock state, the data of the frequency division ratio of the new comparison frequency divider is written into the shift register 6, and the switching signal LE becomes high. At the level T4, data is transferred to the data latch 7B and rewritten. Hereafter, T5, T6 ...
And the frequency f of the output terminal when the PLL is locked.
Each time a change in vco is required, that is, each time a frequency division ratio corresponding to the next required frequency needs to be rewritten, the frequency division ratio data of the comparison frequency divider is updated.

In this PLL frequency synthesizer, when the output frequency of the reference frequency divider 8A is fr and the output frequency of the frequency divider 8B is fv, when the PLL is locked, fr and fv have the same frequency. They have the same phase. This state is called that the PLL is locked. At this time, the output frequency fvco of the voltage controlled oscillator 12 is a frequency represented by the product of fr and the frequency division ratio N of the comparison frequency divider 8B, that is, fv
co = N × fr.

[0007]

Conventionally, in a transceiver using a PLL frequency synthesizer, for example, transmission and reception may be used at two different frequencies. P
As shown in FIG. 9, switching of the frequency of the LL frequency synthesizer is performed by inputting a channel of a frequency designated externally by input of a key or the like to the channel control circuit 1 and transmitting a control signal corresponding to the channel to the microcomputer 2. The microcomputer 2 reads the frequency division ratio data corresponding to the control signal from the memory, and writes the data as data in the shift register 6 of the PLL IC 4. The PLL / IC4 has
The above-described PLL frequency synthesizer of FIG. 7 is provided.

When transmission and reception are used at two different frequencies, the transmission and reception are usually performed alternately, so that the PLL frequency synthesizer generates the transmission and reception different frequencies alternately. Is required. That is, in the PLL frequency synthesizer, the operation of alternately transferring the two different frequency division ratios N1 and N2 to the data latch 7B is repeated.

With respect to such alternate writing of the dividing ratios N1 and N2 to the shift register or the register, in the conventional PLL frequency synthesizer of FIG. 7, new dividing ratio data is serially written to the shift register. However, there is a disadvantage that the operation from when the switching of the dividing ratio is instructed by a key input or the like until the actual switching is performed is long.

In the PLL frequency synthesizer shown in FIG. 7, when different frequency division ratio data is alternately written into a shift register or a register, the microcomputer 2 reads out the frequency division ratio data from the memory 3 every time the data is written. It is necessary to write to the shift register or register. Therefore, the processing from the reading of the frequency division ratio data to the memory 3 to the writing to the shift register or the register becomes frequent, so that the frequency of occurrence of erroneous data increases and the reliability decreases.

Therefore, in the present invention, as compared with the conventional PLL frequency synthesizer, the operation from instructing the switching of the new frequency division ratio to the actual switching is relatively fast, and the frequency of frequency division ratio switching is relatively high. It is an object of the present invention to provide a PLL frequency synthesizer in which the number of processes from reading of the frequency division ratio data to the memory 3 to writing to the shift register or the register performed every time is reduced.

[0012]

FIG. 1 is a diagram illustrating the principle of the present invention. In FIG. 1, reference numeral 40 denotes an oscillator, reference numeral 41 denotes a reference frequency divider, which converts the oscillation frequency of the oscillator 40 into an arbitrary frequency, and reference numeral 42 denotes a comparison circuit.
And outputs a frequency corresponding to a DC voltage obtained by smoothing a signal output according to the phase difference. Reference numeral 43 denotes a comparison frequency divider, which divides the frequency from the phase comparison circuit 42 by a predetermined frequency division ratio, and 451 to 45n denote a plurality of shift registers which divide the frequency given to the comparison frequency divider 43. Reference numeral 47 denotes a selection terminal for storing the ratio, one for selecting one of the plurality of shift registers 451 to 45n in response to an input signal, and 48 an output terminal. The above object is to provide a variable frequency divider which can set arbitrary frequency division ratio data,
A plurality of shift registers each storing different frequency division ratio data for the one variable frequency divider; and selectively dividing frequency ratio data stored in one of the plurality of shift registers. Means for transferring to said variable frequency divider, wherein said frequency division ratio data and a selection signal are provided, and said frequency division is performed to an arbitrary one of said plurality of shift registers corresponding to said selection signal. This is achieved by a phase-locked loop characterized by providing means for inputting ratio data.

[0013]

According to the present invention, in the configuration of FIG. 1, for example, data of a plurality of different frequency division ratios are stored in a plurality of registers 451 and 45n, and these data are selected and the variable frequency divider 43 is selected.
Has given to. Therefore, the time until the writing of the data of the new frequency division ratio is required similarly to the conventional PLL frequency synthesizer of FIG. 7, but after the setting, only the switching time of the register is used, and the new frequency division ratio is obtained. Since it is determined by the operation from when the data switching is instructed until the data is actually switched, the speed can be increased.

Since the frequency division ratio data stored in the plurality of registers 451 and 45n is selected,
Reading from the memory 3 and writing to the register every time the frequency division ratio is switched is only required to set new data of the frequency division ratio, and the set frequency can be reduced.

[0015]

FIG. 2 is a diagram showing an embodiment of the present invention. The difference between this embodiment and the PLL frequency synthesizer of FIG. 7 is that the shift registers 15A and 15B
.. Are provided, and the division ratio data to the shift registers 15A, 15B.
, And a switching signal L for providing the frequency division ratio data of each shift register 15A, 15B... To the data latches 7A, 7B.
, L2, terminals 201, 202 to which signals C1, C2,... For arbitrarily selecting the shift registers 15A, 15B,.
.. Has a signal line for supplying data of the frequency division ratio to the data latches 7A and 7B. The same components as those in FIG. 7 are denoted by the same reference numerals, and the description of the configuration will be omitted.

In the PLL frequency synthesizer shown in FIG. 2, the multiplexer 14 decodes the selection signal S and selects one of the shift registers 15A, 15B... To obtain the frequency division ratio data D read from the memory. Are distributed to the shift registers 15A, 15B,. The shift registers 15A, 15B,... Transfer the division ratio data written in the shift register corresponding to the input to the selected data latch 7A or 7B in response to the input of the switching signals L1, L2. It is configured to be.

As shown in FIG. 3, the data latch 7B includes a plurality of NAND circuits 17A to 17D.
The bit latch circuits 71, 72,... When the switching signal L2 becomes high level, each bit D1 to Dm of the m-bit division ratio data stored in one selected one of the plurality of shift registers 15A, 15B. .., 7m of the latch 7B, and are held. At the same time, each bit D1 to Dm of the frequency division ratio data is stored in a one-bit latch circuit 71, 72,.
Output from 7m and input to comparison frequency divider 8B. As shown in FIG. 4, the comparison frequency divider 8B includes a counter 21 including a plurality of flip-flops FF1 to FFm;
AND circuit 22 and three flip-flops FFa-F
And a circuit 23 made of Fc. The D input terminals of the flip-flops FF1 to FFm constituting the counter 21 are connected to the one-bit latch circuits 71, 72,
... Each bit D1 of frequency division ratio data output from 7m
To Dm are input. Load signal LOA in the figure
When D is low level, high level input data (D1
To Dm) are set to high level (the held information becomes “1”), and the flip-flops to which low-level input data (D1 to Dm) are input are set to low level. (The held information becomes “0”). That is, when the load signal LOAD is at a low level, the frequency division ratio data (D1 to Dm) output from the data latch 7B is set in the comparison frequency divider 8B. Next, when the load signal LOAD returns to the high level, the counter 21 starts counting down in synchronization with the clock signal CK. By the way, counter 2
1 reads the frequency division ratio data (D1 to Dm) when the load signal LOAD is at a low level, and loads the load signal LOAD.
Starts counting down when the clock signal CK returns to the high level. However, when the frequency of the clock signal CK increases and the counter operation speeds up, the frequency division ratio data (D1 to D1) is restored within the period in which the load signal LOAD is at the low level. Dm) may not be read correctly. In order to prevent this, in the embodiment of FIG. 4, a so-called "frequency extender circuit by early decoding" is provided by a NAND circuit 22 and a circuit 23 composed of three flip-flops.
And the load signal LOAD is generated by this circuit. That is, the input side of the NAND circuit 22 has F
The Q output of F3 and all other FFs (FF1, FF2,
The inverted Q outputs of FF4 to FFm) are connected. Therefore, when the counter 21 counts down and only the value held in the FF3 goes high (FF3 is the third FF counting from the lowest, the count value of the counter 21 is "4" in decimal notation. ), The NAND circuit 22 operates to output a low-level signal. Then, in the next clock cycle (when the count value of the counter 21 is “3” in decimal notation), the low level signal is shifted to the Q output side of the flip-flop FFa of the circuit 23. Similarly, the low-level signal is shifted in the order of FFb and FFa, and in the clock cycle in which the count value of the counter 21 becomes “1” in decimal notation, the low-level load signal LOAD is output from the Q output terminal of the FFc. Is output as Since the load signal LOAD is at the low level at the start of the next clock cycle (when the count value of the counter 21 is “0” in decimal notation), each flip-flop FF of the counter 21
1 to FFm receive new bits D1 to Dm of the frequency division ratio data from the respective D input terminals. As described above, the detection of the end of the down-counting of the counter 21 by the decoder (NAND circuit 22) is performed before the down-counting is actually ended (the count value of the counter 21 is “4” in decimal notation).
), The load signal L at the start of the clock cycle whose count value is “0” in decimal notation
OAD is definitely set to low level. Therefore, even if the frequency of the clock signal CK increases and the counter operation speeds up, the new frequency division ratio data D1 to D1
Dm can be read.

Next, the operation of the PLL frequency synthesizer of the present embodiment will be described with reference to the system configuration diagram of FIG. 5 and the operation explanatory diagram of FIG. For the sake of simplicity, it is assumed that there are two shift registers 15A, 15B.

At T0 after power-on and reset, the microcomputer 2 automatically supplies the frequency division ratio data to the reference frequency divider 8A to the PLL IC 4 via the memory 3. In the PLL IC 4, the frequency division ratio data is synchronized with the clock CK to shift the shift register 15A or 15B.
Write serially to. A control bit is added to the frequency division ratio data to specify which of the reference frequency divider 8A and the comparison frequency divider 8B is the frequency division ratio data.
It is stored in the control register 31. Here, when the control bit is "1", the reference frequency divider 8A
It is assumed that data is sent to the comparison frequency divider 8B when it is “0”. At the time of T0, the division ratio data N of the reference divider 8A
Assuming that "1" is stored in the control register as the setting of 1, the signal L1 becomes high level, so that the reference frequency divider 8 stored in the shift register 15A is set.
The division ratio data N1 of A is transferred to the data latch 7A. In the case of T1, the microcomputer 2 reads out the data N2 of the frequency division ratio corresponding to the channel information from the memory 3 based on the information of the channel of the transmission frequency, for example, which is input to the channel control circuit 1 of FIG. ,
The data is provided to a PLL IC 4 constituting the PLL frequency synthesizer of FIG. In the PLL IC 4, a selection signal S is input from the microcomputer 3 (or from an external terminal) to the multiplexer 14, and the shift register 15A side is selected by the decoded high level, and the shift register 15A is selected in response to the clock CK. The frequency division ratio data N2 serially written in 15A is held. At the time of T2, the same operation as the operation at the time of T1 is performed, and the frequency division ratio data N3 corresponding to the channel information of the reception frequency input to the channel control circuit 1 by key input or the like is obtained.
The data is written to the shift register 15B side selected by the decode output of the selection signal S, and the frequency division ratio data N3 is held. As described above, the dividing ratio data N is stored in the reference divider 8A.
1 is set, and the data N2, 1 are stored in the shift register 15A.
This means that N3 is stored in 5B.

As shown in T3 and thereafter, the data of the frequency division ratio corresponding to the frequency required for transmission and reception is set to L1 or L2 to a high level to set the data in the comparison frequency divider. From 15B, the frequency division ratio is set in the comparison frequency divider 8A. Therefore, unless the transmission or reception frequency is newly changed, the transmission or reception frequency can be switched by switching the signals L1 and L2. In the control register 31, information of "1" instructing writing from the microcomputer 2 to the data latch 7A side is instructed by..., And is shifted to the data latch 7A in response to a signal LE given by. The data stored in the register 6 is transferred.

When the transmission or reception frequency is newly changed, the data of the new frequency division ratio is stored in the shift register holding the data of the frequency division ratio to be changed by the same operation at T1. May be held.

When there are a plurality of shift registers, the above-described writing of the frequency division ratio data into the shift registers at T2 may be repeated. In addition, a plurality of shift registers 15
The shift register to be written into the data latch 7B among A, 15B,... May be selected using signals C1, C2,.

As described above, in this embodiment, the switching of the output frequency is performed by providing the shift registers 15A, 15B,... And switching the different frequency division ratio data held therein. Therefore, the shift registers 15A,
Although writing time of new frequency division ratio data to 15B is required, after writing, only the switching time of the shift register is required, and after the instruction to switch the data of the new frequency division ratio is issued, the data is actually switched. The speed is determined by the operation.
In addition, since the data of the frequency division ratio held in the shift registers 15A and 15B is selected, every time the frequency division ratio is switched, reading from the memory 3 and writing to the shift register are performed with new data of the frequency division ratio. Need only be set, and the number of settings can be reduced.

[0024]

According to the present invention, the division ratio is switched by selecting a plurality of registers storing the division ratio data, so that the new division ratio data can be switched. The time from instructing to actually switching can be shortened. In addition, the writing from the memory to the read register every time the frequency division ratio is switched is performed only when new frequency division ratio data is set, so that the number of times of setting can be reduced, and the effect of improving reliability is exhibited. .

[Brief description of the drawings]

FIG. 1 is a principle configuration diagram of a phase locked loop circuit of the present invention.

FIG. 2 is a configuration diagram of a PLL frequency synthesizer showing one embodiment of the present invention.

FIG. 3 is a configuration diagram of data latches 7A and 7B in FIG. 2;

FIG. 4 is a configuration diagram of a comparison frequency divider 8B in FIG. 2;

FIG. 5 is a system configuration diagram of a PLL frequency synthesizer of an embodiment.

FIG. 6 is an operation explanatory diagram of the PLL frequency synthesizer of the embodiment.

FIG. 7 is a configuration diagram of a conventional PLL frequency synthesizer.

FIG. 8 is a diagram illustrating the operation of a conventional PLL frequency synthesizer.

FIG. 9 is a system configuration diagram of a conventional PLL frequency synthesizer.

[Explanation of symbols]

 Reference Signs List 1 channel control circuit 2 microcomputer 3 memory 4 PLL IC 5 crystal oscillator 6, 15A, 15B, 451 to 45n shift register 7A, 7B data latch 8A reference frequency divider 8B comparison frequency divider 9 phase comparator 10 charge pump 11 low pass Filter 12 Voltage controlled oscillator 14 Multiplexer 41 Reference frequency divider 42 Variable frequency divider 48 Output terminal

Continuation of the front page (56) References JP-A-54-60511 (JP, A) JP-A-2-170720 (JP, A) JP-A-2-94710 (JP, A) JP-A-53-92616 (JP) , A) JP-A-53-90811 (JP, A)

Claims (2)

(57) [Claims] 1. A variable frequency divider capable of setting arbitrary frequency division ratio data, a plurality of shift registers each storing different frequency division ratio data for the one variable frequency divider, and the plurality of shift registers Means for selectively transferring the frequency division ratio data stored in one of the shift registers to the variable frequency divider, wherein the frequency division ratio data and a selection signal are provided, A phase synchronization circuit comprising: means for inputting the frequency division ratio data to an arbitrary shift register corresponding to the selection signal among a plurality of shift registers. 2. A means for inputting frequency division ratio data to the shift register, decodes the selection signal, selects an arbitrary shift register from a plurality of shift registers, and selects the frequency division ratio data from the selected shift register. 2. The phase synchronization circuit according to claim 1, wherein the phase synchronization circuit is a multiplexer that inputs the data to the shift register.