JPH04132048A - Pll false lock detection circuit - Google Patents

Abstract

PURPOSE:To detect the false lock of a PLL, and to properly decide the abnormality of the PLL by detecting an (n+1)T or an (n-1)T pattern existing in the nT patterns of an input signal. CONSTITUTION:Flip flops 1, 2 synchronize a binary reproduced signal inputted to this false lock detection circuit with a clock generated by the PLL. A shift register 3 serial/parallel-converts synchronized data. Then, gates 4 to 9 detect the (n+1)T pattern or the (n-1)T pattern existing between the nT pattern and the nT pattern. Thus, the false lock of the PLL can be detected, and the abnormality of the PLL can be properly decided without being influenced by the defect of other signals.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is directed to a PL used in information recording devices, communication devices, etc.
Regarding the L circuit.

[Prior Art] Conventionally, information recording devices and communication devices that do not have a dedicated clock signal use a PLL circuit to generate a synchronized clock when reproducing information.

In this PLL circuit, for example, a pattern of a constant period included in a reproduced signal from a recording medium is input, and a clock synchronized with the pattern is generated from this pattern. That is, assuming that the cycle of the synchronization clock to be generated is T, the reproduced signal includes a pattern (VFO pattern) with an nT cycle for activating and pulling in the PLL.

FIG. 2 is a schematic diagram showing an example of a sector format of a rewritable optical disc.

The part labeled -1'VFO1, VFO2, and VFO3 in the middle is a part installed for pulling in the PLL, and a 3T pattern consisting of repeating "010" is recorded in this part. That is, this is the case when n=3.

3g is a block diagram showing an example of an optical disc reproducing circuit.

This reproduction circuit includes a detector 32 that detects a reproduction signal from a recording medium 31, a binarization circuit 33 that binarizes this detection signal, and a sector mark detector that detects sector marks from this binary reproduction signal. a read gate generation circuit 35 that generates a read gate signal from the sector mark detected here, a PLL circuit 36 that generates a clock from the read gate signal and the binary reproduction signal, A synchronization signal detection circuit 37 that generates a synchronization signal from a binary reproduction signal, a decoder 38 that decodes the binary reproduction signal, an address recognition circuit 39 that recognizes an address from decoded data, and an error correction circuit that performs error correction on the decoded data. It has a correction circuit 40 and a buffer 41 for sending decoded data to a host computer via an interface.

FIG. 4 is a block diagram showing a general example of the PLL circuit 36.

This PLL circuit 36 includes a reference oscillator 42, a pulse gate circuit 43 that operates based on a binary reproduction signal, and a changeover switch 44 that is controlled by a read gate signal.
, a phase comparator 45 , a charge pump 46 , and a voltage controlled oscillator (VC0) 47 .

In this PLL circuit 36, when the read gate is closed, the two inputs of the 1-phase comparator 45 are connected to the reference oscillator 42.
and the VCO 47 are connected, and the clock of the VCO 47 approaches the same frequency and phase as the reference oscillator 42.The pulse gate 43 compares the pulse with the binary reproduction signal pulse every time it is inputted.5VCO clock pulse Let one pass through. Furthermore, when the binary reproduction signal pulse is not input, the pulse gate is also cut off.

On the other hand, when the read gate is opened, phase comparison is performed once each time a binary reproduction signal is input. Furthermore, when a binary reproduction signal is not input, one-phase comparison is not performed, the output value of the charge pump 46 is saved, and the frequency and phase of the clock output by the VCO 47 are also held.

When a signal having a format as shown in FIG. 2 is input to such a PLL circuit 36, the following three steps of operation are performed.

(1) First, in the part before the VFOI, the read gate is closed, then the changeover switch 44 is connected to the lower contact, and the PLL circuit 36 is connected.

During this time, the frequency is pulled in using the clock of the reference oscillator 42.

(2) Next, when the VFOI is entered, the read gate is opened, and the changeover switch 44 is connected to the upper contact point as shown in FIG. Performs phase pull-in.

(3) According to (1) and (2) above, the synchronization signal (A
When the signal M) is input, the PLL clock is synchronized (locked) with the input signal in both frequency and phase, so that AM can be detected.

[Problems to be Solved by the Invention] By the way, if there is no abnormality in the input signal, the above-mentioned operation is performed by the PLL circuit 36, and there is no problem. , or due to noise generated on the transmission path, the VFO
Even in patterns, pulse dropouts (dropouts), extra pulses (extra pulses), and even large pulse phase shifts (bit shifts) may occur.

In particular, if a dropout or extra pulse occurs at the time of switching between (1) and (2) above in PLL operation,
PLLs may malfunction, in which case the PLL may reach another stable state. This state is called a pseudo-lock.

Fifth. , is a time chart showing four examples of pseudo locks.

As shown from ■ to @ in the figure, the locking frequency during pseudo-locking is (3n+1)/3n during normal locking, and (4n+1)/3n during normal locking.
4n, (5n+1)15n... or (3
n-1)/3n, (4n-1)/4n, (5n-1)1
5n..., where m is a positive integer, ((mn+ 1)/mn) F or ((mn
-1)/mn) Takes the value F.

Generally, when the free-running frequency of the VFO is higher than the target frequency, ((mn+1)/mn) F tends to appear,
When the value is low, ((mn-1)/mn)F tends to appear.

Pseudo-locking of the PLL is likely to occur due to discontinuity in the characteristics of the phase comparator 45 or nonlinearity in the FV characteristics of the VCO 47. Furthermore, even if the same defective signal is input to the same device, it may or may not occur depending on the phase difference between the input signal and the clock of the reference oscillator 42, so the reproducibility of this event is poor.

FIG. 6 is a schematic diagram showing the input/output frequency characteristics of the PLL.

In the figure, the line f=nF indicates normal operation, and the lines on both sides of it indicate pseudo-lock.

The input frequency is the free running frequency of VCO 47 or the reference oscillator 4.
When the clock frequency becomes higher or lower than 2, false locks tend to occur.

When the PLL is pseudo-locked, addresses and data cannot be reproduced, and synchronization signals cannot be detected.

Therefore, if the PLL becomes pseudo-locked, the PLL should be restarted, the clock of the reference oscillator 42 should be input, and the frequency should be pulled in again.

However, once the PLL locks normally.

It is better not to restart the PLL, as it is unlikely to enter a pseudo-locked state or become unstable.

Therefore, the following method can be considered as a method of controlling restart of the PLL.

First, according to the format shown in FIG. 2, there is an AM after the VFOI, followed by an ID, and within the ID there is a CRC for error detection. Therefore, if the ID is not reproduced correctly using this CRC,
The first method is to restart the PLL within the next VCO2 area.
It can be considered. The flow of the CRC error signal at this time is explained in the third section.
Indicated by a broken line in the figure.

In addition, the PL
Another possible method is to restart L. The flow of the synchronization signal detection error signal at this time is shown by a dotted line in FIG.

However, in any of these methods, it is difficult to determine whether these errors are caused by an abnormality in the PLL operation, or whether the PLL is operating normally but there is a defect in the signal and the error is determined to be an error. I don't understand.

Also, I investigated the pattern when synchronizing the VFO pattern with the PLL clock, and found that 100100100...
There is also a method of counting the repetition of the same pattern of nT, determining that the PLL is locked when it continues for a predetermined number of times, and restarting the PLL as an abnormality if not.

However, when there is a signal defect in the VFO pattern, it may be determined as an error even though the PLL is normally locked.

The present invention provides a PLL that can appropriately determine whether the PLL is normal or abnormal and can restart the PLL correctly.
An object of the present invention is to provide a LL pseudo-lock detection circuit.

[Means for Solving the Problems] The present invention provides a PLL circuit that generates a clock with a period T synchronized with a pattern of a constant period nT (n is an integer) included in an input signal, in which the input signal is synchronized with the PLL clock. Regarding the pattern when the pattern is converted into
-1) It is characterized by detecting whether the PLL is operating normally by detecting the T pattern.

[Operation] In the present invention, the pattern when the input is synchronized with the PLL clock is recognized, and the (n+1)T pattern between the nT pattern and the nT pattern or between the nT pattern and the nT pattern is detected. Since a false lock of the PLL is detected by detecting a certain (n-1)T pattern, an abnormality in the PLL can be appropriately determined without being affected by defects in other signals.

〔Example] FIG. 1 is a circuit diagram showing one embodiment of the present invention.

Further, FIGS. 7(1) to (3) are time charts illustrating the operation of this PLL pseudo lock detection circuit.

In FIG. 1, flip-flops 1 and 2 synchronize the binary reproduction signal input to the pseudo lock detection circuit with the clock generated by the PLL. That is, synchronous data synchronized with the clock is determined by the position of the rising edge of the binary reproduction signal with respect to the falling edge of the clock. Note that the synchronization data shown in FIG. 5 described above is also generated by this circuit.

Next, the shift register 3 performs serial/parallel conversion on the synchronous data. Then, when the pattern input to the shift register 3 is "10010001001", the AND circuit 4.6 and the NOR circuit 5 perform an AND operation.
“l” is output to the output terminal A of the circuit 4.

Also, the pattern input to the shift register is 1001
01001”, AND circuit 7.9 and NOR
The circuit 8 outputs l'' to the output terminal B of the AND circuit 9.

If the detection pulse of either output terminal A or H passes through the OR circuit 12 and falls within the window formed by the flip-flop lO, "1" is output to the Q output C, and a PLL error is detected in the flip-flop 11. Output.

That is, within the window, within the nT pattern (n+1
)T pattern or (n-1)T pattern is present, an error will be detected. However, this example is a case where n=3.

FIG. 8 is a time chart showing an example of window settings.

As shown in the figure, it is effective to use the window memory in the latter half of the VFO pattern when the PLL operation is stable.

FIG. 7 (1) shows that the pseudo lock detection circuit of this embodiment has a fifth
It is a time chart when the pseudo lock signal shown in the figure [stock] is input. In this case, “100101” is displayed in the window.
001” pattern and outputs an error signal.

FIG. 7 (2) shows that the pseudo lock detection circuit of this embodiment has a fifth
It is a time chart when the pseudo lock signal of figure [phase] is input. In this case, “100100” is displayed in the window.
01001” pattern and outputs an error signal.

FIG. 7(3) shows a case where there is a defect in the reproduced signal, and the section a in FIG. 0 is a normal 3T pattern with no defects.

Furthermore, a pulse is missing in part b. Furthermore, C
A bit shift occurs in the part. In either of these cases, no PLL error is detected.

FIG. 9 is a time chart showing an example of a read gate control method using the pseudo lock detection circuit of this embodiment.

If there is no PLL error, it is best to open the read gate once in the preformat section and the data section as shown in the figure.If a PLL error is detected by the 6 circuits, close the read gate and restart the PLL. You can restart the PLL as soon as an error is detected, as in read gate α, or leave it as is until the first ID is played, as in read gate β. Another possible method is to restart the PLL in the second VFO area.

As described above, in this example, due to the reproduction signal defect, P
When a LL pseudo-lock occurs, it can be quickly detected and the PLL can be restarted.

As a result, even when there are many reproduction signal defects, it is possible to reduce the incidence of reproduction failure caused by the PLL not being properly locked.

Furthermore, even if there are signal defects such as dropouts, extra pulses, and bit shifts within the VFO pattern area, the pseudo-lock state of the PLL can be correctly determined.

Furthermore, it is convenient to use the circuit of the present invention when measuring characteristics such as the pull-in range and lock-in range of a PLL.

Also, when data is not played correctly, the cause may be P.
Is it due to LL pseudo lock or other cause 1?
For example, it can be determined whether there is a signal defect in the data section.

[Effects of the Invention] According to the present invention, (
By detecting the nil)T pattern or the (n-1)T pattern, PLL pseudo-lock is detected, so it is possible to appropriately determine PLL abnormality without being affected by other signal defects. can.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention. FIG. 2 is a schematic diagram showing an example of a sector format of a conventional rewritable optical disc. FIG. 3 is a block diagram showing an example of a conventional optical disc reproducing circuit. FIG. 4 is a block diagram showing an example of a conventional PLL circuit. FIG. 5 is a time chart showing four examples of pseudo-locking of the PLL circuit. FIG. 6 is a schematic diagram showing the input/output frequency characteristics of the PLL circuit. FIGS. 7(1) to (3) are time charts illustrating the operation of the PLL pseudo-lock detection circuit of the above embodiment. FIG. 8 is a time chart showing an example of window settings in the above embodiment. FIG. 9 is a time chart showing an example of a read gate control method using the pseudo lock detection circuit of the above embodiment. l, 2, 10.11...Flip-flop, 3...
Shift register, 4.6.7.9...AND circuit, 5.6...NOR circuit, 12...OR circuit. Patent Applicant: Canon Co., Ltd. Kubo Shin 7y-7-7 Try'/'F Figure 6 Input Sake Moromi 49 Figure 8 Figure 7 (1) RiO Tsuku 1JIS1fL ``----- Figure 7 (2) PLlj5-

Claims (2)

[Claims] (1) In a PLL circuit that generates a clock with a period T synchronized with a pattern with a constant period nT (n is an integer) included in an input signal, the pattern when the input signal is synchronized with the PLL clock is nT. To detect whether the PLL is operating normally by detecting the (n+1)T pattern between the pattern and the nT pattern or the (n-1)T pattern between the nT pattern and the nT pattern. A PLL pseudo lock detection circuit characterized by: (2) The PLL circuit according to claim (1), wherein when it is determined that the PLL is not operating normally, the PLL is restarted anew.