JPH0735498Y2 - Sync signal detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a synchronizing signal generating circuit for reproducing digital data recorded by a rotary head type magnetic recording device by a rotary reproducing head.

[Prior Art] FIG. 4 is a block diagram showing a conventional sync signal (hereinafter referred to as SYNC signal) detection circuit. In FIG. 4, (11) is a gate pulse generation circuit and (12) is a protection SYNC signal. Generator circuit (13) for gating the detected SYNC signal
AND gate, (14) gated detect SYNC signal and protection S
OR gate for passing both YNC signals, (15) is output S
This is a YNC signal counter.

Next, the operation of the above configuration will be described based on the time chart of FIG.

First, before the frame, the block gate pulse is in the open state, the gate is closed by the first detected SYNC signal, the clock is counted by 1 block from there, and the block gate pulse is opened. The SYNC signal detected while the gate is open is output from the AND gate (13), but the pseudo SYNC signal detected while the gate is closed is not output.
Also, the blocks are counted one block at a time, and the protection SYNC signal generation circuit (12) generates the protection SYNC signal where the SYNC signal should be, and when the detected SYNC signal is not available, this is used as the SYNC signal for the OR gate. Output from (14).

The timing lag between the gate pulse generation circuit (11) and the protection SYNC signal generation circuit (12) is reset by the output SYNC signal to maintain synchronization.

Further, the output SYNC signal is counted by the counter (15), and the block gate pulse is kept open by the set block count number.

[Problems to be solved by the invention] Since the conventional sync signal detection circuit is configured as described above, there is a pseudo SYNC signal before the frame or the first SYNC signal of the frame cannot be detected. In this case, there is a problem that the initial setting of the gate pulse generation circuit (11) is deviated, and the deviation of the gate pulse causes the protection SYNC signal to occur at the wrong position.

This invention was made in order to solve the above problems, even if the first SYNC signal of the frame cannot be detected, or if there is a pseudo SYNC signal before the frame, the shift of the gate pulse, An object of the present invention is to provide a sync signal detection circuit that can minimize the generation of an erroneous protection SYNC signal.

[Means for Solving the Problems] A sync signal detection circuit according to the present invention includes a sync signal and a plurality of data following the sync signal as one block, and n (n is 2)
A frame gate opening / closing means for opening a frame gate indicating a valid section of data on the basis of a switching signal of a rotary reproducing head for reproducing digital data which composes one frame by the above (integer) blocks, and a clock for each block. Gate pulse generation means for generating a block gate pulse by counting, protection synchronization signal generation means for generating a protection synchronization signal by counting the clocks in units of the blocks based on the head switching signal, and the frame A synchronization signal output means for outputting a synchronization signal from both of the detection synchronization signal detected in the block gate pulse section and the protection synchronization signal while the gate is open, and the synchronization output from the synchronization signal output means If n signals corresponding to the number of blocks in one frame are counted, Frame gating means is characterized by being configured to close the frame gate.

[Operation] According to the present invention, since the block gate pulse and the protection SYNC signal are generated on the basis of the switching signal of the rotary reproduction head, the pseudo SYNC which is erroneously detected at the position where no data originally exists.
Even if the signal is not picked up and the first SYNC signal of the frame cannot be detected, the protection SYNC signal can prevent the loss of the SYNC signal. Further, since the frame gate of the gate pulse generating circuit is closed by the count number of the set block, there is no fear of outputting an extra signal.

[Embodiment of the Invention] An embodiment of the invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a synchronizing signal detecting circuit according to an embodiment of the present invention. In FIG. 1, (11) is a gate pulse generating circuit, (12) is a protective SYNC signal generating circuit, and (1)
3) is an AND gate for gating the detected SYNC signal, (14) is an OR gate for passing both the gated detected SYNC signal and protection SYNC signal, and (15) is a counter for the output SYNC signal. However, these configurations are the same as those of the conventional example shown in FIG. 4, except that the A head and B head during reproduction are different.
The head switching signal of the head is inputted to the gate pulse generating circuit (11), and the block gate pulse and the protection SYNC signal are generated on the basis of the head switching signal.

FIG. 3 shows, for example, two rotating heads (A) facing each other by 180 °.
FIG. 3 is a data pattern diagram in which a magnetic tape is recorded by winding 180 ° by using (B) and (B).
The recorded digital data is composed of a SYNC signal and a plurality of data (1,2,3 ... k) following it as one block, and the plurality of blocks (1,2,3 ... n-1, n) form one frame. Make up.

Next, the operation of the above configuration will be described based on the time chart of FIG.

First, with reference to the rising edge of the head switching signal,
The position where the first SYNC signal should exist is found by counting the clock, and the frame gate is opened from that position. It also generates a protective SYNC signal. As a result, the false SYNC signal erroneously detected before the frame is removed except when it is extremely close to the original SYNC signal position.

In addition, even if the first SYNC signal cannot be detected, there is a protected SYNC signal, which enables approximate alignment.

Continuing, the clock is counted, and a block gate pulse is generated from the gate pulse generation circuit (11) for each block, and among the detected SYNC signals, only the SYNC signal near the position where the original SYNC signal should be is output from the AND gate (13). Output. If the SYNC signal is not detected, use the protection SYNC signal generated from the protection SYNC signal generation circuit (12) to supplement OR
By outputting from the gate (14), SYNC without loss
Can detect signals. The gate pulse generator circuit (11)
The timing difference between the protection SYNC signal generation circuit (12) and
The output of the SYNC signal is reset to maintain synchronization, and the counter (15) counts the output SYNC signal, and the gate pulse generation circuit (1
Close the frame gate in 1).

The above clock may be a bit clock or a symbol clock as long as it is a clock synchronized with data.

Further, the output data may be provided with another gate, or a block address may be provided in the data to check the data so as to prevent the shift or loss of the data.

Further, the data to be recorded may include a code for error correction, a block address, etc. in the data.

Further, the number of rotary heads and the winding angle of the magnetic tape may be set arbitrarily, and the polarities of the signals can be set arbitrarily by the peripheral circuit if they function in the same manner as described above.

[Effects of the Invention] As described above, according to the present invention, the gate pulse for detecting the SYNC signal and the protection SYNC signal are generated based on the switching signal of the reproduction head, so that the pseudo SYNC signal before and after the frame is generated. Can be suppressed as much as possible, the lack of the SYNC signal at the beginning of the frame can be compensated for, and there is no possibility that an extra signal is output from the gate pulse generation circuit. Further, as a result, when the data is not completely clogged between the head switching signals, the pseudo sync signal appearing in the area other than the data may cause synchronization disturbance, or the already reproduced normal data may be overwritten with erroneous data. You can prevent mistakes. Therefore, in the rotary head type magnetic recording / reproducing apparatus to which the present invention is applied, it is possible to significantly suppress signal disturbance due to head switching.

[Brief description of drawings]

FIG. 1 is a block diagram showing a sync signal detection circuit according to an embodiment of the present invention, and FIG. 2 is a time chart showing the operation.
FIG. 3 is a recording / reproducing data pattern, FIG. 4 is a block diagram showing a conventional synchronizing signal detecting circuit, and FIG. 5 is a time chart showing the operation of FIG. (11) ... Gate pulse generation circuit, (12) ... Protection SYNC signal generation circuit, (13) ... AND gate, (14) ... OR gate, (1
5)… Counter. The same reference numerals in the drawings indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] 1. A sync signal and a plurality of data following the sync signal
A frame gate opening / closing means for opening a frame gate indicating a valid section of data, based on a switching signal of a rotary reproducing head that reproduces digital data that composes one frame by n blocks (n is an integer of 2 or more) A gate pulse generating means for generating a block gate pulse by counting a clock in units of the block; and a protection synchronization signal in counting the clock in units of the block based on the head switching signal. A protection synchronization signal generating means; and a synchronization signal output means for outputting a synchronization signal from both of the detection synchronization signal detected in the block gate pulse section and the protection synchronization signal while the frame gate is open, The sync signal output from the sync signal output means is set to the above 1
A synchronizing signal detecting circuit, characterized in that the frame gate opening / closing means is configured to close the frame gate when counting n corresponding to the number of blocks of a frame.