JPS5950644A - Synchronizing signal protecting device - Google Patents

Abstract

PURPOSE:To protect a frame synchronizing signal in an optimum state, by switching the number of protection frames in response to the state of supply of a signal including a frame synchronizing pattern and a digital signal. CONSTITUTION:An FF33 is reset at all times by a detected output of a synchronism detecting circuit 32 when a synchronizing pattern detecting signal is to be accommodated in a window pulse, and the number of protection frames N detected at a protection frame number detecting circuit 37 is set to, e.g., 13. Then, since a synchronizing signal protector 31 protects the synchronizing signal with a comparatively large number, 13 in this case, of the protection frame number N, the optimum operation to prevent adverse effect due to the generation of random error, etc. is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a synchronization signal protection device suitable for, for example, a digital disc player, which protects a synchronization signal extracted from a reproduction signal of a digital disc.

[Technical background of the invention and its problems] Recently, audio signals have been converted into digital data signals (PCM).
A digital audio disc (DAD) (hereinafter simply referred to as a disc) recorded on a disc with uneven pit sequences and a digital disc player that optically detects the bit sequence of this disc and reproduces the original audio signal have been developed. There are n. Nowadays, it has become possible to reproduce audio signals with high fidelity, which was previously considered impossible with analog disc players.

By the way, such a defthal disc player is
Normal disk playback can be performed only when the reference clock signal, which serves as a reference for the operation of the entire device, and the frame synchronization signal component of the digital data signal read from the disk are synchronized. In addition, controlling the reference clock signal and the frame synchronization signal component of the digital data signal to be synchronized means that the relative speed of the disk and the pick-up for bit detection is approximately constant. It is also used to control the rotation of a motor that rotates a disk on which dezotal data is recorded using a fixed method.

For this reason, in such a digital disc player, for example, due to dirt or scratches on the disc, random errors with a relatively short period of time, or burst errors with a relatively long period of time, may occur at the beginning of a frame of a digital data signal. If a frame synchronization signal (hereinafter simply referred to as a synchronization signal) with substantially coincident timing cannot be extracted, there may be an inconvenient situation in which the playback of the disc is interrupted or the total rotational pressure of the disc becomes uncontrollable. It is something that occurs.

Due to these circumstances, conventional digital disc players, for example, have a synchronization signal protection device that artificially interpolates the synchronization signal in a state where the synchronization signal cannot be detected, and when this state continues for a predetermined period of time or more, The entire operation of the device is synchronized to the detected synchronization signal again.

For example, as shown in FIG.
In a digital disc player of the type (disc disc), the disc 1 is attached to the rotating shaft of a motor 12 and driven to rotate, and the bit string is read out to an optical pickup 13. It's becoming a sea urchin.

This pickup 13 supplies its output signal to an RF signal detection circuit 14 that detects an RF signal readout signal.
Based on the predetermined signal obtained by the signal detection circuit 14, the servo circuit 15 loses focus and tracking control for the bit string on the disk 11, and the pick-up feed motor 16 feeds the bit string in the radial direction of the disk 1. It's about to start work.

The rL7'CRF signal obtained by the RF signal detection circuit 14 is
Synchronous clock regeneration circuit 17. The signal is supplied to a data separation circuit 18° and a synchronization pattern detection circuit 20 constituting a synchronization signal protection device 19.

The synchronization clock regeneration circuit 17 generates a regeneration clock signal whose cycle is approximately equal to the period during which one bit of digital data is transferred from the RF multiplied signal, and the regeneration clock signal is transmitted to the synchronization pattern detection circuit 20. The clock input terminal of the frame counter 21 and the control clock generation circuit 22 are provided.

The synchronization four-turn detection circuit 20 detects all of the predetermined frame synchronization turns (pit-turns) (hereinafter referred to as synchronization patterns) indicating the start of a frame in digital data that constitutes one frame of 588-bit serial data, for example. The 5- synchronization pattern detection signal is supplied to one input terminal of the AND circuit 23.

The frame counter 21 constitutes the synchronization signal protection device 19, and is configured to count, for example, a reproduced clock signal up to a maximum of 588, and each time the counted value reaches a predetermined value (for example, the value taken in the reset state). A circular frame synchronization signal (hereinafter referred to as synchronization signal) is provided to the control clock generation circuit 22 and the motor control circuit 24, and count value data of the reproduced clock signal is supplied to the protection window generation circuit 25.
It is designed to be supplied to The protection window generation circuit 25 generates a window pulse for a period corresponding to several bits (of the digital data signal) before and after the timing at which the synchronization signal is output based on the count value data of the frame counter 21, and generates a window pulse for the OR circuit 26. and one input terminal of the asynchronous frame number counter 27 (ek
2).

The output signal of the OR circuit 26 is the 6- It is designed to be supplied to the other input terminal.

The output signal of the AND circuit 23 is provided as a synchronization signal to the reset terminal (CI4) of the frame counter 21 and to the reset terminal (cl,) of the asynchronous frame number counter 27.

In other words, if the synchronization pattern detection signal is output within the wind pulse output period, each time the synchronization pattern detection signal or turn detection signal is output by the synchronization signal of the AND circuit 23,
The frame counter 21 and the asynchronous frame number counter 27 are reset. For this,
For example, if a burst error or the like occurs and the synchronization pattern detection signal is not output without detecting four turns of error synchronization, the synchronization signal is not output and the frame counter 21 receives the reproduced clock signal every time it counts, for example, 588 times. A pseudo synchronization signal is generated to compensate for the loss of the synchronization signal, and the asynchronous frame number counter counts wind pulses to detect a synchronization turn and count the possible number of frames. Then, the asynchronous frame number counter 27 determines that the number of frames in which the fourth turn of synchronization cannot be detected is a predetermined number (N).
A synchronization abnormality signal indicating that the number of protection frames is exceeded is supplied to the other input terminal of the AND circuit 23 via the OR circuit 26. Then, the next time a synchronous gloss turn is detected, a synchronization signal is output from the AND circuit 23 to reset the frame counter 21 and the asynchronous frame number counter 27. ? Thereafter, the frame counter 21 supplies a regular synchronization signal to the control clock generation circuit 22 and motor control circuit 24 each time a synchronization pattern detection signal is detected.

That is, the synchronization/'P turn detection circuit 20. Frame counter 21. AND circuit 23. Protective window generation circuit 2
5. OR circuit 26. A synchronization signal protection device 19 composed of an asynchronous frame number counter 27 compensates for missing synchronization patterns and prevents the digital disc player from malfunctioning.

Further, the control clock generation circuit 22 is adapted to provide a predetermined clock signal to the total data separation circuit 18 and the demodulation circuit 28. The data separation circuit 18 separates only the digital data signal from the RF signal and supplies it to the demodulation circuit 28. The demodulation circuit 28 demodulates the digital data signal and supplies it to a signal processing section that performs error correction processing and analog conversion of digital data via a terminal (OUTD) i. The analog signal obtained by this signal processing section is used, for example, to drive a speaker or the like via an amplifier.

On the other hand, the motor control circuit 24 is supplied with a reference clock signal from the reference clock generation circuit 27 of the digital disc player, and the 7-frame counter 2 of the synchronization signal protection device 19
comparing a synchronization signal provided by I with a reference clock signal;
The rotation speed of the motor 12 is controlled.

However, the optimal value for setting the number of protection frames (N) of the asynchronous frame number counter 27 differs depending on the reproduction state of the RF signal, and if it is set to (N)', it is likely to be adversely affected by random errors; If N) is increased, there is a problem in that it takes a long period of time for the synchronization signal protection circuit 19 to operate normally after a burst error occurs.

In other words, when the synchronization signal protection device 19 obtains an RF signal without any errors, it can obtain a correct synchronization/turn detection signal as shown in FIG. The output is shown in Fig. 2(b), and the symbols (P, , ) in Fig. 2(1) are added to the output of Fig. 2(b).
(P2) to (P4) of the synchronization signals.

If the synchronous gloss turn detection signals corresponding to (P6) and (P9) are lost due to frequent occurrence of random errors that occur during the period (Txt) from time (tl) to (t4), if N=2, the correct synchronous signal As shown in FIG. 2(c), only those corresponding to P3 in FIG. 2(,) are output. Then, the synchronization signal protection device 19 protects against noise n, for example.
If the 7-frame counter 21 is synchronized at a time (t3) different from the timing of the normal synchronization/four-turn detection signal at l+nl, a synchronization signal with an incorrect timing will be generated from time (t2). The output is interrupted until (t4), and when the synchronization pattern detection signal corresponding to Plo is obtained, the normal operation returns (see FIG. 2(c)).

On the other hand, when N=13, for example, the synchronization signal protection device 19 outputs a correct synchronization signal without departing from the normal timing, as shown in FIG. 2(d).

On the other hand, as shown in Figure 3 (2L), the period (TΣ2)
Due to the burst error that occurs in the synchronous E turn detection signal, for example 2. c many and 13, C,
In the case where only a small number of 9 are missing and the interval can be obtained immediately after the burst error ends, the synchronization signal protection device 19 operates normally as soon as the synchronization signal is detected (N=2). It returns to the state and outputs all the synchronization signals as shown in Figure 3(b), but when N=13, a synchronization pattern detection signal is obtained, but no synchronization signal is obtained even if N=13, as shown in Figure 3(C). As shown in the figure, it takes time to return to the normal operating state.

Further, a digital disc player is usually equipped with a search device that performs a search by specifying a desired platinum track number and index number recorded on the disc.

Although not shown, this search device drives the pickup feed motor 16 at high speed to drive the Virafatsuji 13f disk 11 in the forward and reverse radial directions ((, with the target track number and index number detected). It operates to stop the feed of the pickup 13 and completes the search operation.Even in such a search state, the synchronous pattern detection signal period is delayed, so N of the asynchronous frame number counter 27 is large. and synchronization signal protection device] It takes time for the operation of
Is there a problem with that? :,.

[Purpose of the invention]

This invention has been made in view of the above points, and it is possible to protect the frame synchronization signal in an optimal state by switching the number of protection frames in accordance with the frame synchronization pattern and the supply status of the signal including digital data. The overall objective is to provide an extremely good synchronization signal protection device.

[Summary of the invention]

The present invention provides a first method for outputting a frame synchronization signal in response to a frame synchronization pattern detection signal in a state in which the frame synchronization turn can be detected for an input signal containing a digital data-generated frame synchronization pattern. means, second means for pseudo-outputting all frame synchronization signals in a state in which the four turns of frame synchronization cannot be detected, and third means for counting the total number of frames of the input signal in which the frame synchronization pattern cannot be detected. When it is detected that the count value data of the third means and the third means are the predetermined number of protection frames, the next frame synchronization/? A synchronous signal protection device comprising a fourth means for synchronizing and driving the first means by detecting a turn, and a fifth means for detecting drop irregularity of the input signal; and sixth means for selectively switching the number of protection frames to be detected by the fourth means from 13 to 8 in binary values in response to the detection output of the fifth means. These are all characteristics.

[Embodiments of the invention]

An embodiment of the present invention will be described in detail below with reference to all the drawings.

FIG. 4 shows a synchronization signal protection device according to the present invention. However, in FIG. 4, the same parts as in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted.

That is, the synchronization signal protection device 31 according to the present invention includes the synchronization pattern detection circuit 20. Frame counter 21.
AND circuit 23. Protective window generation circuit 25. OR circuit 26. It has an asynchronous frame number counter 27, and the synchronization pattern detection circuit 20 supplies the synchronization pattern detection signal to the total synchronization detection circuit 32. The synchronization signal detection circuit 32 is also supplied with the wind nozzle from the protection window generation circuit 25, and detects a state in which the synchronization pattern detection signal is within the wind nozzle (synchronization state). All of these signals are supplied to the reset terminal (R) of the flip-flop 14-tube 33, which will be described later.

Further, a synchronization dropout detection circuit 34 provided in the synchronization signal protection device 31 receives an RF signal from the RF signal detection circuit.
For example, when a burst error or the like occurs, a dropout signal indicating a period during which a dropout occurs in which the RF multiplied signal is missing is provided to one input terminal of the OR circuit 35. It is something. The OR circuit 35 receives a search state signal indicating that the digital disc player is in the search operation state from a search device 36 that controls the digital disc player to perform the search operation at the other input terminal, and outputs the output signal to the flip-flop. It is designed to be supplied to the set terminal (S) of the pull-up 33.

The above Furi, Pflo and Zo33 are, for example, Noah circuit board 'X3
A set-up lycee consisting of 1,332 units.

It is a flip-flop in the form of a
The output signal is provided to a control input terminal of a protection frame number detection circuit 370, which will be described later.

The protection frame number detection circuit 37 has an input section supplied with the count value data of the asynchronous frame number counter 27. For example, when the control input terminal becomes high level, the protection frame number detection circuit 37 detects the number of protection frames N-13. When the number of protection frames to be detected becomes high level, N=2, and the count data of the asynchronous frame number counter 27 is equal to or greater than the number of protection frames N, its output terminal changes from low level to high level. The output terminal signal of the protection frame number detection circuit 37 is replaced with the output signal of the asynchronous frame number counter 21 as an abnormal signal and sent to the OR circuit 2.
It is designed to be served on the 6th.

That is, in the device configured as described above, the flip-flop 33 is always in the reset state by the detection output of the synchronization detection circuit 32 in the synchronization state in which the synchronization gloss turn detection signal falls within the wind pulse. The number (N)' of protection frames detected by the circuit 37 is set to 13, for example. Konniji synchronization signal protection device 31
Since the protection of the synchronization signal is performed using a relatively large number of protection frames (N), such as 13, the operation is optimal for preventing the adverse effects caused by random errors and the like.

On the other hand, if the dropout detection circuit 34 detects the RF multiplied signal drop or the signal is in the dropout search operation state, then the dropout detection circuit 34 is in the set state and the fraud protection frame is set. The number of protection frames (N) detected by the number detection circuit 37 is set to 2, for example. In addition, the synchronization signal protection device 31 protects the synchronization signal with a relatively small number of protection frames (N), such as 2, so that the synchronization signal protection device 31 protects the synchronization signal with a relatively small number of protection frames (N) of 2, so after a dropout occurs due to a burst error, etc., or after the search operation is completed, the The period required to return to the operating state (that is, the synchronous state) can be shortened.

In this way, by switching the number of protection frames to the optimum value according to the RF multiplication signal supply state, the synchronization signal protection device 31 can perform a good protection operation for the synchronization signal. Therefore, the reliability of the operation of the digital disc player is improved, which is extremely good.

It goes without saying that the present invention is not limited to the above embodiments, and that various modifications and applications can be made without departing from the spirit of the invention.

〔Effect of the invention〕

As detailed above, according to the present invention, frame synchronization A
? An extremely good synchronization signal protection device that can maintain frame synchronization signals in an optimal state by switching the number of protection frames according to the supply status of signals including turn and digital data. It is.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the configuration of a conventional synchronization signal protection device, and Figures 2 (a) to (d) are timing diagrams used to explain the operation of the device in Figure 1 in response to random errors. 3(a) to 3(C) are diagrams used to explain the operation of the device in FIG. 1 against burst errors, and FIG. 4 is an implementation of the synchronization signal protection device according to the present invention. FIG. 2 is a block diagram illustrating an example. DESCRIPTION OF SYMBOLS 11...Disk, 12...Motor, 13...Pickup, 14...RF signal detection circuit, 15...
SiryI? Circuit, 16...Pickup feed motor,
17... Synchronous clock regeneration circuit, 18... Data separation circuit, 19.31... Synchronous signal protection device, 20...
- Synchronous l' turn detection circuit, 21... Frame counter, 22... Control clock generation circuit, 23... AND circuit, 24... Motor control circuit, 25... Protection window generation circuit, 26. 35...OR circuit, 27...
・Asynchronous frame number counter, 28... Post-adjustment circuit, 2
9... Reference clock generation circuit, 32... Synchronization detection circuit, 33... Flip-flop, 331, 332...
・Nor circuit, 34... Dropout detection circuit, 36
. . . Search device, 37 . . . Protection frame number detection circuit. Applicant's agent Patent attorney Suzue - Hiko Zura 19-

Claims (1)

[Claims] a first means for outputting a frame synchronization signal in response to a frame synchronization non-turn detection signal in a state in which the frame synchronization pattern can be detected with respect to an input signal including digital data and a frame synchronization pattern; a second means for outputting a pseudo frame synchronization signal in a state in which a synchronization pattern cannot be detected; a third means for counting the number of frames of the input signal in which the frame synchronization gloss turn cannot be detected; a fourth means for detecting a next frame synchronization pattern and synchronizing and driving the first means in a state in which it is detected that the count value data of the means is a predetermined number of protection frames; A synchronization signal protection device comprising: fifth means for detecting mud or shear in the input signal; and a number of protection frames to be detected by the fourth means in response to a detection output of the first means. Large and small 2
A synchronization signal protection device comprising: sixth means for selectively switching to any one of the n values.