JPH0416868B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal transmission device applied to digital VTRs, data recorders, etc. that record and reproduce digital video signals.

When transmitting data, each of the plurality of samples is treated as one block, and a block synchronization signal and an error detection code for each block are added to each block. Furthermore, a set of a predetermined number of blocks is used as a unit, and numbering is performed to indicate the number of each block within the set. Taking a digital VTR as an example, a unit consisting of a predetermined number of blocks corresponds to data recorded and reproduced in one head scan. Conventionally, in order to locate the beginning of the reproduced data, a wind pulse is formed using a detection pulse or a servo reference signal obtained by magnetically detecting the rotational phase of the rotating head. , a method in which the block synchronization signal that falls within the window width is set as the beginning of the data, or a method in which the block synchronization signal at the beginning of the data (hereinafter referred to as the V block synchronization signal) is inserted separately from other block synchronization signals, and the window width is inserted during playback. A method is used in which the V block synchronization signal is extracted only from the reproduced signal without using the V block synchronization signal. The former has a simple circuit configuration, but is disadvantageous against jitter because the window width cannot be widened very much. The latter is
Although this is advantageous against jitter, it has the disadvantage of complicating the circuit configuration.

This invention basically uses a V block synchronization signal that can be distinguished from other block synchronization signals, but it is aimed at realizing a configuration that can easily and reliably extract the V block synchronization signal from the reproduced signal. This is the purpose.

Hereinafter, this invention will be described as a rotary head type digital device.
An example applied to a VTR will be described. This digital VTR is structured so that one field of video data is divided into multiple segments, and one segment's worth of data is recorded while the rotating head scans the magnetic tape once.
A V block synchronization signal for cueing is inserted into the first block of this segment. Figure 1 is used to explain this V block synchronization signal.
The first block of the blocks consisting of samples is used as a V block synchronization signal, and a block synchronization signal of M words (one word consists of two samples) is repeatedly inserted at the beginning of this first block.
+ as the remaining (N-2M) samples of the block
Sequence data that increases stepwise by 1 (0,
1, 2, ...N-2M-2, N-2M-1). The second and subsequent blocks are configured to consist of a one-word block synchronization signal and subsequent data.

By inserting such a pattern of V-block synchronization signals, it is possible to cue the data only from the reproduced data. That is, continuous numerical sequence data is found by constantly monitoring the reproduced data, that block is determined to be the first block, and the data is cued using the next block synchronization signal. Also, the reason why M words of the block synchronization signal are inserted before the sequence data is to distinguish it from other blocks, and also to extract the block synchronization signal on the playback side and use it to form the sample clock. This is to enable the PLL circuit for sample clock generation to start up quickly.

In addition to the above-mentioned sequence data, data sequences with a certain regularity may be used, such as those that increase by +2 or decrease by a predetermined number.

FIG. 2 shows the above-mentioned V block synchronization signal generation circuit, in which 1 and 5 are multiplexers, 2
3 is a sequence data generation circuit, 3 is a modulation circuit that performs block coding to convert 8 bits into 10 bits, 4 is a block synchronization generation circuit, 6 is a parallel-to-serial conversion circuit, and 7 is a timing controller. The timing controller 7 controls the multiplexers 1 and 5, the sequence data generation circuit 2, and the parallel-to-serial conversion circuit 6 as shown in the time chart of FIG. FIG. 3A shows a segment pulse of a segment period, FIG. 3B shows a timing pulse showing a data period of each segment, and FIG. 3C shows a timing pulse showing a V block synchronization signal period. Only the first part of one segment is shown enlarged in FIGS. 3D to 3H, and FIG. 3D is a block pulse of a block period. Further, the multiplexer 1 is controlled by the timing pulse shown in FIG. 3E and the timing pulse shown in FIG. 3F, and video data is inserted from the second block onwards. Further, sequence data is generated from the sequence data generation circuit 2 in synchronization with the timing pulse shown in FIG. 3H. Furthermore, the multiplexer 5 is controlled by the timing pulse shown in FIG.
A word block synchronization signal is inserted, and from the second block onwards, one word block synchronization signal is inserted at the beginning of each block.

Through the timing control described above, serial data to which a V block synchronization signal is added appears as the first block of each segment, as shown in FIG. recorded on tape. The reproduced signal is then supplied to an input terminal indicated by 8 in FIG. 4 via a reproduction amplifier.

A bit clock synchronized with the reproduced data is formed by the PLL circuit 9, and this bit clock is sent to the serial/parallel converter circuit 1 via the bit synchronization circuit 10.
3 and the block synchronization separation circuit 12.
The block synchronization signal separated by detecting the coincidence of bit patterns in the block synchronization separation circuit 12 is supplied to the synchronization correction circuit 15, where interpolation is performed when missing due to dropout, etc., and pseudo block synchronization signal is removed. A corrected block synchronization signal is obtained at its output. This block synchronization signal is supplied to a V block synchronization extraction circuit 14 and a sample clock generation circuit 16. The sample clock generated by the sample clock generation circuit 16 is supplied to the serial-parallel conversion circuit 13, the demodulation circuit 11, and the V-block synchronization extraction circuit 14, and is used for data processing in units of samples in these circuits. The reproduced data is synchronized with the sample clock by the serial/parallel converter circuit 13.
It is converted into 10-bit parallel data, and returned to 8 bits per sample by the demodulation circuit 11. The demodulated data is supplied to a TBC (time base correction circuit) and also to a V block synchronization extraction circuit 14.

Further, a detection signal PG corresponding to the rotational phase of the rotary head is supplied to the pulse generator 17 to form a wind pulse WND.
WND is supplied to the V block synchronization extraction circuit 14. Then, the V block synchronization signal is used to locate the beginning of one segment of reproduced data, and the blocks within one segment are numbered by counting the block synchronization signals obtained thereafter.

FIG. 5 shows a specific configuration of the V block synchronization extraction circuit 14 and the synchronization correction circuit 15.
FIG. 6 is a time chart of the operation of the V block synchronization extraction circuit 14.

First, the parallel data from the demodulation circuit 11 is supplied to the adder 18 and incremented by 1, and then supplied to the latch 19 where it is delayed by one sample by the clock. The output of the latch 19 and the reproduced data are compared by the comparator 20, and when the two match, a comparison output of "1" is generated.
That is, adder 18, latch 19, and comparator 20 determine whether adjacent data differ by one. This combination is V
This is the basic unit of the block synchronization extraction circuit 14. However, if there is data that differs by 1 even in two samples in the video data that is not sequence data, the output of the comparator 20 will be "1", so it is dangerous to judge that it is the first block based only on the output of the comparator 20. be. Therefore, in this embodiment, an adder 21, a latch 22, and a comparator 23 are provided to detect whether up to three consecutive samples form sequence data. In other words, the comparator 23 determines whether the values of data two samples apart differ by two.

The comparison output of comparators 20 and 23 is
Supplied to NAND gate 24, NAND gate 2
The output of 4 is used as the load signal of the counter 25.
Parallel data from the adder 18 is supplied to this counter 25 as a preset input, and
A sample clock is supplied. Therefore, the counter 25 only has 3 or more samples when the data is incrementing by 1 in the correct order.
The data is loaded, otherwise the counter 25 runs free by the clock. The parallel output of the counter 25 and the output of the digital switch 26 are compared by a comparator 27, and the comparator 27 generates an output that becomes "1" when the two match. As mentioned above, corresponding to the fact that the first block is N samples and the block synchronization signal of the first block is M words, the digital switch 26 selects (N-2M).
The value of is set. Therefore, the output of the comparator 27 becomes "1" at the beginning of the second block.

This counter 25 is a D flip-flop 41
When the output is "0", it is in the clear state. The output of the NAND gate 24 inverted by an inverter 42 is supplied as the clock input of the flip-flop 41, and its data input is set to "0", and the block synchronization signal inverted by the inverter 43 is supplied as its preset input. ing.

The comparison output of this comparator 27 is supplied to the AND gate 28 together with the wind pulse WND,
This output is latched by the D flip-flop 29. Wind pulse WND is used supplementarily to prevent spurious pulses from being picked up in video data. The output of D flip-flop 29 is
V via NOR gate 30 and inverter 31
It is extracted as a block synchronization signal. Further, a counter 32 is provided to count the block synchronization signals from the synchronization correction circuit 15, and when all of the first blocks disappear due to dropout or the like, the output of the counter 32 is used to interpolate the V block synchronization signal. being done.

The synchronization correction circuit 15 also includes two counters 33 and 34 that count sample clocks and generate an output when N sample clocks are counted, which is equal to the number of samples in one block. These counters 33 and 34 are connected to the NOR gate 3
5 and 36 by its own output. The block synchronization signal from the block synchronization separation circuit 12 loads a counter 33, and is also supplied to an AND gate 37 to which the output of the counter 33 is supplied, and checks whether the separated block synchronization signal is at a predetermined interval. be done.
The output of the AND gate 37, the V block synchronization signal obtained from the output of the flip-flop 29, and the output of the counter 34 are supplied to the NOR gate 36.
A counter 34 is loaded with its output. Furthermore,
The output of counter 34 is decoded by decoder 38, and a D-type flip-flop 39 is preset with the output. This flip-flop 39 is
The output of the NOR gate 36 is inverted by an inverter 40 and latched, and the output is taken out from the synchronization correction circuit 15 as a block synchronization signal.

The synchronization correction circuit 15 generates a block synchronization signal at regular intervals even when a dropout occurs in the reproduced data or a pseudo pulse is generated from the block synchronization separation circuit 12.
Configurations other than those shown in the figures may also be used.

Now, the operation of the above-mentioned V block synchronization extraction circuit 14 will be explained with reference to FIG. 6. FIG. 6A shows a sample clock synchronized with reproduced data. FIG. 6 shows a case where reproduction data of the first part of the first block and the second block is supplied, and from the block synchronization separation circuit 12,
As shown in FIG. 6B, M block synchronization signals are supplied to the first block and one block synchronization signal is supplied to the second and subsequent blocks. FIG. 6C shows parallel data from the demodulation circuit 11, and as mentioned above, after M block synchronization signals, sequence data that changes by +1 from 0 to (N-2M-1) is located. . The illustrated example shows a case where three samples C, D, and E (hexadecimal display) have become error data due to dropout, as indicated by diagonal lines.

The reproduced data shown in FIG. 6C is supplied to the adder 18, from which the output shown in FIG. 6D is obtained.
From latch 19, E is delayed by one clock.
The output shown in will appear. Since the reproduced data and the output of latch 19 are supplied to comparator 20, the output of comparator 20 is as shown in FIG. 6F.
From the beginning of the numerical sequence data output from latch 19 (N-
2M-1) and is "1" except for the 4-sample section including dropout. Further, the outputs of the adder 21 and the latch 22 are as shown in FIGS. 6G and 6H, respectively, and therefore the output of the comparator 23 is as shown in FIG. 6I.

The output of the above-mentioned comparator 20 (FIG. 6F) and the output of the comparator 23 (FIG. 6I) are NAND.
The signal is supplied to the gate 24. The counter 25 becomes "0" at the rising edge of the block synchronization signal (FIG. 6B) and is cleared by the output of the flip-flop 41. Next, the counter 25 is loaded at "0" from the output of the NAND gate 24. Along with being
It is no longer in the clear state, and becomes the clear state when the block synchronization signal of the second block is supplied.
Further, while the output of the NAND gate 24 is "0", the output of the adder 18 (D in FIG. 6) is output to the counter 2.
5, and when the output of the NAND gate 24 becomes "1" due to dropout, it is no longer loaded, and the counter 25 runs free during that time. Therefore, the operation of the counter 25 is as shown in FIG. 6J. And counter 25
When the output reaches (N-2M), the comparator 27 generates an output of "1" as shown in FIG. 6K. Since this is within the width of the wind pulse WND shown in FIG. 6L, the V block synchronization signal shown in FIG. 6M is formed. In this way, it is possible to extract the V block synchronization signal whose timing coincides with the block synchronization signal of the second block.

The above-mentioned invention differs from the conventional configuration in which only a window is applied, in that it is possible to reliably extract a V block synchronization signal even if there is considerable time variation, and it is also possible to extract sequence data as a V block synchronization signal. Because of this, there is no malfunction due to dropout, and the circuit structure can be simplified.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing the V block synchronization signal in one embodiment of the present invention, and FIGS. 2 and 3 are V block synchronization signals.
A time chart for explaining a block synchronization signal generation circuit and its operation, FIG. 4 is a block diagram showing the configuration of the playback side of an embodiment of the invention, and FIGS. 5 and 6 are an embodiment of the invention. 2 is a time chart for explaining the V block synchronization extraction circuit and its operation. 2...Sequence data generation circuit, 12...Block synchronization separation circuit, 14...V block synchronization extraction circuit, 18, 21...Adder, 20, 23, 27...
... Comparator, 25, 32, 33, 34... Counter.

Claims (1)

[Scope of Claims] 1. In a digital signal transmission device that divides a digital signal into blocks of a predetermined length and transmits a block synchronization signal by adding a block synchronization signal to each block, the number of blocks increases stepwise by a predetermined number. or means for generating a V-block synchronization signal consisting of decreasing number sequence data, which enables the reception side to identify the divisions of a certain number of blocks by detecting the number sequence data from the received data; , means for generating the block synchronization signal, and synchronization adding means for adding the block synchronization signal to each of the blocks, and adding the V block synchronization signal to the first block of the predetermined number of blocks. A digital signal transmission device characterized by: