JPS6113476A - Synchronous control system of cassette type magnetic tape device - Google Patents

Abstract

PURPOSE:To facilitate the processing of s cynchronizing pattern interposed between data blocks and to perform the demodulation processing of CMT at the program level of a microcomputer by using a special pattern which does not appear in normal data as the 1st pattern of a record, and using another special pattern which appears in normal data as synchronizing patterns in the middle. CONSTITUTION:The 1st synchronizing pattern FSY of a record following a preamble PREA consists of the special pattern which does not appear in normal data and resynchronizing patterns SYNC among data blocks 10, 11... in the middle of the record consist of the specific bit pattern (''F9''=''11111001'') which appears in normal data. When records being to be read, a one-chip microcomputer 14 detects the 1st FSYN of the record after detecting the PREA. In this case, the microcomputer 14 has a margin of processing because data blocks are not read yet, and the processing ability is assigned to the detection of FSYN, and data blocks of every frame are read correctly in a readout routine.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a synchronous control method for a cassette-type magnetic tape device for recording and reproducing digital information.

゛ [Technical shape of the invention and its problems] In a cassette-type magnetic tape device, when recording digital data on a recording medium, that is, a cassette-shaped magnetic tape (hereinafter referred to as CMT), the record is usually Put the sync pattern at the beginning,
This synchronization pattern provides synchronization during demodulation.

Conventionally, this type of synchronization pattern is a special pattern that never appears as a result of demodulating data. Therefore, when processing the synchronization pattern, a demodulation process different from data demodulation is performed, and the result is compared with the set synchronization pattern.

Here, conventional synchronization detection means will be explained with reference to the drawings. Figure 1 shows the record format of a CMT that uses an erasure error correction method in its simplest form. A synchronous pattern, ie, a 5YNC pattern, is provided in the front. As mentioned above, this 5YNC pattern is the normal l l=
, 'l゛Q゛T data is recorded in a special pattern that is completely different from that of the data. This recording waveform example is shown in Fig. 2(a) to (
Shown in C). Here, taking the FM method (1f2f method) as an example, the recording waveform of data #1'' is shown in Figure 2 (a,).
In addition, the recording waveform of data "0" is shown in FIG. 5(b), and the special signal recording waveform is shown in FIG. 12(c).

Normal data (1°l,
There are several methods for reading (or demodulating) IIQll), but to give an example, synchronize the waveform and sampling clock at point A shown in Figure 3, and synchronize the waveform and sampling clock at point B (or 0
point), depending on whether the waveform is positive or negative, #1lZ
l"0'° is identified.

For data identification of this level (normal data), point B (
Therefore, the hardware only needs to perform zero-cross detection, and the rest of the processing can be left to the firmware processing of the one-chip microcomputer. In this case, there is one data buffer inside the one-chip microcomputer.
It is sufficient to have a byte register, fill the register with positive/negative data one bit at a time at the timing corresponding to point B above, and when the register is full, send that one byte to the CPLI. , all remaining registers are available for other purposes.

Similar to the data identification means described above, when attempting to correctly identify a special pattern that does not appear in normal data as shown in FIG. 2(C) using a one-chip microcomputer, As shown in a), this is achieved by sampling the waveform at each timing of the O mark and comparing the data pattern according to the sign of the waveform at that time with the set pattern. To contrast the sampling timing of this special pattern, we will compare the sampling timing of the normal data pattern (
11i H2 “O”) sampling timing
It is shown in figure (b).

In this way, in the case of the special pattern shown in FIG. 4(a), as is clear from the comparison with 1i4(b),
It is necessary to perform sampling at four times the speed of the normal pattern, which requires an extra processing load on the 1-chip microcomputer and increases the number of registers used.

In the format shown in Figure 1 above, at the stage of processing the synchronization pattern (SYNC) at the beginning of the record, the 1-chip microcomputer has not yet read the data block and can concentrate only on processing the synchronization pattern. There is no problem even if the sampling frequency is quadrupled as described above. Therefore, for the synchronization pattern processing at the beginning of a record, the above-mentioned special pattern, that is, the 5YNC pattern identification processing is possible. However, the 5YNC pattern in the middle of the record (data blocks Ij, I
In the case of 8YNC between k), the 1-chip microcomputer stores the remaining data in buffer 1 (N and
CRC data) must be sent to CPLJ at the same time. Furthermore, tasks such as reading data and sending it to the CPU must be performed simultaneously with the detection of the synchronization pattern. Therefore, in the past, dedicated hardware was required to identify the synchronization bars and turns, and the li! This method has the disadvantage that it becomes complicated and expensive.

[Object of the invention] - The present invention has been made in view of the above-mentioned circumstances, and it simplifies the processing of synchronization patterns interposed between data blocks, and
It is an object of the present invention to provide a synchronous control method for a cassette-type magnetic tape device that enables MT demodulation processing to be executed at the program level of a microcomputer.

[Summary of the invention] The present invention focuses on the difference between the synchronization pattern at the beginning of a record and the synchronization pattern in the middle of the record, and the first synchronization pattern of the record is provided for the original synchronization. On the other hand, the synchronization pattern in the middle of the record is
Since this is to resynchronize the read signals that should have been synchronized, a specific pattern that can appear in normal data is used as the synchronization pattern in the middle of this record. . That is, in the present invention, a special pattern that does not appear in normal data is used only for the first pattern of a record, and a synchronization pattern in the middle of the record (hereinafter referred to as a resynchronization pattern) is used.
are each a specific pattern that can appear in normal data (
Here “' F 9 ” = “11111001”
) is used. This makes it possible to simplify the processing of synchronization patterns interposed between data blocks, and to perform GMT demodulation processing at the microcomputer program level, thereby greatly simplifying the device configuration.

[Embodiment of R-light] Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 5 to 9. FIG. 5 is a ten-dimensional diagram showing the hardware configuration in one embodiment of the present invention.

In the figure, 11 is a read head, 12 is an amplifier, 13 is a zero-cross detector, and 14 is a 1-chip microcomputer (8048). The output of the zero-cross detector 13 is applied to one of the test input terminals (TO) of the one-chip microcomputer 14. The data demodulated and assembled into bytes by the one-chip microcomputer 14 is sent to a CPLI (not shown) via a passport (Bus).

FIG. 6 shows a record format in one embodiment of the present invention. In the figure, FSYN is the first synchronization pattern of the record, and 5YNC is the so-called resynchronization pattern described above. Here, only FSYN is a special pattern that does not exist in normal data as in the past, and 5YNC is a specific pattern that can appear in normal data.
”.

FIG. 7 is a diagram showing a partial processing flow of the 1-chip microcomputer 14 when reading records of the format 1- shown in FIG. 6, and FIG. 8 is a diagram showing the resynchronization routine in FIG. FIG. 3 is a diagram showing a processing flow of a resynchronization processing part. FIG. 9 is a diagram for explaining the pattern comparison operation of the resynchronization process shown in FIG. 8.

Here, the operation of one embodiment will be described with reference to FIGS. 5 to 9. Here, record unit data consisting of multiple frames is recorded on CN4T in the format shown in Figure 6, and FSYN, which is the first synchronization pattern of the record following the preamble PREA, is:
As mentioned above, although it is a special pattern that does not appear in normal data, the synchronization pattern in the middle of a record, that is, the resynchronization pattern 5YNC provided between data blocks 70, 71... A specific bit pattern that can appear in normal data (i.e. can be treated like normal data) ("F9"="'11
111001”).

In FIG. 7, when the record reading process is started, the 1-deep microcomputer 14 reads the preamble (
After the detection of FSYN, which is the first synchronization pattern of the record, processing is performed to detect FSYN which is the first synchronization pattern of the record. At this time, the 1-chip microcomputer 14 has processing time because it has not yet read the data blocks in the record, and therefore all the processing TI! Since the capacity can be applied to detecting FSYN, detection processing by high-speed sampling of FSYN consisting of a special pattern as shown in FIG. 4(a) can be sufficiently performed.

° Once synchronization is established by this FSYN synchronization detection, from then on, resynchronization is performed by 5YNC, and data block IO for each frame is performed in the data reading routine.
, r1, . . . are correctly read. In this data read processing routine, in addition to data demodulation, byte assembly, buffering, block length/record arrangement management, etc. are performed in parallel. FIG. 8 shows the resynchronization processing portion of the resynchronization routine shown in FIG. 7, and here, work in the loop that is not related to resynchronization is not shown. In this resynchronization process, the "fill byte buffer" subroutine is used in common with the data reading routine.
The contents of byte banff 1, which contains 8-bit data including the last bit read, are shifted to the left by 1 bit, and the bit read this time is placed at the right end. FIG. 9 shows how the 5YNC pattern is compared and detected by the loop shown in FIG. As is clear from FIG. 9, here, as 5YNC, a specific pattern that can appear in normal data ("F 9 " = " 1
1111 o o 1”)
, 5YNC patterns are compared so that they always include a part of the position where the 5YNC pattern should be, so no matter what value the data part indicated by XXX in Figure 9 takes, A match (synchronous detection) will not occur at the wrong position. Furthermore, even if there is a 1-bit error in the read 5YNC pattern, a match will not occur at an erroneous position.

In this way, the synchronization process between data blocks, that is, the resynchronization process, is performed in the same way as normal data reading process, so the above process can be easily realized by the programmer of the one-chip microcomputer 14, and therefore,
As for the hardware, demodulation processing for 0 to 1 devices can be performed with a very simple configuration that only includes a zero-cross detector 13.

In the above-mentioned embodiment, FSYN is a special pattern that can never be seen in normal data, but like the above-mentioned resynchronization pattern, it can appear in normal data, for example, “FF” (a I I”
It is also possible to replace it with a pattern such as 1″).

[Effects of the Invention] As described in detail above, according to the synchronization control method of the cassette 1-type magnetic tape device of the present invention, specific patterns that may appear in normal data are set in synchronization patterns in the middle of records. By using this pattern detection to resynchronize data reading, processing of synchronization patterns interposed between data blocks can be simplified, and CM
Since the demodulation process of T can be executed at the microcomputer program level, the device configuration can be greatly simplified.

[Brief explanation of drawings]

Figures 1 to 4 are for explaining conventional synchronization control means, respectively, and Figure 1 shows record formats 1 to 4.
, and FIGS. 2 to 4 are diagrams showing recording waveforms, respectively. 5 to 9 are for explaining one embodiment of the present invention, respectively. FIG. 5 is a block diagram showing the hardware configuration in the above embodiment, and FIG. 6 is a block diagram showing the hardware configuration in the above embodiment. Figures 7 and 8 are diagrams showing the processing flow of the main parts in the above embodiment, respectively, and Figure 9 explains the resynchronization pattern comparison operation in the above embodiment. This is a diagram for 13... Zero cross detector, 14... 1-chip microcomputer.

Claims (1)

[Claims] In a cassette magnetic tape device that records and reproduces digital data in a recording format in which each field in a record has a resynchronization pattern, the resynchronization pattern of each field is modulated using the same modulation method as the recorded data in each field. A cassette type magnetic recording device records data using a specific bit pattern, and upon reproduction, the resynchronization pattern is demodulated by the same demodulation means as the data in the field, and synchronization is detected by comparison with a set synchronization pattern. A synchronous control method for tape devices.