JPS5665321A - Processor for digital signal - Google Patents

Processor for digital signal

Info

Publication number
JPS5665321A
JPS5665321A JP14167379A JP14167379A JPS5665321A JP S5665321 A JPS5665321 A JP S5665321A JP 14167379 A JP14167379 A JP 14167379A JP 14167379 A JP14167379 A JP 14167379A JP S5665321 A JPS5665321 A JP S5665321A
Authority
JP
Japan
Prior art keywords
signal
subblock
block
main block
extracted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14167379A
Other languages
Japanese (ja)
Inventor
Ryusuke Moriya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP14167379A priority Critical patent/JPS5665321A/en
Publication of JPS5665321A publication Critical patent/JPS5665321A/en
Pending legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE: To number subblocks by exercising control so that a reference signal for generating a window pulse for extracting the 1st block-synchronizing signal has a constant phase relation to a reproduced signal.
CONSTITUTION: Every time some samples are extracted from an input digital signal, a subblock is generated and block-synchronizing signal is added to every subblock; and a certain number of subblocks constitutes a main block and prescribed signal processing is performed for every subblock and main block. Then, the 1st subblock-synchronizing signal of the main block is extracted 93 and servo loop 80 exercises control so that this extracted signal will have a constant phase relation to reference signal REV whose repetitive period is equal to that of the main block in order to generate a window pulse.
COPYRIGHT: (C)1981,JPO&Japio
JP14167379A 1979-10-31 1979-10-31 Processor for digital signal Pending JPS5665321A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14167379A JPS5665321A (en) 1979-10-31 1979-10-31 Processor for digital signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14167379A JPS5665321A (en) 1979-10-31 1979-10-31 Processor for digital signal

Publications (1)

Publication Number Publication Date
JPS5665321A true JPS5665321A (en) 1981-06-03

Family

ID=15297527

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14167379A Pending JPS5665321A (en) 1979-10-31 1979-10-31 Processor for digital signal

Country Status (1)

Country Link
JP (1) JPS5665321A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS603248A (en) * 1983-06-20 1985-01-09 Nec Home Electronics Ltd Bi-phase mark modulation circuit of pcm recording and reproducing device
JPS6113476A (en) * 1984-06-28 1986-01-21 Nippon Telegr & Teleph Corp <Ntt> Synchronous control system of cassette type magnetic tape device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS603248A (en) * 1983-06-20 1985-01-09 Nec Home Electronics Ltd Bi-phase mark modulation circuit of pcm recording and reproducing device
JPS6113476A (en) * 1984-06-28 1986-01-21 Nippon Telegr & Teleph Corp <Ntt> Synchronous control system of cassette type magnetic tape device
JPH0544749B2 (en) * 1984-06-28 1993-07-07 Nippon Telegraph & Telephone

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