JPH0834038B2 - Information recording / reproducing device - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to an information recording / reproducing apparatus for reading and processing an ID information signal from a recording medium recorded in a preset format, and more particularly to a PCM signal conversion. The digital signal is reproduced from the magnetic tape on which various subcode data such as the program number is recorded together with the audio signal,
The present invention relates to a so-called DAT information recording / reproducing device.

[Technical background of the invention and its problems]

A helical scan type rotary head is used as the DAT to scan and record diagonal tracks on the tape.
There is a device called R-DAT which is adapted to perform reproduction, and one track thereof has a format as shown in FIG.

That is, one track is mainly PCM of audio signals
PCM area including data and ATF for automatic tracking control
It is composed of two subcode areas (SUB1, SUB2) provided before and after the PCM area with the area in between, and the PCM area and the subcode area are both composed of a plurality of blocks.

Further, in the PCM area, in addition to the audio signal, a PCM-ID indicating the sampling frequency and the propriety of copying, and an optional code indicating time information are recorded, and each sub code area of SUB1 and SUB2 is similar to the PCM area. In addition to subcode data such as time information, a start that indicates the beginning of the program
A control code including an ID and a subcode ID including a PNO-ID (program number) for identifying a program are recorded. The PCM-ID of the PCM area and the subcode ID of the subcode area have the same data recorded over a plurality of tracks.

At the time of reproducing the data as described above, the coincidence detection is performed on the PCM-ID of the data read from the magnetic tape to improve the reliability of the reproduced data.

However, since only the parity check is performed on the subcode ID, there is a problem that the reliability of this subcode ID is low.

[Object of the Invention]

The present invention focuses on the fact that the match detection for the PCM-ID is conventionally performed, and in addition to the match detection for the PCM-ID, the match detection is also performed for the subcode ID with a simple configuration to thereby ensure the reliability of the reproduction data. The purpose is to improve the sex.

[Outline of Invention]

The information recording / reproducing apparatus of the present invention made to achieve the above object is based on a preset format.
1. An information recording / reproducing apparatus for reading out these ID information signals from a recording medium in which different ID information signals are recorded in duplicate in the first and second recording areas, and processing the read information information. Coincidence detecting means for performing coincidence detection between the information signals recorded in duplicate for each of the read first and second ID information signals based on the control signal output corresponding to And a coincidence detection control means for outputting control signals corresponding to the first and second recording areas based on the format of the recording medium to the coincidence detection means.

Particularly in the DAT, a control signal is output corresponding to each of the PCM area, which is the first recording area, and the subcode area, which is the second recording area, and is recorded in the PCM area and the subcode area in an overlapping manner. Match detection is performed for the existing PCM-ID and subcode ID.

〔Example〕

FIG. 8 is a diagram showing the block format of the PCM region in the R-DAT according to the present invention, and FIG. 9 is a diagram showing the block format of the subcode region in the R-DAT in the same manner.

As shown in FIG. 8, in the PCM area, the PC is added to the 8-bit (W ₁ ) following the 8-bit block synchronization signal (SYNC).
A block address is set in each of the M-ID and the next 8 bits (W ₂ ), and 8 bits of parity (P) of W ₁ and W ₂ are further added. PCM data and parity are set in the subsequent 256-bit (32 symbol) data part. Also, the most significant bit (MSB) of W ₂ is set to “0”, which indicates that this block is a PCM area.

As shown in Fig. 9, in the subcode area, SY
NC and parity (P) are set in the same way as the block format of the PCM area above, but the subcode ID is set to a part (3 bits) of W ₁ and W _{2 and} the block address is the lower order of W ₂ . It is set to 4 bits, and subcode data and its parity are set in the 256-bit data part. In this subcode area, the MSB of W ₂ is set to “1”, which indicates that it is a subcode area.

The PCM area is composed of 128 blocks, and each of the first and second subcode areas (SUB1, SUB2) is composed of 8 blocks.

FIG. 6 is a diagram for explaining the PCM-ID and block address of the PCM area, and FIG. 7 is a diagram for explaining the subcode ID and block address of the subcode area.

As shown in Fig. 6, the PCM-ID is a control signal of 2 bits for each of ID-1 to ID-8 that specifies sampling frequency, necessity of emphasis or prohibition of copying, and a 4-bit frame address. Consists of 2 control signals (ID-1, ID-2, etc.) and a frame address of 8
Bits are configured and repeated every 8 blocks and recorded in blocks of even addresses. Incidentally, various optional codes such as program time and absolute time are recorded in the odd number blocks. Therefore, the same ID is recorded up to 16 times in the PCM area of one track. The same address value is set as the frame address over two tracks (one frame).

As shown in Fig. 7, the subcode ID is a 4-bit control ID including the start ID (1 bit) that indicates the beginning of the program, a 4-bit data ID that specifies audio specifications, and the program time. , A 3-bit format ID that indicates the number of pieces of pack data that is recorded as sub-code data and that indicates absolute time, and a 3-bit PNO-1 that represents a program number with a total of 11 bits and a 4-bit PNO- each. It is composed of 2 and PNO-3 data.

Then, control to W ₁ of the even address block
ID and data ID, format ID is recorded in 3 bits of W _{2 in} the same block, PNO-2 in W ₁ of odd address block
, PNO-3, and PNO-1 are recorded in the 3 bits of W ₂ of the block. Therefore, one track has SUB1, SUB
The same ID is recorded 4 times, 2 times in total, 8 times in total.

The data ID and format ID of the subcode ID
Is related to pack data, so it is transferred to a storage device together with PCM data or subcode data, and coincidence detection is performed for other IDs.

FIG. 2 is a block diagram showing an embodiment of the present invention, R-
The reproduction system of DAT is shown.

In the figure, 1 is a rotary drum equipped with a recording / reproducing head, 2 is a reproducing amplifier, 3 is an equalizer, and 4 is a PLL circuit. Then, the signal read from the magnetic tape by the rotating drum 1 passes through the reproduction amplifier 2 and the equalizer 3.
It is input to the PLL circuit 4, the clock is extracted in the PLL circuit 4, and digital data is obtained from the reproduced signal.

5 is an 8-10 demodulation unit that demodulates 8-10 modulated data, 6 is a match detection unit that detects a match between PCM-ID and subcode ID, and 7 is data that is output from the 8-10 demodulation unit 5. , A match detection control unit for controlling the match detection unit 6 by outputting a latch signal, a reset signal, etc. based on a clock or the like.

The data output from the PLL circuit 4 is 8-10 demodulator 5
The data word including each ID is demodulated by the parity check and the ID data having no error is output to the match detection unit 6 and the match detection control unit 7, and the match detection control is performed. Part 7 is 8-
10 A latch signal, a reset signal, etc. are output to the coincidence detection unit 6 based on the data, clock, etc. output from the demodulation unit 5.

Then, as will be described later in detail, the match detection unit 6 performs match detection on both the PCM-ID and the subcode ID based on the signal output from the match detection control unit 7, and the ID at which the match is detected is determined to be predetermined. Hold in the output register of.

In this way, a match is detected, and the PCM-ID and subcode-ID held in the match detection unit 6 are read by the microcomputer 9 via the microcomputer interface 8, and the microcomputer 9 responds to each ID. Each process such as program number identification is performed.

In addition, the PCM data output from the above 8-10 demodulation unit 5,
Subcode data is temporarily stored in RAM10,
The error correction decoding unit 11 performs predetermined processing on each data such as deinterleave, C1 correction, C2 correction, and stores the data again in the RAM 10. Then, the PCM data stored in the RAM 10 is interpolated by the interpolation unit 12 and converted into an audio signal by the D / A conversion unit 13.

The subcode data that has been C1 corrected by the error correction decoding unit 11 and stored in the RAM 10 is detected by the subcode detection unit 14 when read by the microcomputer 9, and is output to the microcomputer 9 via the microcomputer interface 8. It Then, based on this subcode data, for example, processing such as time display is performed under the control of the microcomputer 9.

FIG. 1 is a circuit diagram of the coincidence detection section 6, and the numbers attached to the wiring parts in the figure show the number of bits.

In the figure, 61 ₁ , 61 ₂ , 62 ₁ and 62 ₂ are 4-bit D flip-flops (D-FF), 61 ₃ and 62 ₃ are 8-bit D flip-flops, and 61 ₄ and 62 ₄ are 2-bit D flip-flops. 8-10 is a flip-flop, and the PCM-ID and subcode ID output from the 8-10 demodulator 5 are the D flip-flops 61 ₁ , 61 ₂ ,
..., it is sequentially input latch 62 _4.

D flip-flops 61 ₁ and 62 ₁ , D flip-flop 61
₂ and 62 ₂ , D flip-flops 61 ₃ and 62 ₃ and D flip-flops 61 ₄ and 62 ₄ form a pair by connecting an output terminal and an input terminal through an inverter, respectively, and the pair of D flip-flops of each pair. Latch signal for each clock terminal
LTH1 to LTH4 are applied, and the contents of the D flip-flop in the preceding stage are inverted and stored in the subsequent stage, forming four pairs of two-stage shift registers.

Each D flip-flops 61 _1, 61 _2, ... 62 _3, the 62 _fourth reset terminal the same reset signal RST1 is input.

Further, the output terminal of the output terminal and the rear stage of the D flip-flop 62 of the preceding D flip-flop 61 are connected to respective input terminals of the XOR circuit 63 ₁ to 63 ₄ in each pair, and each XOR circuit 63 ₁ to 63 ₄ The output terminals of are connected to the input terminals of the AND circuits 64 ₁ to 64 ₄ , respectively.

Therefore, if the data input first and the data input next in each pair of D flip-flops match, all the outputs of the XOR circuit 63 become active and the outputs of the AND circuit 64 become active. Become. As a result, data matching is detected.

The 1-bit output terminal of each of the AND circuits 64 ₁ to 64 ₄ is set to 4 bits and connected to the input terminals of the AND circuits 65a and 65b, respectively, and the other input terminals of the AND circuit 65b are "H" in the subcode area. The SUB / PCM switching signal and the latch signal LTH5 that become "L" level in the level and PCM areas are input, and the inverted signal of the above SUB / PCM switching signal and the latch signal LTH5 are input to the other input terminal of the AND circuit 65a. Is entered.

66a is an 18-bit D flip-flop to which the 18-bit output terminals of 4 bits, 4 bits, 8 bits, and 2 bits of the D flip-flops 62 _{1 to} 62 _{4 in} the latter stage are respectively connected, and 66b is a D flip-flop 62. 4 from _{1 to} 62 ₃
It is a 16-bit D flip-flop to which output terminals of 16 bits in total of 4 bits, 8 bits and 8 bits are connected. The output of the AND circuit 65a is connected to the clock terminal of the D flip-flop 66a, and the output of the AND circuit 65b. The output is connected to the clock terminal of the D flip-flop 66b. In addition,
The reset signal RST2 is input to the reset terminals of the D flip-flops 66a and 66b.

67a and 67b are 18-bit and 16-bit parallel input / serial output shift registers, respectively. The data output terminal of the D flip-flop 66a is the input terminal of the shift register 67a, and the data output terminal of the D flip-flop 66b is The shift register 67b is connected to each input terminal.

The shift registers 67a and 67b latch parallel data when a clock signal is input while the applied parallel / serial select signal PS is at “H” level, and the parallel / serial select signal PS is at “L” level. When a clock signal is input, the latched data is output as serial data.

A latch signal LTH6 is applied to each clock input terminal of the shift registers 67a and 67b via an OR circuit, and clock signals CK1 and CK2 output from the microcomputer are applied.

Latch signals LTH1 to LTH6, reset signals RST1, RST
2, SUB / PCM switching signal, parallel / serial select signal P
S is generated by the coincidence detection control unit 7 based on the data, clock, etc. output from the 8-10 demodulation unit 5.

That is, since the data format as described above is set in advance, for example, the distinction between the PCM area and the subcode area is identified by the MSB of W ₂ to generate the SUB / PCM switching signal, or the block is generated as described later. Latch signals LTH1, LTH2, ..., Which are separately output for each, are generated by identifying each block by the block address.

FIG. 5 is a timing chart for explaining the operation repeated for each track. As shown in the figure, RST1 is output before the subcode area and the PCM area, and the D flip-flops 61 ₁ , 61 ₂ , ..., 61 _4, 62 ₄ match detection of subcode ID, or PCM-ID in each area is reset is performed as follows.

(Subcode ID coincidence detection) FIG. 3 is a timing chart for explaining subcode ID coincidence detection. When the first block data (even address) in the subcode area is input and LTH2 is output, the subcode is detected. The control ID (4 bits) of the code ID W ₁ is D
It is latched into flip-flop 61 _2. The second block (odd address) Lth3 is output PN of W ₁
O-2 and PNO-3 (4 bits each) are D flip-flops 61
₃ is latched, LTH1 the same block is outputted in W ₂ PNO
-1 is latched in the D flip-flop 61 ₁ .

When the above operation is similarly performed for the third and fourth blocks, the control ID of the third block, PNO-2, PNO-3 and PNO-1 of the fourth block are D flip-flops 61 ₂ , 61. ₃ and 61, respectively while being latched to _1, D flip-flop 61 _2, 61 ₃ and 61 control ID of the first block which has been latched in _1, the second block PNO-2, PNO-3 and PNO- 1 is inverted by the inverter, and D flip-flops 62 ₂ , 62 ₃ and 6 at the subsequent stage are inverted.
Latched to 2 ₁ respectively.

Also, at this time, each D flip-flop latched
The ID is output to the XOR circuits 63 ₂ , 63 ₃ and 63 ₁ , and the matching of each ID is detected.

And the above control ID, PNO-1, PNO-2 and PNO-
If all 3 match, as shown in Fig. 5, SUB / P
When the AND circuit 65b becomes conductive because the CM switching signal is at "H" level and LTH5 (Fig. 3) is output, the outputs of the D flip-flops 62 _{1 to} 62 ₃ , that is, the coincidence is detected. The control IDs PNO-1, PNO-2 and PNO-3 are latched by the D flip-flop 66b.

In this way, the subcode IDs that sequentially match in the areas of SUB1 and SUB2 are latched in the D flip-flop 66b.

(PCM-ID Match Detection) FIG. 4 is a timing chart for explaining PCM-ID match detection. When the first block data (even address) in the PCM area is input and LTH1 is output, W ₁ ID-1, I
D-2 (4 bits in total) is latched in the D flip-flop 61 ₁ , and LTH2 is output in the same way in the third block, and the ID of W ₁ is output.
-3, ID-4 (4 bits in total) are latched in the D flip-flop 61 ₂ .

Next, in the fifth block, LTH3 is output and W ₁ 's ID-5, I
D-6 and the frame address (8 bits in total) are latched in the D flip-flop 61 ₃ , LTH4 is output in the 7th block, and ID-7 (2 bits) of W ₁ is latched in the D flip-flop 61 ₄ . To be done.

When the same operation is sequentially performed for a block of odd-numbered (even address), the sub-code XOR in the same manner as described for the detection of ID circuit 63 ₁ to 63 ₄ and the AND circuit
Match detection is performed on 64 ₁ to 64 ₄ .

Then, as shown in FIG. 5, all the IDs (ID-1 to ID-1 to
AND circuit when ID7 and frame address) match
65a becomes conductive, and the PCM-ID whose match is detected by the latch signal LTH5 output every 8 blocks thereafter in the 7th block is latched in the D flip-flop 66a.

When the processing for the data of one track is completed as described above, the parallel / serial select signal PS is set to the "H" level and the latch signal LTH6 is output as shown in FIG. And the subcode ID and P latched in the D flip-flops 66a and 66b.
The CM-ID is latched and stored in the shift registers 67a and 67b, respectively.

The subcode ID and PCM-ID stored in the shift registers 67a and 67b are serially read by the clock signals CK1 and CK2 output from the microcomputer 9, and the microcomputer 9 performs each process.

〔The invention's effect〕

According to the present invention, particularly in the DAT, the PCM-ID and the subcode ID are respectively associated with the PCM area and the subcode area.
For each of the above, since the coincidence detection of the information signals recorded redundantly is performed, it is possible to perform the process based on the highly reliable ID code.

Further, in the embodiment, the coincidence detection for the PCM-ID and the subcode ID is performed in a time division manner by using the same circuit together, so that an ID code having a simple configuration and high reliability can be obtained. You can

[Brief description of drawings]

FIG. 1 is a circuit diagram of a match detection unit in an embodiment of the present invention, FIG. 2 is a block diagram of a reproduction system in the embodiment, FIG. 3 is a timing chart for explaining subcode ID match detection in the embodiment, FIG. 4 is a timing chart for explaining the PCM-ID coincidence detection in the embodiment, FIG. 5 is a timing chart for explaining the operation for each track in the embodiment, and FIG. 6 is a PCM-ID and block address in the PCM area. FIG. 7 is a diagram for explaining subcode IDs and block addresses in the subcode area, FIG. 8 is a diagram showing a block format in the PCM area, and FIG. 9 is a diagram showing a block format in the subcode area. FIG. 10 is a diagram showing a track format in R-DAT. 6 ... Match detection unit, 61, 62, 66 ... D flip-flop,
67 …… Shift register.

Claims (1)

[Claims] 1. A first ID information signal is redundantly recorded in a first recording area and a second ID information signal is redundantly recorded in a second recording area based on a preset format. The first and / or second ID from the recorded recording medium
In an information recording / reproducing apparatus for reading out an information signal for processing, each of the read first and second ID information signals is read based on a control signal output corresponding to the first and second recording areas. With respect to the above, the coincidence detecting means for detecting coincidence between the information signals recorded in duplicate, and the control signals corresponding to the first and second recording areas based on the format of the recording medium are output to the coincidence detecting means. An information recording / reproducing apparatus, comprising: