JP2972090B2 - Digital tape recorder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION The present invention relates to a digital audio
Digital information signals such as e-signals and digital video signals
The present invention relates to a digital tape recorder that reproduces a. [0002] 2. Description of the Related Art Digital audio signals (PCM signals)
Recording / reproducing by a pair of rotating heads
With one rotating head
The amount of PCM signal to be recorded / reproduced is arranged in a matrix,
For each PCM signal vertically aligned in this matrix arrangement
The error correction code C1 is coded and the matrix arrangement is performed.
For each PCM signal aligned in the horizontal direction, the error correction code C2
What performs encoding is used. This error correction mark
Signal encoded PCM signal, error correction code C1 and
Check symbols C2 and C2 are aligned vertically
Is recorded / reproduced every time. Error correction of the playback signal
The error correction code C1 is decoded (C1 decoding).
The error correction code C2 is decoded (C2 decoding). When an uncorrectable error occurs,
To facilitate the interpolation of error symbols, the PCM signal
Adjacent even-numbered data and its odd-numbered data
Recording is performed by dividing into two tracks.
The pair of rotating heads are called a magnetic head A and a magnetic head B.
In the case of a stereo PCM signal, the L (left) channel
Of odd-numbered data Le and R (right) channel
The data Ro is recorded on the magnetic tape by the magnetic head A.
The odd-numbered data Lo and R channels of the L channel are recorded.
The even-numbered data Re of the channel is read by the magnetic head B.
Recorded on magnetic tape. Thus, each magnetic head
The formed pair of tracks is an interleaved pair
be called. Recorded on interleaved pair tracks
The data has the same frame address in the additional code.
On the playback side from the frame address.
It is possible to know the leave pair. Play data
Is subjected to the error correction processing described above and
PCM in which the reproduction data of each of the leave pairs is combined
Converted to a signal. Further, in order to increase the utilization rate of the magnetic tape,
Recording method without guard band between tracks
Is used. That is, the gap of the magnetic head A is extended.
Direction is different from the extension direction of the gap of the magnetic head B.
And crosstalk from adjacent tracks causes azimuth loss
Therefore, it is suppressed. [0005] SUMMARY OF THE INVENTION The above rotary head type
In digital tape recorders, each block of playback data
Block address for writing to the buffer memory,
Additional code such as a frame address indicating an interleaved pair
For simple mode, simple parity is used separately from the PCM signal.
Error detection code is applied. However,
This error detection code has low reliability of the error detection result.
And the replayed block address is incorrect,
Playback data was written to the wrong block address
The frame address is incorrect,
Probe pair is formed by extraneous data,
An unpleasant abnormal sound may be generated. PCM signal
Performs C1 decoding and C2 decoding using the error correction code of
However, the generation of abnormal sound could not be completely prevented. [0006] Therefore, an object of the present invention is to surely provide an abnormal sound.
Digital tape recorder that can prevent the occurrence of noise
Is to provide a da. [0007] SUMMARY OF THE INVENTION The present invention provides a pair of magnetic
Rotation with heads mounted at a predetermined angular interval
Reproduction from head and magnetic tape wound around rotating head
Demodulation means for demodulating a signal and reproduction obtained from the demodulation means
In signalWith a predetermined periodAdditional code error included
Error detection means for detecting
didOf the above additional codeThe number of errorsOver a period of time
A counter for counting, and a large value of the count value of the counter and a predetermined value.
Small relationshipFor each reproduction signal of the pair of magnetic heads
ToDiscriminationAnd determine if there are many errorsNumber detection hand
Stage and reproduced signal obtained from demodulation meansDi included
Digital dataError correction means for performing error correction processing
And from the error correction meansofInterpolate for corrected signal
Interpolating means for performing processing;By
Both reproduced signals of a pair of magnetic heads have errors.
When it is determined that there are many, the correction result of the error correction means and
Irrespective ofInterpolation means pre-hold or muty
OperationTo doDigit characterized by controlling
It is a tar tape recorder. [0008] [Function] The additional code decoder detects an error.
Judging the quality of playback data from the amount of data output
Can be. Many error data in additional code to be reproduced
When data is detected, the quality of the reproduced data is
There is a high possibility that an erroneous decoding process is performed on the M signal.
Therefore, many error data were detected in the additional data.
In the case, the pointer is independent of the error correction of the PCM signal.
Is set. The interpolation circuit
The interpolation operation such as the previous value hold is performed according to the data. [0009] BRIEF DESCRIPTION OF THE DRAWINGS FIG.
Applied to tape recorder (abbreviated as R DAT)
An embodiment will be described with reference to the drawings. This one implementation
The description of the examples will be made in the following order. a. Overall configuration of digital tape recorder b. Data structure of digital tape recorder c. Error correction code for digital tape recorderissue d. Playback signal processing circuit e. Frame address judgment circuit f. Control of interpolation operation and error correction operation [0010] a. Overall configuration of digital tape recorder FIG. 1 shows a digital tape recorder of a rotary head type, a so-called digital tape recorder.
2 shows the overall configuration of R DAT. 1 is 30mm in diameter
A drum rotated at 2000 rpm. 1 for drum 1
A pair of magnetic heads 2A and 2B at an angular interval of 80 °
Is attached. 90 ° wrap around drum 1
Magnetic tape 3 (indicated by dashed line) is wound diagonally at the corner
Attached. The magnetic tape 3 is a reel of a tape cassette
Spanned between hubs 4A and 4B,
And pinch roller 6 at a speed of 8.15 (mm / sec)
Be run. The magnetic heads 2A and 2B are alternately
By sliding contact with the step 3, it was inclined as shown in FIG.
Tracks 7A and 7B are formed on the magnetic tape 3. Magnetic
The tape width A of the air tape 3 is 3.81 mm. One time
The magnetic gap of the transfer head 2A is perpendicular to the track.
+ Α with respect to the direction, the magnetism of the other rotary head 2B
The gap is inclined at -α with respect to the direction perpendicular to the track.
Have been. (Α = 20 °). This magnetic
The angles of the magnetic gaps of the heads 2A and 2B are respectively +
They are called mass and -azimuth. The magnetic heads 2A and 2B switch heads.
Switch 8 alternately selects the recording / playback switch.
The recording signal from the terminal r of the switch 9 is supplied to a rotary transformer (not shown).
) Is supplied to the magnetic heads 2A and 2B via the
Reproduced signals from the heads 2A and 2B are converted by rotary transformers.
(Not shown) to the terminal p of the recording / playback switch 9
Taken out. The analog audio signal from the input terminal 10
Signal to the A / D converter 12 via the low-pass filter 11
(Sampling frequency: 48KHz, 16 bit
Into a digital audio signal.
Is replaced. Digital audio from A / D converter 12
The E signal is supplied to the recording signal processing circuit 13. Recording signal
In the processing circuit 13, the error of the digital audio signal
Correction encoding and the format of recorded data as described later
Is converted to In this case, the recorded signal
Re-emphasis on / off, sampling frequency, amount
ID signal (PCM-ID) for identifying the number of child bits
Will be added. Also, the program number of the recorded signal
For sub-codes and time codes
ID signal (subcode ID) is a subcode encoder
(Not shown), and a recording signal
It is supplied to the processing circuit 13. From the recording signal processing circuit 13, one track
The serial recording data for each minute is stored in the magnetic heads 2A and 2A.
It occurs in synchronization with the rotation of B. Recording data is recorded by amplifier
15 and the head through the terminal r of the recording / reproducing switch 9
It is supplied to the changeover switch 8. Head switching switch
The switch 8 allows the recording data to be transferred to the magnetic heads 2A and 2B.
Are supplied alternately. Reproduced by the magnetic heads 2A and 2B
The signal is sent to the head changeover switch 8 and the recording / reproduction switch.
The signal is supplied to the reproduction amplifier 16 through the terminal p of the switch 9.
The output signal of the reproduction amplifier 16 is supplied to the PLL 17 and
In LL17, a clock synchronized with the reproduction signal is extracted
Is done. The reproduction signal is supplied to the reproduction signal processing circuit 18.
After processing such as error correction and interpolation,
The Dio signal is supplied to the D / A converter 19. D / A change
The reproduced audio signal from the converter 19 is a low-pass filter.
It is taken out to the output terminal 21 through 20. With this
In the reproduction signal processing circuit 18, the subcode and the subcode
The code ID is separated and taken out to the output terminal 22. Out
A sub-code decoder is connected to the input terminal 22 for control.
Data is formed from the subcode. Head switch 8 and recording / reproducing
The control signal for controlling the changeover switch 9 is
It is formed by the mining control circuit 23. Also, timing
The recording control circuit 23 includes a recording signal processing circuit 13 and a reproduction signal.
The clock signal and timing required by each of the processing circuits 18
Generate a signaling signal. [0017] b. Data structure of digital tape recorder The entire data recorded on one track is one segment
Referred to as FIG. 3A shows recording by one rotating head.
1 shows the structure of the data of one segment. Record data
When the unit amount of is one block, one segment includes
Includes 196 blocks of data (7500 μsec)
You. One end of one segment corresponding to the end of the track
Each has a margin (11 blocks). This ma
Subcode 1 and subcode 2 adjacent to each
Is recorded. These two subcodes have the same data
And there is a double record. The subcode is
Program number and time code. Of subcode
PLL run-in sections on both sides of the 8-block recording area
(2 blocks) and post amble section (1 block)
H) are arranged. Further, an interface where data is not recorded is used.
・ Block gap is provided, and 3 blocks
-A block for the ATF
Signal is recorded over 5 blocks. 1 segment
Within a 130 block long area at the center of the
128 blocks excluding the block's PLL run-in section
PCM signal that has been recorded is recorded in the area of the
Is done. This PCM signal indicates that the rotary head makes a half turn.
Data corresponding to the audio signal at a certain time. The PCM signal includes an L (left) channel and
2-channel stereo P consisting of R and R (right) channels
Parity data of CM signal and error detection / correction code
Become. One segment shown in FIG.
When recording / reproducing is performed by A, the PCM signal recording area
Data Le is recorded in the left half, and the right half thereof is recorded.
Data Ro is recorded in the section. Data Le is L
The even data of the channel and the
Parity data, and data Ro is an R channel
Odd-numbered data and parity for this data
Consists of data. Odd and even numbers are interleaved
This is the order counted from the beginning of the block. The track formed by the other magnetic head
1 segment with the same configuration as one of the above tracks
Event data is recorded. One track of this other track
Segment in the segment data, the left half
Is recorded in the right half of the data Re.
Is recorded. Data Re is an even-numbered R channel
Data and parity data for this data
Become. Data Lo is the odd-numbered data of the L channel.
And parity data for this data. This
, Even number data and odd number data of each channel
Eye data is recorded separately on two adjacent tracks
With the L channel and R channel on the same track.
The data of the file is recorded by dropout etc.
Prevents consecutive data on the same channel from being mistaken.
That's because. FIG. 3B shows the data of one block of the PCM signal.
2 shows a data configuration. 8 bits (1 symbol) at the beginning of one block
), And the 8-bit P
CM-ID is added. After PCM-ID, block
Address is added. This PCM-ID and block
The two symbols (W1 and W2) of the address
The error correction coding process of pure parity is performed,
Is added next to the block address. B
The lock address is, as shown in FIG.
(MSB), and consists of 7 bits.
By setting the bit to “0”, the PCM block
It is shown that there is. The 7-bit block address is (00)-
(7F) (hexadecimal display). Block ad
3 bits of the address are (000) (010) (100)
PCM-ID recorded in each block of (110) is fixed
Is being used. The lower three bits of the block address are (0
01) (011) (101) (111)
Dress can record PCM-ID optional code
It is said to be capable. 2 bits each in PCM-ID
ID1 to ID8 and 4-bit frame address
It is. ID1 to ID7 each have identification information defined.
You. A pack is composed of 32 ID8s. example
For example, ID1 is a format ID for audio.
Or other uses are identified by ID1 and by ID2,
Pre-emphasis on / off and pre-emphasis features
The sampling frequency is identified by ID3.
Separated. ID1 to ID7 described above and frame address
Is the same data in the segment of the interleaved pair
Is done. FIG. 3C shows the data of one block of the subcode.
2 shows a data configuration. The same data structure as the PCM block described above
It is said to be done. As shown in FIG.
Of the symbol W2 is set to “1”, and
It is indicated that it is a hard disk block. This symbol W2
Of the symbol W
8 bits of 1 and the MSB and block address in symbol W2
The three bits excluding the dress are used as the subcode ID.
You. 2 symbols of subcode block (W1 and W2)
Error correction coding for simple parity
Then, 8-bit parity is added. The subcode ID is an even block address.
The number (the LSB (least significant bit) of the block address is
"0") and its odd number (block
The LSB of the address differs from that recorded in "1").
Data. Subcode ID contains the playback method
Control ID, time code, etc.
ing. Subcode data is stored in the same way as PCM data.
Error-corrected code processing by
ing. [0025] c. Error correction code for digital tape recorder For every 128 blocks of data recorded in one segment
Are subjected to error detection / correction code processing. FIG. 4A
Is the code of the data recorded by one magnetic head 2A.
FIG. 4B shows the structure of the other magnetic head 2B.
1 shows a code configuration of data to be recorded. The number of quantization bits is
The 16-bit PCM signal has upper 8 bits and lower 8 bits.
It is divided into 8 bits, and the error
-The detection / correction code is encoded. In one segment, (128 × 32 = 40)
(96 symbols). As shown in FIG. 4A
, From the symbol (L0, L2, ... L1438)
And the even-numbered data Le of the L channel and (R1, R
3, ... R1439) R-channel odd-numbered data
Vertical and horizontal of a two-dimensional array of data consisting of Ro
Error detection code C1 and error correction for each of the directions
The coding of the code C2 is performed. 28 vertical thins
Bol has a (32,28,5) Reed-Solomon code
The used C1 code is encoded. This C1 code 4
The parity data P of the symbol is the last position in the two-dimensional array
Distributed to. For 52 symbols in the horizontal direction,
C using the (32,26,7) Reed-Solomon code
Two codes are encoded. This C2 code is 52 synths.
This is done for every 26 symbols of Bol
Parity of 6 symbols for one code sequence
Data Q is generated. Is it a total of 12 symbols of C2 code?
Is arranged in the center of the two-dimensional array.
You. The other 52 PCM data located in the horizontal direction
The same C2 code is also applied to symbols.
Of parity data Q is arranged at the center. The code configuration shown in FIG. 4B corresponds to the code configuration of FIG. 4A.
The even-numbered PCM signal of the L channel in the
Even-numbered PCM signals (R0, R2,.
・ R1438), the odd number of the R channel
The odd-numbered PCM signal of the L channel
Code replaced by (L1, L3, ... L1439)
Configuration. In these code configurations, they are arranged in the vertical direction.
For 32 symbols, as shown in FIG.
Number, PCM-ID, block address and parity
Add to form one PCM block.
It is. D. Playback signal processing circuit The present invention relates to the above-described rotary head type digital tape recorder.
The reproduction at the time of variable-speed reproduction in the reproduction signal processing circuit 18 of the coder
Applied to raw data processing. FIG. 5 shows a reproduction signal processing cycle.
9 shows a configuration of the path 18, and a reproduced signal is input to an input terminal indicated by 31.
Supplied. The reproduced signal is supplied to a demodulation circuit 32 and
10 bits of symbol are demodulated into 8 bits of 1 symbol
You. When recording on the magnetic tape 3, one symbol of 8 bits
Is 10 bits to reduce low frequency components as much as possible.
Of Digital Modulation Converted to Preferred Pattern
Is receiving. The reproduction data from the demodulation circuit 32 is
One symbol via the register 33 and the buffer 34
At the same time. The data bus 35 has a buffer RAM 36
And an error correction circuit 37. Data bus
Reproduction data is taken into buffer RAM 36 from 35
In the error correction circuit 37, the buffer RAM 36
The data stored in the
It undergoes error correction processing (C1 decoding and C2 decoding).
The error-corrected PCM signal is supplied to an interpolation circuit 38.
The error that cannot be corrected is interpolated and output to the output terminal 39 again.
The raw PCM signal is extracted. This reproduced PCM signal is D
/ A converter 19 (see FIG. 1). Also,
The subcode is transmitted by a subcode decoder (not shown).
Output, sub-code output terminal
Is taken out. In addition, a block address is associated with the demodulation circuit 32.
A dress detection circuit 40 is provided. Block address
The read block address is read by the
Can be The reproduction block address is stored in the address generation circuit 41.
Supplied to The address generated by the address generation circuit 41
The raw address is used as an address signal of the buffer RAM 36.
You. The playback block address is one segment (32
(X128 blocks) (see FIG. 4)
From the first block to the 128th block,
No. is an address for writing for each block. An ECC (error) is generated by the address generation circuit 41.
An address for the correction circuit is also generated. This EC
The C address is supplied to the buffer RAM 36. EC
The address for C is used for each of C1 decoding and C2 decoding.
Address for reading data from buffer RAM 36
Buffer and the data and pointer after error correction
This is an address for writing to M36. At the time of C1 decoding, it is preceded by a reproduction address.
C1 series data (PCM signal and
And parity data P) are stored in a buffer RAM for each block.
36, and the error is corrected by the error correction circuit 37.
-The corrected PCM signal and C1 pointer are
Written to the same block address of the
You. The C1 pointer indicates the location where the parity P was written.
Written to the Molly area. This error correction process is all
Is performed on the C1 sequence of ECC address is above
The read address and write address in the C1 decoding described above.
Raise the dress. At the time of C2 decoding, C1 decoding is performed.
The PCM signal, C1 pointer and parity data Q are C2
It is read out for each stream, and the error correction circuit 37
2 Decryption processing is performed. This C2 decoding is an error correction code.
Correction of one or two symbols using signal C2 and C1
And erasure correction using a pointer. C2 decryption
The PCM signal and the C2 pointer that have been error-corrected by
The data is written to the buffer RAM 36. In this C2 decryption
Required read and write addresses
The dress is formed by the address generation circuit 41. PCM signal after C1 decoding and C2 decoding
The signals are read from the buffer RAM 36 in the original order.
In this case, the track T of the interleaved pair_AAnd tiger
Cook T_BError-corrected PCs played from
The M signal forms a two-channel stereo signal
You. PCM with error correction from buffer RAM 36
In order to read out the signal, it is formed by the address generation circuit 41.
The supplied address is supplied to the buffer RAM 36,
The PCM signal read from the RAM 36 is supplied to the interpolation circuit 3
8 is supplied. In the reproduced data obtained from the demodulation circuit 32,
Frame address is frame address from PCM-ID
The frame address F is detected by the detection circuit 42.
The RAD sends the frame address together with the playback block address.
And is supplied to the The PCM- obtained from the demodulation circuit 32
ID or subcode ID (W1), block address
(W2) and the parity are supplied to the error detection circuit 44.
In the error detection circuit 44, simple parity is used.
Error detection is performed. From this error detection circuit 44
An error pulse indicating the presence or absence of an error is generated. This error
-Pulse becomes "1" when there is an error and there is no error
It becomes "0" at that time. Error pulse
It is supplied to the address determination circuit 43 and the counter 45. Cow
The counter 45 outputs an error pulse that becomes “0” without error.
Counting is performed for one segment of reproduced data. The count value of the counter 45 is the number detection circuit 4
7, is supplied to the comparison circuit 48 and the register 46. Magnetic
1-segment reproduction data reproduced by the head 2A
The count value of the counter 45 for
And then reproduced by the magnetic head 2B.
The count value of the counter 45 and the record
The count value of the register 46 is compared by a comparing circuit 48.
You. In the comparison circuit 48, these count values are compared.
1-bit comparison output signal corresponding to the count value
Occurs. This comparison output signal is used as the interpolation control circuit.
49. The number detection circuit 47 includes the magnetic head 2A and
1B of reproduced data reproduced by each of 2B
Is detected whether or not the count value is less than or equal to a predetermined number n.
n is set to 7, for example. The number detection circuit 47
Of the magnetic heads 2A and 2B
Generates a detection signal that becomes "1" when both are less than n
I do. This detection signal is supplied to the interpolation control circuit 49.
Is done. Further, the interpolation control circuit 49
The determination signal NGAB from the frame address determination circuit 43 is
And a track identification signal is supplied from the terminal 50.
Be paid. The frame address determination circuit 43 will be described later.
As described above, the error detection circuit 44 determines that there is no error.
Most significant bit of the specified block address and the least significant bit
Bit and frame address F determined to have no error
Using the RAD to set the frame address in one track
Discrimination signal NGTR and the frame address of the adjacent track
A determination signal NGAB for the dress is generated. Discrimination
The signal NGTR has different frame addresses within one track.
It becomes "1" when a signal is detected. Frame address
Is for PCM signals that form an interleaved pair
Are the same, and different tracks within one track.
The detection of a frame address indicates that another track
It is an abnormal playback operation that occurs when cutting and playing back etc.
You. This determination signal NGTR is supplied to the error correction circuit 37.
Is done. When the discrimination signal NGTR is "1", the error correction circuit
In the path 37, the erasure correction using the C1 pointer is executed.
Rows are prohibited. The discrimination signal NGAB is output from the magnetic head 2
A and the read signal of the magnetic head 2B are included in each of
"1" when the frame addresses do not match
Become. Interleave is performed by this discrimination signal NGAB.
It is detected that the pair is not formed. This discrimination signal
The signal NGAB is supplied to the interpolation control circuit 49.
When the determination signal NGAB is “1”, the error detection circuit 4
4 is one of the magnetic heads having less error detected.
The read data of the other magnetic head is supplemented using the read data.
Intervened. The interpolation control circuit 49 includes the interpolation circuit 3
8 to generate an interpolation control signal. The interpolation circuit 38
In the PCM signal after error correction processing,
The PCM signal words that cannot be corrected
Average value interpolation, previous value hold, and the like. Interpolation controller
For example, the interpolation control signal from the roll circuit 49 becomes “1”.
For PCM signals, the interpolation operation is forcibly performed.
You. E. Frame address judgment circuit FIG. 6 shows an example of the configuration of the frame address determination circuit 43.
Show. The frame address determination circuit 43 includes the magnetic head 2
A by the track A reproduced by A and the magnetic head 2B
Frame address matches with track B to be played
Output terminal 6 outputs a determination signal NGAB indicating whether the
2 and the frame address is one in one track.
An output terminal for a determination signal NGTR indicating whether or not
Occurs at 61. PCM-ID of PCM block (FIG. 3B)
(W1) is multiplex-written at a cycle of 8 blocks.
Therefore, in one segment, (128/8 = 16)
Each time, the same PCM-ID is recorded. Also block
Address (W2) changes sequentially from (06) to (7F)
However, according to the least significant bit B0 of this block address,
ID code and optional code can be distinguished.
You. PCM-I of the block address of (B0 = "0")
D is a standardized ID signal, and this block
ID1 to ID8 and the frame address (4 bits
G) is included. Further, the frame address is
Code that changes sequentially from (0000) to (1111)
Signal, the same code in the interleaved pair
It is. Whether or not an interleaved pair is
Can be determined by the lower two bits FRAD of the address.
Wear. Most significant bit of block address (S / Pid signal
Signal, the PCM block (S / Pid signal:
“0”) and a subcode block (S / Pid signal:
"1"). The S / Pid signal is input to the input terminal 63 in FIG.
Signal is supplied to the input terminal 64 and the bottom of the block address.
Bit B0 is supplied, and both are EX-NOR (EX
(Negative NOR) gate 68. Therefore,
The output signal of the EX-NOR gate 68 is a PCM block.
And in a standardized PCM-ID block
It becomes “1”. The output signal of this EX-NOR gate 68
Is supplied to the AND gate 69. To AND gate 69
Provides the error pulse inverted by the inverter 70.
Be paid. The error pulse is “0” when there is no error.
Therefore, when it is determined that there is no error, the AND
An output signal is obtained from the terminal 69. This AND gate 69
Is output to the enable terminal of the flip-flop 71.
Supplied. The flip-flop 71 has a frame address
2 bits of address (simply called frame address)
FRAD is supplied. Therefore, it is determined that there is no error.
The frame address FRAD of the PCM-ID
It is taken into the flop flop 71. Flip-flop 71
Is supplied to the flip-flop 72. EX-N
Frame address from input terminal 65 to OR gate 73
FRAD and frame address from flip-flop 71
And are supplied. For flip-flops 71 and 72
Is supplied with a clock pulse of the block cycle, not shown
Have been. The output of the EX-NOR gate 73 is AND gated.
To the port 74. AND gate 74 has AND
An output signal of the gate 69 is supplied. AND gate 74
Is output to the enable terminal of the flip-flop 72.
Supplied. Therefore, the same
Frame address is stored in flip-flops 71 and 72
available. Each of the flip-flops 71 and 72 stores
The obtained 2-bit frame address is EX-OR
It is supplied to the gate 75. EX-OR gate 75 output
The signal is provided to AND gate 76. AND gate 7
6 is supplied with the output signal of the RS flip-flop 77.
It is. The RS flip-flop 77 connects the inverter 78
Set by the output signal of AND gate 74
From the terminal 67 via the inverter 79.
Reset by Luth CLR. The clear pulse CLR is applied to the magnetic field shown in FIG.
The output A of the head 2A and the output B of the magnetic head 2B are obtained.
The first timing of the 90 ° rotation angle period (see FIG. 7)
The pulse of B). Therefore, the RS flip-flop 7
7 is the output of the frame address determined to have no error.
If the two FRADs match twice, it becomes "1". This RS
Output of flip-flop 77 is supplied to AND gate 76
Is done. The output signal of the EX-OR gate 75 has two signals.
"1" when the frame address FRAD does not match
Therefore, the output signal of the AND gate 76 has two frames.
It becomes "1" when the addresses do not match. AND gate
The output signal of 76 is stored in flip-flop 80. The output signal of flip-flop 80 is
Setting of the RS flip-flop 82 via the
And the clear pulse CLR is output through the inverter 83.
As a reset input of the RS flip-flop 82.
The output signal of the RS flip-flop 82 is a determination signal N
It is taken out to the output terminal 61 as GTR. This discrimination signal
NGTR has the same frame address within one track
It becomes "1" when not performed. In order to generate the discrimination signal NGAB,
The flip-flop 84, the EX-OR gate 85 and the flip-flop
A flip-flop 86 is provided. flip flop
84 and the flip-flop 86 have the clock shown in FIG.
Clock pulse CK1 and the clock pulse CK shown in FIG. 7D.
2 are each supplied. The flip-flop 84 has a free
The output signal of the flip-flop 72 becomes the clock pulse CK1.
More taken in. The clock pulse CK1 is shown in FIG.
Thus, the reproduction of each of the magnetic head 2A and the magnetic head 2B
The frame address FR detected as described above from the signal
AD (stored in flip-flop 72)
This is a clock for taking in the flip-flop 84. E
The X-OR gate 85 causes the one magnetic head 2A to re-start.
The frame address detected from the raw signal and the other magnetic head
And the frame address detected from the reproduced signal of the
Match is detected. When they match, it becomes “0”.
EX-OR gate that becomes “1” when they do not match
The output signal of the clock 85 is clocked to the flip-flop 86.
Captured by Lus CK2 (FIG. 7D). This pretend
The output signal of the flip-flop 86 is used as the discrimination signal NGAB
It is taken out to the output terminal 62. F. Control of interpolation operation and error correction operation In one embodiment of the present invention described above, the interpolation circuit 38
Normally, each word of the PCM signal from the error correction circuit 37
The interpolation operation is performed using the pointer attached to. This normal
Generated by the interpolation control circuit 49 separately from the interpolation operation of
In response to the interpolation control signal,
The interpolation operation is forcibly performed independently of the interface. This strength
FIG. 8 shows a reproduction state when a regular interpolation operation is performed.
It will be described with reference to FIG. FIG. 8 shows the respective magnetic heads 2A and 2B.
4 illustrates an example of a reproduction signal. FIG. 8A shows a magnetic head 2A.
And the amplitude of the reproduced signal of the magnetic head 2B are both
This is the case when it becomes smaller. For example, azimuth at the time of reproduction
Unlike recording, azimuth loss causes the amplitude of the reproduced signal
Playing back an area that has become smaller or has no data recorded
Therefore, the amplitude of the reproduced signal is reduced. Such playback state
Then, as a result of the error detection by the error detection circuit 44, the error
Is reduced to n or less. Naturally, magnetic
The reproduced signals from the heads 2A and 2B are both n or less.
As a result, the output of the number detection circuit 47 becomes "1". This
Therefore, the interpolation control circuit 49 sends the magnetic head 2A and
Pointers for both the playback signals 2B and 2B
An interpolation control signal to be set is generated. The interpolation circuit 38
Since many pointers are set, the previous value hold
Operation or muting operation. FIG. 8B shows the reproduction signal of one magnetic head 2A.
Is the normal amplitude and the other magnetic head 2B reproduces
This shows a case where the signal amplitude is small. For example, one magnet
Make a connection record using the device whose head is clogging.
In this case, a reproduced signal shown in FIG. 8B is generated. like this
In the reproduction state, the reproduction signal of the magnetic head 2B has an error.
, The quality of the corrected PCM signal is poor. One
In the case of blind recording, two adjacent frame addresses
Do not match between tracks. Therefore, the frame address
When the determination signal NGAB formed by the determination circuit 43 is "1"
Become. In the comparison circuit 48, two adjacent tracks are used.
Playback with less error for playback data from
Data is detected. In the interpolation control circuit 49, the judgment signal
When NGAB is "1", the comparison output signal of the comparison circuit 48
Is enabled and the playback data with less error is used.
Control signal to interpolate the playback data with the more error
A signal is formed. PCM signal supplied to the interpolation circuit 38
Of the sequence (L0, R0, L1, R1, L2, R2, L
, R3, L4...), (L0, R1, L
, R3, L4,...) Reproduced by the magnetic head 2A.
(R0, L1, R2, L3,...)
.) Is a PCM signal reproduced by the magnetic head 2B.
You. From the input terminal 50 to the interpolation control circuit 4
9 is supplied to the magnetic head 2A.
It becomes “0” during the period of the PCM signal reproduced from
"1" during the period of the PCM signal reproduced by the head 2B
Is a pulse signal. Compare with this track identification signal
From the comparison output signal of the circuit 48 and one of the magnetic heads
A complement that becomes “1” corresponding to the period of the reproduced PCM signal
Control signal is generated in the interpolation control circuit 49.
It is. For the PCM signal during the period when the interpolation control signal is "1"
Pointer is set. Therefore, the interpolation circuit 38
Is a reproduction PCM of one of the magnetic heads having less error.
The reproduced PCM signal of the other magnetic head is supplemented using the signal.
Intervened. FIG. 8C shows that the track is bent.
The magnetic head 2A and the magnetic head 2B are
Head 2A and magnetic head when scanning is performed halfway
2B shows respective reproduction signals. Such a rebirth letter
State is different as frame address in one track
The signal is reproduced, and the discrimination signal NGTR becomes “1”. This
Is supplied to the error correction circuit 37,
Pointer erasure correction in C2 decoding is prohibited
You. In the C2 decoding, an error using the error correction code C2 is used.
Error symbol of 1 symbol or 2 symbols by correction
Is corrected and the C1 pointer generated by C1 decoding is
The erasure correction is performed using a counter. But
As described above, the magnetic head straddles two tracks as described above.
In a playback state, such as scanning, the signal generated in C1 decoding is used.
The reliability of the obtained C1 pointer is low.
Erasure correction is prohibited by the discrimination signal NGTR.
You. Control of interpolation operation and error correction as described above
By controlling the normal operation, unpleasant abnormalities can be
The generation of ordinary sound is reliably prevented. Note that the PCM-ID of the recording data is
Error detection by CRC code other than simple parity
The present invention cannot be applied to the case where the data
You. [0063] According to the present invention, the PCM signal
Decoding status of additional code separately from the error correction code decoding result
Mode, the amplitude of the reproduced signal is reduced,
Error correction code may cause erroneous decoding.
Also ensure that abnormal playback sounds are not generated.
Can be.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the overall configuration of a rotary head type digital tape recorder to which the present invention can be applied. FIG. 2 is a schematic diagram illustrating a tape format of a digital tape recorder. FIG. 3 is a schematic diagram used for describing a track format and a block format of the digital tape recorder. FIG. 4 is a schematic diagram used for describing an error correction code of the digital tape recorder. FIG. 5 is a block diagram of a main part of one embodiment of the present invention. FIG. 6 is a connection diagram illustrating a configuration of a frame address determination circuit and a time chart used for describing the operation thereof. FIG. 7 is a connection diagram illustrating a configuration of a frame address determination circuit and a time chart used for describing the operation thereof. FIG. 8 is a waveform diagram of a reproduced signal used for describing the present invention. [Description of Signs] 1 Drum 2A, 2B Magnetic head 3 Magnetic tape 13 Record signal processing circuit 18 Reproduction signal processing circuit 32 Demodulation circuit 35 Data bus 36 Buffer RAM 37 Error correction circuit 38 Interpolation circuit 40 Block address detection circuit 42 Frame address detection Circuit 43 Frame address determination circuit 44 Error detection circuit 47 Number detection circuit 48 Comparison circuit 49 Interpolation control circuit

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Kentaro Odaka               6-7-35 Kita Shinagawa, Shinagawa-ku, Tokyo So               Knee Co., Ltd.                (56) References JP-A-60-33740 (JP, A)                 JP-A-58-187843 (JP, A)                 JP-A-61-110380 (JP, A)

Claims (1)

(57) [Claims] A rotating head on which a pair of magnetic heads are mounted at a predetermined angular interval, demodulating means for demodulating a reproduction signal from a magnetic tape wound around the rotating head, and the demodulating means and error detection means for detecting an error of the additional code included with in the reproduction signal obtained from the means in a predetermined cycle, over time the number of errors <br/> over the additional code detected by said error detection means A counter for counting, and a magnitude relationship between a count value of the counter and a predetermined value are defined by the pair.
Discrimination for each reproduction signal of the magnetic head of
Number detection means for determining whether or not there is a large number of bits, and a digit included in a reproduced signal obtained from the demodulation means.
And error correcting means for performing error correction processing of the barrel data, and a interpolating means for performing interpolation processing on the corrected signal from said error correcting means, by the number detecting means, the pair of magnetic heads its
When both playback signals are judged to have many errors
In addition, regardless of the correction result of the error correction means, the interpolation means performs a pre-hold or muting operation .
A digital tape recorder characterized by performing control as follows.