JPS62204470A - Synchronization detector - Google Patents

Abstract

PURPOSE:To prevent the generation of a malfunction state which causes a burst error, and to more certainly prevent the mis-detection of a synchronizing signal generated by an error, etc., by locking a window signal only when the synchronizing signal is detected, and it is decided that no error is included in a block. CONSTITUTION:To a synchronization detection circuit 32, the window signal is supplied from a timing generation circuit 36, and the synchronization detection circuit 32 is controlled based on the window signal, and the synchronization detection circuit 32 is set at a state possible to output the detecting signal S1 of the synchronizing signal in a section where the window signal goes to, for example, a high level. In other words, a part coinciding with the pattern of a prescribed synchronizing signal regarding with a continuous data string of ten bits, is detected, and only when they are coincided, the detecting signal S1 to be set at the high level, of the synchronizing signal is formed at the synchronization detection circuit 32. The detecting signal S1 of the synchronizing signal is supplied to a timing generation circuit 33 only in the section where the window signal is set at the high level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronization detection device suitable for use in a reproduction signal processing circuit of a rotary head type digital tape recorder, for example.

[Summary of the invention]

The present invention provides an error detection circuit as means for determining whether or not a synchronization signal in one block is reliable in a synchronization detection device used, for example, in a reproduction signal processing circuit of a rotary head type digital tape recorder. A window signal is formed in the timing generation circuit using a signal that indicates the presence or absence of an error for each block supplied from the circuit, and this window signal controls the synchronization detection circuit, and only when a synchronization signal that is estimated to be correct is detected. This locks the window signal to prevent malfunctions that may cause burst errors.

[Conventional technology]

For conventional PCM signal processing devices, synchronization with respect to input data is important in processing that data, so a recognition bit for synchronization, that is, a synchronization signal, is added to the data and transmitted. is common.

In order to prevent this erroneous detection of the synchronization signal, a control signal called a window signal is set at a predetermined period, for example, a low level, with respect to the timing of the synchronization signal, and is used for signal reproduction processing. In other words, this window signal is used to detect a synchronization signal that is estimated to be correct in an interval where the wind signal is at a high level, and in a predetermined interval where the wind signal is at a low level, a synchronization signal that is generated due to an error or the like is detected. Detection is likely to be disabled.

[Problems to be Solved by the Invention] However, in the above-mentioned method for preventing false detection of a wind signal, the first detected synchronization signal may be incorrect and the timing of the wind signal may deviate from the correct timing of the synchronization signal. If this is set, there is a problem that a correct synchronization signal cannot be detected, resulting in a burst error state.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a synchronization detection device that is free from malfunctions that cause burst errors and more reliably prevents erroneous detection of synchronization signals.

[Means for solving problems]

The present invention provides a synchronization detection device in which data to which a synchronization signal is added to each block of digital data is input, including a circuit for detecting a synchronization signal, and a circuit for detecting a synchronization signal for a period shorter than one block in response to detection of the synchronization signal. , and a circuit 36 that generates a window signal that turns off the synchronization signal detection operation and turns on the detection operation until the next synchronization signal is detected.

[Effect]

An error detection circuit 35 is provided as means for determining whether the synchronization signal in one block detected by the synchronization detection circuit 32 can be trusted, and the error detection circuit 35 outputs a signal S4 indicating the presence or absence of an error for each block. This signal S4 is supplied to the timing generation circuit 36. Only when it is determined that no error is included, a window signal S5 is generated in the timing generation circuit 36 for a predetermined period shorter than one block, for example, at a low level, based on the timing of the signal S4, and this window signal S5 is synchronized. The signal is supplied to the detection circuit 32. The synchronization detection circuit 32 is controlled by the window signal S, and the output of the detection signal Sl of the synchronization signal is prohibited during the period in which the window signal S is at a low level. In addition, if it is determined that an error is included, the wind signal S,
is maintained at a high level, and the synchronization detection circuit 32 is kept in a state in which it can output the synchronization signal detection signal S1 until a synchronization signal estimated to be correct is detected.

〔Example〕

Hereinafter, an embodiment in which the present invention is applied to a rotary head type digital tape recorder (abbreviated as RDAT) will be described with reference to the drawings.

The description of this one embodiment will follow in the following order.

a. Overall configuration of the digital tape recorder; Data configuration of the digital tape recorder C; Error correction code of the digital tape recorder d; Partial configuration and operation of the reproduced signal processing circuit and timing control circuit e; Configuration of the timing generation circuit 1 shows the overall structure of a rotary head type digital tape recorder, so-called RDAT. 1 is a drum with a diameter of 30 mm and rotated at 2000 rpm. A pair of magnetic heads 2A and 2B are attached to the drum 1 with an angular interval of 180°.

A magnetic tape 3 (indicated by a dashed line) is wound diagonally at the corners to a length of 90'' around the circumferential surface of the drum 1.The magnetic tape 3 is wound around the reel hubs 4A and 4B of the tape cassette.
The capstan 5 and the pinch roller 6
Therefore, it runs at a speed of 8.15 (n+n+/5eC).

As the magnetic heads 2A and 2B alternately come into sliding contact with the magnetic tape 3, an inclined track 7 is formed as shown in FIG.
A and 7B are formed on the magnetic tape 3. magnetic tape 3
The tape width A is 3.81 mm. The magnetic gap of one rotary head 2A is tilted by +α with respect to the direction perpendicular to the tracks, and the magnetic gap of the other rotary head 2B is tilted by 1α with respect to the direction perpendicular to the tracks.

(α=20°). The angles of the magnetic gaps of the two magnetic heads and 2B are called +azimuth and -azimuth, respectively.

The magnetic heads 2A and 2B are operated by a head changeover switch 8.
terminal r of the record/playback switch 9.
A recording signal from the magnetic heads 2A and 2B is supplied to the magnetic heads 2A and 2B via a rotary transformer (not shown), and a reproduction signal from each of the magnetic heads 2A and 2B is supplied to the recording/reproducing switch 9 via a rotary transformer (not shown). It is taken out to terminal p of.

The analog audio signal from the input terminal 10 is supplied to the A/D converter 12 via the low-pass filter 11.
Sampling frequency: 48 KH2 (16-bit linear quantization) and converted to a digital audio signal. A digital audio signal from the A/D converter 12 is supplied to a recording signal processing circuit 13. The recording signal processing circuit 13 performs error correction encoding of the digital audio signal and conversion into a recording data format as described below. In this case, an ID signal (PCM-10) is added that identifies on/off of pre-emphasis, sampling frequency, number of quantization bits, etc. of the signal to be recorded. Also, the program number of the signal to be recorded, subcode such as time code, and ID for the subcode.
A signal (subcode ID) is formed by a subcode encoder (not shown) and is supplied from the terminal 14 to the recording signal processing circuit 13.

The recording signal processing circuit 13 generates serial recording data for each track in synchronization with the rotation of the magnetic heads 2A and 2B. Recorded data is supplied to the head changeover switch 8 through the recording amplifier 15 and the terminal r of the recording/reproduction switch 9.

Recorded data is alternately supplied to the magnetic heads 2A and 2B by the head changeover switch 8.

The signals reproduced by the magnetic helads 2A and 2B are sent to the terminal p of the head changeover switch 8 and the recording/reproduction switch 9.
The signal is supplied to the reproduction amplifier 16 through. Playback amplifier 1
The output signal of PLL 17 is supplied to PLL 17.
At , a clock synchronized with the reproduced signal is extracted.

The reproduced signal undergoes processing such as error correction and interpolation in the reproduced signal processing circuit 18, and the reproduced digital audio signal is supplied to the D/A converter 19. D/A converter 19
A reproduced audio signal is outputted to an output terminal 21 via a low-pass filter 20. At the same time, the reproduced signal processing circuit 18 separates the subcode and subcode ID, and outputs them to the output terminal 22. Output terminal 22
A subcode decoder is connected to the subcode decoder, and control data and the like are formed from the subcode.

Control signals for controlling the head changeover switch 8 and the recording/reproduction changeover switch 9 are generated by the timing control circuit 23. In addition, the timing control circuit 2
3 is a recording signal processing circuit 13 and a reproduction signal processing circuit 18
generates clock signals and timing signals required by each.

b. Data structure of digital tape recorder The entire data recorded on one track is called one segment. FIG. 3A shows 1 recorded by one rotating head.
Indicates the structure of segment data. When the unit amount of recording data is one block, the l segment includes 196 blocks (7500 μsec) of data.

A margin (11 blocks) is provided at each end of one segment corresponding to the end of a track. Subcode 1 and subcode 2 are recorded adjacent to each of these margins. These two subcodes are the same data and are recorded twice.

The subcode is a program number and a time code. PLL on both sides of the 8-block recording area of the subcode
A run-in section (2 blocks) and a post-ampule section (1 block) are arranged.

Also, inter-block blocks where no data is recorded
A gap is provided between the inter-block gaps of three blocks, and pilot signals for ATF are recorded over five blocks. (2) A PCM signal subjected to recording processing is recorded in an area of 128 blocks in length, excluding the 2-block PLL run-in section, within a 130-pro.7-length area at the center of the segment. This PCM signal is data corresponding to an order io signal of the time during which the rotary head rotates A.

This PCM signal consists of a two-channel stereo PCM signal consisting of an L (left) channel and an R (right) channel and parity data of an error detection/correction code. Third
When one segment shown in Figure A is recorded/reproduced by the magnetic head 2A, data Le is recorded in the left half of the PCM signal recording area, and data RO is recorded in the right half. Ru. Data Le consists of even-numbered data on the L channel and parity data regarding this data, and data RO consists of odd-numbered data on the R channel and parity data regarding this data. The odd number and even number are the order counted from the beginning of the interleaved block.

The track formed by the other magnetic head has the same configuration as the one track described above, and one segment of data is recorded thereon. In the data section of one segment of data on this other track, data Re is placed in the left half.
is recorded, and data LO is recorded in the right half. The data Re consists of even-numbered data of the R channel and parity data regarding this data. Data Lo consists of odd-numbered data of the L channel and parity data regarding this data. In this way, recording the even-numbered data and odd-numbered data of each channel separately on two adjacent tracks, and recording the L channel and R channel data on the same track is a method such as dropout etc. This is to prevent errors in consecutive data on the same channel.

FIG. 3B shows the data structure of one block of the PCM signal. ■An 8-bit (1 symbol) block synchronization signal is added to the beginning of the block, and then an 8-bit PCM-10
is added. Next to the PCM-ID, simple parity error correction encoding processing is performed on the PCM-ID and the two symbols (Wl and W2) of the block address to which the block address is added, and the 8-bit parity is It is added after the block address. The block address has the most significant bit (MS) as shown in the third diagram.
It is composed of 7 bits excluding B), and the most significant bit is set to "0" to indicate that it is a PCM block.

The 7-bit block address is (OO) ~ (7F) (1
(in hexadecimal). Lower 3 of block address
Bits are (000) (010) (100) (1
10) The PCM-ID to be recorded in each block is determined. The lower 3 bits of the block address are (001
)(011)(10ri) Each block address (111) can record an optional code of PCM-ID.In PCM-ID, each block address is 2 bits !D1 to ID8 and 4 bits. frame address is included. Identification information is defined for each of 101 to ID7. A pack is made up of 32 108. For example, IDI is a format ID and indicates whether it is for audio or other use. is identified by IDI, and by ID2,
Pre-emphasis on/off and pre-emphasis characteristics are identified, and ID3 identifies the sampling frequency.

The above-mentioned IDI to ID7 and frame address are the same data in the segments of the interleave pair.

FIG. 3C shows the data structure of one block of the subcode. It has the same data structure as the PCM block described above. As shown in FIG. 3E, the most significant bit of the symbol W2 of the subcode block is set to l'', indicating that it is a subcode block.The lower four bits of this symbol W2 are set as the block address, and the symbol W1 The 8 bits of the symbol W2 and the 3 bits excluding the MSB and block address of the symbol W2 are used as the subcode ID.

Simple parity error correction encoding processing is performed on the two symbols (W1 and W2) of the subcode block, and 8-bit parity is added.

Subcode IDs are those recorded at the even numbered block address (LSB (least significant bit) of the block address is "0") and those recorded at the odd numbered number (LSB of the block address is "1"). The data are said to be different. The subcode ID includes a control ID that specifies a reproduction method, a time code, and the like. The subcode data is subjected to error correction code processing using a Reed-Solomon code similarly to the PCM data.

C. Error correction code of digital tape recorder Error detection/correction code processing is performed for each 128 blocks of data recorded in the l segment. Figure 4A is
The code structure of data recorded by one magnetic head 2A is shown, and FIG. 4B shows the code structure of data recorded by the other magnetic head 2B. Quantization bit number is 1
A 6-bit PCM signal is divided into an upper 8-bit node and a lower 8-bit node, and an error detection/correction code is encoded using 8 bits as one symbol.

One segment records data of (128×32=4096 symbols). As shown in Figure 4A, (L
O, L2. ... L 1438) even-numbered data Le of the L channel and (R1, R
The error detection code C1 and the error correction code C2 are encoded in the vertical and horizontal directions of the two-dimensional array of data consisting of the odd-numbered data RO of the R channel of 3, . . . R1439). The 28 symbols in the vertical direction are encoded with a C1 code using a (32, 28, 5) Reed-Solomon code. Parity data P of four symbols of this C1 code is arranged at the last position of the two-dimensional array. Further, 52 symbols in the horizontal direction are encoded with a C2 code using a (32, 26, 7) Reed-Solomon code. This C2 code is 52
This is done for 26 symbols every 2 symbols, and parity data Q consisting of 6 symbols is generated for one code sequence. Parity data Q consisting of a total of 12 symbols of C2 code is arranged at the center of the two-dimensional array. The other 52 PCM data symbols located in the horizontal direction are similarly encoded with the 02 code, and their parity data Q is placed in the center.

The code configuration shown in FIG. 4B converts the even-numbered PCM signal of the L channel into the even-numbered PCM signal (RO) of the R channel in the code configuration of FIG. 4A.

R2, . . . R143B), and the odd-numbered PCM signals of the R channel are replaced by the odd-numbered PCM signals of the L channel (Ll, L3, . . . L1439).

As shown in FIG. 3B, for the 32 symbols arranged vertically in these code configurations, the synchronization signal,
One PCM block is configured by adding an ID, block address, and parity.

d. Structure and operation of reproduced signal processing circuit and timing control circuit The present invention is applied to the detection of synchronization signals in the reproduced signal processing circuit 18 and timing control circuit 23 of the above-mentioned rotary head type digital tape recorder. FIG. 5 shows a partial configuration of the reproduced signal processing circuit 18 and the timing control circuit 23. As shown in FIG. The data recorded on the magnetic tape 3 is converted from 8 bits per symbol to a preferred pattern of 10 bits in order to reduce low-frequency components as much as possible.
Digital modulation processing is performed.

Reproduction signals reproduced by the magnetic heads 2A and 2B are supplied to terminals shown at 31 in FIG. The reproduced signal is supplied from the terminal 31 to the synchronization detection circuit 32, and
The signal is supplied to the demodulation circuit 34.

The synchronization detection circuit 32 is supplied with a window signal from the timing generation circuit 36, and the synchronization detection circuit 32 is controlled based on the window signal, and in an interval where the window signal is at a high level, for example, the synchronization detection circuit 32: It becomes possible to output the synchronization signal detection signal S1. In other words, a portion of a 10-bit continuous data string that matches a predetermined synchronization signal pattern is detected, and only when they match, a synchronization signal detection signal S that is set to a high level, for example, is generated in the synchronization detection circuit 32. be done. This synchronization signal detection signal S is supplied to the timing generation circuit 33 only in the period in which the window signal is at a high level.

In the timing generation circuit 33, based on the timing of the detection signal S of the synchronization signal, a timing signal S2 having a lO bit clock cycle necessary for modulating the reproduced signal of lO bits per symbol into a signal of 8 bits per symbol is generated.
is formed, and this timing signal S2 is supplied to the demodulation circuit 34.

At the same time, in the timing generation circuit 33, based on the timing of the detection signal S1 of the synchronization signal, the error detection circuit 35 is reset for each block, and W1 data, W2 data, and parity data (third
A timing signal S3 necessary for capturing the data (see FIG. B and FIG. 3C) is generated, and this timing signal S3 is supplied to the error detection circuit 35.

In the demodulation circuit 34, serial reproduction data of 1 symbol and 10 bits is converted into 1 symbol at the timing of the timing signal St.
The symbol is demodulated into 8-bit reproduced data, and
Converts to bit-parallel playback data. This 8-bit parallel reproduced data is supplied to the error detection circuit 35 and also to the data register 37.

A timing signal S is supplied to the error detection circuit 35, and the error detection circuit 35 is reset at the timing of the timing signal S, and W1 data, W2 data, and parity data are sequentially taken into the error detection circuit 35. , error detection is done based on simple parity. That is, the exclusive OR of W1 data, W2 data, and parity data is calculated, and the presence or absence of an error is determined based on whether the obtained 8-bit results are all "0".

The error detection circuit 35 generates a signal S that is set to a low level for a predetermined period only when the data is determined to contain no errors.

A signal S4 indicating the presence or absence of this error is supplied to the timing generation circuit 36.

In the timing generation circuit 36, a window signal S for controlling the synchronization detection circuit 32 is generated. At the timing when the signal S4 indicating the presence or absence of an error from the error detection circuit 35 falls to a low level, a window signal Ss is set to a low level for a period shorter than a preset l block (360 bit clocks) and is set to a high level for other periods.
is formed. This window signal S is the synchronization detection circuit 3
2.

Further, in the timing generation circuit 36, a signal S6 for controlling the data register 37 is formed, and this signal S'6 is supplied to the data register 37. The data register 37 is supplied with parallel reproduction data of 8 bits per symbol from the demodulation circuit 34, and the reproduction data is written to the data register 37 for each symbol at the timing of the signal S from the timing generation circuit 36. .

The reproduced data written in the data register 37 is supplied to the data bus 39 symbol by symbol via the buffer circuit 38.

A buffer RAM 40 and an error correction circuit 41 are coupled to the data bus 39 . Reproduction data is taken from the data bus 39 into the buffer RAM 40, and in the error correction circuit 41, the data stored in the buffer RAM 40 is subjected to error correction processing using Reed-Solomon codes.

The error-corrected PCM signal is supplied to an interpolation circuit 42, where uncorrectable errors are interpolated, and a reproduced PCM signal is taken out at an output terminal 43. This reproduced PCM signal is
/A converter 19 (see FIG. 1). The second subcode is subjected to processing such as error correction by a subcode decoder (not shown).

e. Configuration and operation of the timing generation circuit FIG. 6 shows an example of the configuration of the timing generation circuit 36 described above, and the portion surrounded by a broken line 36 in FIG. 6 shows the timing generation circuit. Further, a portion surrounded by a broken line 32 indicates a synchronization detection circuit. Timing generation circuit 3
6 is a negative OR circuit 52. Counter 53. Decoder 55
and a flip-flop 56, and the synchronization detection circuit 32 is composed of a coincidence detection circuit 57 and an AND circuit 58.

One input terminal 5 of the OR circuit 52 whose terminal 51 is a negative input
2a and to a negative reset input terminal 56a of flip-flop 56. OR circuit 52
The output terminal of the counter 53 is connected to the reset input terminal of the counter 53. A predetermined carry output terminal 53a of the counter 53 and the other input terminal 52b of the OR circuit 52 are connected, and a parallel output terminal of the counter 53 is connected to an input terminal of the decoder 55. The output terminal of the decoder 55 is connected to the negative set input terminal 56bm of the flip-flop 56. A clock input terminal of counter 53 and a terminal 54 are connected. The Q output terminal of the flip-flop is connected to one input terminal of an AND circuit 58. The other input terminal of the AND circuit 58 and the output terminal of the coincidence detection circuit 57 are connected,
The output terminal of the A N D circuit 58 is led out as an output terminal 59 .

The terminal 31 is connected to the input terminal of the coincidence detection circuit 57, and the reproduced signal is supplied from the terminal 31 to the coincidence detection circuit 57, as described above. The coincidence detection circuit 57 detects a portion of the 10-bit continuous data string that matches a predetermined synchronization signal pattern. When the synchronization signal is detected, a synchronization signal detection signal S is generated as shown in FIGS. 7B and 8C, for example, and this detection signal S is supplied to the timing generation circuit 33 (see FIG. 5). be done.

In the timing generation circuit 33, a timing signal S3 is generated as shown in FIG. 7C, and this timing signal S is supplied to the error detection circuit 35 (see FIG. 5). A signal S4 indicating the presence or absence of an error is formed in the error detection circuit 35 and is supplied to a terminal indicated by 51 in FIG. The signal S4 from the terminal 51 is input to one input terminal 52a of the negative OR circuit 52 and the flip-flop 5.
It is supplied to the reset input terminal 56a of No. 6.

If the error detection circuit 35 determines that no error is included, a signal S4 that falls to a low level is formed as shown in Figure 7, and the timing at which the signal S4 falls to a low level (B in Figure 8) is generated. (see), the output of the OR circuit 52 is set to high level, and the counter 53 is reset. At the same time, at the timing when the signal S4 falls to the low level (see FIG. 8B), the flip-flop 5
6 is reset, and the output of the flip-flop 56, ie, the window signal S, is brought to a low level and held as shown in FIG. 7E and FIG. 8A. Therefore, AND circuit 5
The output signal S+' of 8 is always at a low level regardless of the level of the synchronizing signal detection signal SI until a low level signal is supplied to the cent input terminal 56b of the flip-flop 56, and the synchronizing signal detection signal S1 is Output is prohibited.

The clock input terminal of the counter 53 has P
A bit clock is supplied from the LL circuit 17 (see FIG. 1), and a pit clock counting operation is performed from the timing when the signal S4 falls to a low level (see FIG. 8B). The count value of the counter 53 becomes a predetermined value.
After a predetermined time period shorter than a block (indicated by T in FIGS. 7E and 8A), a signal S, which falls to a low level, is formed in the decoder 55. The flip-flop 56 is set at the timing when the signal S falls to a low level (see FIG. 8B), and the flip-flop 56
The output of 6, ie, the window signal SS, is set to high level and held as shown in FIG. 7E and FIG. 8A. Therefore, the output of the AND circuit is defined by the synchronization signal detection signal S1 until a low level signal is supplied to the reset input terminal 56a of the flip-flop 56.
AND circuit 58 only when the detection signal S becomes high level.
The output signal S,' (see Figure 8) is set to high level.

Output signals S,' of this AND circuit 58 are taken out from a terminal 59 and supplied to the timing generation circuit 33. As described above, the timing signal S is generated in the timing generation circuit 33, and error detection is performed for the next block.

Further, in the counter circuit 53, the flip-flop 5
A carry is generated at a predetermined timing delayed from the set timing of 6, and at the timing when this carry signal S falls to a low level, the output of the OR circuit 52 is set to a high level, and the counter 53 is reset.

If the error detection circuit 35 determines that the next block does not contain an error, a signal S4 that falls to a low level is generated and operates in the same manner as described above. That is, the erroneous detection of the synchronization signal by the coincidence detection circuit 57 that occurs during the period in which the window signal S is at a low level is invalidated (see FIGS. 8C and 8).

Furthermore, if the error detection circuit 35 determines that the next block contains an error, the signal S4 is held at a high level and the flip-flop 5
The window signal S from 6 is set to high level. Therefore, the output of the AND circuit 58, that is, the detection signal S1 of the synchronization signal from the minus number output circuit 57 is always enabled to be output until the signal S4 is set to low level. In this state, when a synchronization signal is detected and it is determined that the block contains no errors, the normal operation described above is restored.

〔Effect of the invention〕

In this invention, an error detection circuit is provided as a means for determining whether the synchronization signal in one block detected by the synchronization detection circuit is reliable, and the error detection circuit forms a signal indicating the presence or absence of an error for each block. and this signal is supplied to the timing generation circuit. Only when it is determined that no error is included, a window signal is generated in a timing generation circuit that is set to a predetermined period shorter than one block, for example, at a low level, based on the timing of a signal indicating the presence or absence of an error. The signal is supplied to the synchronization detection circuit to control the synchronization detection circuit, and in the period in which the window signal is at a low level, the output of the detection signal of the synchronization signal is prohibited. In addition, if it is determined that an error is included, the wind signal is held at a high level, and the synchronization detection circuit remains in a state where it can output a detection signal of the synchronization signal until a synchronization signal that is estimated to be correct is detected. It is said that

Therefore, according to the present invention, the window signal is locked only when the synchronization signal is detected and it is determined that the block contains no errors, which can cause burst errors. This prevents malfunctions such as the following, and more reliably prevents erroneous detection of synchronization signals caused by errors and the like.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the overall configuration of a rotary head type digital tape recorder to which the present invention can be applied, FIG. 2 is a route map showing the tape format of the digital tape recorder, and FIG. 3 is a diagram showing the digital tape recorder. FIG. 4 is a route map used to explain the error correction code of a digital tape recorder; FIG. 5 is a block diagram showing a partial configuration of an embodiment of the present invention; 6th
The figure is a block diagram showing a partial configuration of a timing generation circuit in an embodiment of the invention, and FIGS. 7 and 8 are time charts used to explain the operation of the embodiment of the invention. Explanation of main symbols in the drawings: 1 Ni drum, 2A, 2B: magnetic head, 3: magnetic tape, 13: recording signal processing circuit, 18: reproduction signal processing circuit, 23: timing control circuit, 32: synchronization detection circuit, 33, 36: Timing generation circuit, 3
4: Demodulation circuit, 35: Error detection circuit. Figure 2 Figure 4 Ar'C1 East edition Figure 6

Claims (1)

[Scope of Claims] A synchronization detection device to which data in which a synchronization signal is added to each block of digital data is input, comprising: a circuit for detecting the synchronization signal; and a circuit that generates a window signal that turns off the detection operation of the synchronization signal for a period shorter than the block and turns on the detection operation until the next detection of the synchronization signal. Detection device.