JP2597989B2 - Data playback device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is applied to, for example, a rotary head type digital tape recorder, and particularly relates to a reproducing apparatus for multiplex-recorded data.

[Summary of the Invention]

The present invention relates to a data reproducing apparatus in which the address and data of each block are encoded so that an error can be detected, and input data including identical data reproduced from a different position on a recording medium a plurality of times is supplied. The data is distributed to a plurality of coincidence detection circuits in accordance with the address determined as having no error as a result of the error detection, and in this coincidence detection circuit, the input data corresponding to the generated coincidence signal is made valid to ensure correct data. The data can be reproduced.

[Conventional technology]

The rotary head type digital tape recorder includes pre-emphasis characteristics of recorded PCM signal, ID signal for identification of sampling frequency, quantization bit number, etc., code for controlling playback operation, time code, etc. Have been. These additional data are not encoded with a strong error correction code such as a PCM signal, but are merely encoded with an error detection code using simple parity. Therefore, the same data is recorded a plurality of times at different positions on the magnetic tape. Conventionally, when processing such multiplex-recorded data, error detection using simple parity is performed, and data having no error is treated as valid data.

[Problems to be solved by the invention]

In a conventional data reproducing apparatus, since data determined to be correct by simple parity is valid, there is a problem that incorrect data is also taken in due to an error in error detection.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a data reproducing apparatus capable of reliably capturing correct data by using multiplex recording more effectively.

[Means for solving the problem]

According to the present invention, first and second subcode blocks each including an identification code and a parity code and a subcode added to the identification code are provided at both ends on an inclined track formed on a magnetic tape. Parity code added to the identification code and
In a data reproducing apparatus for reproducing data from a magnetic tape provided on an inclined track with a PCM block composed of PCM data sandwiched between first and second subcode blocks, demodulation for demodulating data recorded on the inclined track Means, an error detecting means for determining whether or not there is an error in the identification code obtained from the demodulating means;
Means for allocating the PCM block to the first and second sub-code blocks, and comparing the identification codes multiplex-recorded for each unit of the first and second sub-code blocks and the PCM block, which are allocated by the control means. Identification code coincidence detection means, and the identification code coincidence detection means has determined that the identification codes multiplexed and recorded for each of the first and second sub-code blocks and the PCM block are identical. A data reproducing apparatus characterized in that data is determined as valid reproduction data.

[Action]

Different types of data, which are multiplexed and written, are distributed to the plurality of coincidence detection circuits. This distribution is performed using an address signal determined as having no error as a result of the error detection. Therefore, the coincidence detection circuit detects coincidence between data at addresses determined to have no error, and when the coincident data is reproduced, this data is determined to be valid. Even if the detection capability of the error detection code is not so high, the coincidence detection prevents erroneous data from being captured. Also,
Since the coincidence detection is performed between data at addresses determined to have no error, the accuracy of the coincidence detection can be improved. With both of these, it is possible to reliably capture only correct reproduction data.

〔Example〕

An embodiment in which the present invention is applied to a rotary head type digital tape recorder (abbreviated as R DAT) will be described below with reference to the drawings. The description of this embodiment is:
This is done in the following order.

a. Overall configuration of digital tape recorder b. Data configuration of digital tape recorder c. Error correction code of digital tape recorder d. Reproduction signal processing circuit a. Overall configuration of digital tape recorder 1 shows the overall configuration of a digital tape recorder, so-called RDAT. 1 is 200 with a diameter of 30mm
The drum is rotated at 0 rpm. A pair of magnetic heads 2A and 2B are attached to the drum 1 at an angular interval of 180 °. A magnetic tape 3 (indicated by a dashed line) is wound obliquely around the peripheral surface of the drum 1 at a winding angle of 90 °. The magnetic tape 3 is wound between the reel hubs 4A and 4B of the tape cassette, and is run by the capstan 5 and the pinch roller 6 at a speed of 8.15 (mm / sec).

When the magnetic heads 2A and 2B alternately slide on the magnetic tape 3, tracks 7A and 7B which are inclined are formed on the magnetic tape 3 as shown in FIG. The tape width A of the magnetic tape 3 is 3.81 mm. The magnetic gap of one rotating head 2A is inclined by + α with respect to the direction orthogonal to the track, and the magnetic gap of the other rotating head 2B is inclined by -α with respect to the direction orthogonal to the track. (Α = 20
°). The angles of the magnetic gaps of the magnetic heads 2A and 2B are called + azimuth and -azimuth, respectively.

The magnetic heads 2A and 2B are alternately selected by a head changeover switch 8, and a recording signal from a terminal r of a recording / reproducing switch 9 is supplied to the magnetic heads 2A and 2B via a rotary transformer (not shown). Reproduction signals from the heads 2A and 2B are recorded / reproduced via a rotary transformer (not shown).
The signal is taken out to the terminal p of the reproduction switch 9.

An analog audio signal from an input terminal 10 is supplied to an A / D converter 12 via a low-pass filter 11, and is converted into a digital audio signal by (sampling frequency: 48 KHz, 16-bit linear quantization). The digital audio signal from the A / D converter 12 is supplied to the recording signal processing circuit 13. The recording signal processing circuit 13 performs error correction coding of the digital audio signal and conversion of the recording data into a format as described later. in this case,
An ID signal (PCM-ID) for identifying on / off of pre-emphasis of a signal to be recorded, a sampling frequency, the number of quantization bits, and the like is added. A subcode such as a program number and a time code of a signal to be recorded and an ID signal (subcode ID) for the subcode are formed by a subcode encoder (not shown). Supplied to 13.

The recording signal processing circuit 13 generates serial recording data for each track in synchronization with the rotation of the magnetic heads 2A and 2B. The recording data is supplied to the head changeover switch 8 through the recording amplifier 15 and the terminal r of the recording / reproduction switch 9.
Supplied to The recording data is alternately supplied to the magnetic heads 2A and 2B by the head changeover switch 8.

The signals reproduced by the magnetic heads 2A and 2B are supplied to a reproduction amplifier 16 through a head changeover switch 8 and a terminal p of a recording / reproduction switch 9. The output signal of the reproduction amplifier 16 is supplied to the PLL 17, and the PLL 17 extracts a clock synchronized with the reproduction signal. The reproduction signal is subjected to processing such as error correction and interpolation in a reproduction signal processing circuit 18, and the reproduction digital audio signal is supplied to a D / A converter 19. The reproduced audio signal from the D / A converter 19 is taken out to the output terminal 21 via the low-pass filter 20.
At the same time, in the reproduction signal processing circuit 18, the subcode and the subcode ID are separated and taken out to the output terminal 22.
A sub-code decoder is connected to the output terminal 22, and control data and the like are formed from the sub-code.

A control signal for controlling the head changeover switch 8 and the recording / reproduction changeover switch 9 is formed by the timing control circuit 23. Also, the timing control circuit 23
Generates a clock signal and a timing signal required by the recording signal processing circuit 13 and the reproduction signal processing circuit 18, respectively.

b. Data structure of digital tape recorder The entire data recorded on one track is called one segment. FIG. 3A shows the structure of one segment of data recorded by one of the rotary heads. When the unit amount of the recording data is one block, one segment includes 196 blocks (7500 μsec) of data.
A margin (11 blocks) is provided at each of both ends of one segment corresponding to the end of the track. Subcode 1 and subcode 2 are recorded adjacent to each of the margins. These two subcodes are the same data, and are double-recorded. The subcode is a program number and a time code. A run-in section (2 blocks) and a post-amble section (1 block) of the PLL are arranged on both sides of the recording area of 8 blocks of the subcode.

In addition, an inter block gap in which data is not recorded is provided, and a pilot signal for ATF is recorded over five blocks between three inter block gaps. The PCM signal that has been subjected to the recording process is recorded in an area having a length of 128 blocks excluding the run-in section of the two-block PLL in an area having a length of 130 blocks at the center of one segment. This PCM signal is
This is data corresponding to the audio signal during the time when the rotary head makes a half turn.

The PCM signal includes a 2-channel stereo PCM signal including an L (left) channel and an R (right) channel, and parity data of an error detection / correction code. One segment shown in FIG. 3A is recorded / recorded by the magnetic head 2A.
For playback, the left half of the PCM signal recording area
Data Le is recorded, and data Ro is recorded in the right half thereof. The data Le is composed of even-numbered data of the L channel and parity data relating to this data, and the data Ro is composed of odd-numbered data of the R channel and parity data relating to this data. Odd and even numbers are the order counted from the beginning of the interleaved block.

One segment of data is recorded on a track formed by the other magnetic head in the same configuration as that of the above-described one track. The data section in the data of one segment of the other track has a data Re in the left half thereof.
Is recorded, and data Lo is recorded in the right half thereof.
The data Re is composed of even-numbered data of the R channel and parity data relating to the data. Data Lo
Consists of odd-numbered data of the L channel and parity data related to this data. As described above, the even-numbered data and the odd-numbered data of each channel are separately recorded on two adjacent tracks, and the data of the L channel and the R channel are recorded on the same track. This is to prevent erroneous continuous data of the same channel.

FIG. 3B shows the data configuration of one block of the PCM signal. An 8-bit (1 symbol) block synchronization signal is added to the beginning of one block, and then an 8-bit PCM-ID is added. After the PCM-ID, a block address is added. This PCM-ID and two symbols of the block address (W1
And W2), a process of error correction coding of simple parity is performed, and 8-bit parity is added next to the block address. As shown in FIG. 3D, the block address is composed of 7 bits excluding the most significant bit (MSB). When the most significant bit is set to “0”, it indicates that the block is a PCM block.

The 7-bit block address changes sequentially from (00) to (7F) (in hexadecimal). The PCM-ID in which the lower three bits of the block address are recorded in each block of (000) (010) (100) (110) is defined. In each block address where the lower three bits of the block address are (001) (011) (101) (111), an optional code of PCM-ID can be recorded. In PCM-ID, each of ID1 ~ I of 2 bits
D8 and 4-bit frame address are included. ID1 to ID7
Defines frame identification information. A pack is composed of 32 ID8s. For example, ID1 is a format ID, audio or other use is identified by ID1, ID2 identifies pre-emphasis on / off and pre-emphasis characteristics, and ID3 identifies a sampling frequency. . The above-mentioned ID1 to ID7 and the frame address are the same data in the segment of the interleave pair.

FIG. 3C shows the data structure of one block of the subcode. It has the same data configuration as the PCM block described above. As shown in FIG. 3E, the most significant bit of the symbol W2 of the sub-code block is set to "1", indicating that it is a sub-code block. The lower 4 bits of the symbol W2 are used as a block address, and the 8 bits of the symbol W1 and 3 bits excluding the MSB and the block address in the symbol W2 are used as a subcode ID. For the two symbols (W1 and W2) of the sub-code block, simple parity error correction coding is performed, and 8-bit parity is added.

The subcode ID is recorded in the even number (the LSB of the block address (least significant bit is “0”) and the odd number (the LSB of the block address is “1”) in the block address. The subcode ID includes a control ID for specifying a reproduction method, a time code, etc. The subcode data is an error correction code based on a Reed-Solomon code like PCM data. Being processed.

c. Error Correction Code of Digital Tape Recorder Error detection / correction code processing is performed for each of 128 blocks of data recorded in one segment. FIG. 4A shows a code configuration of data recorded by one magnetic head 2A, and FIG. 4B shows a code configuration of data recorded by the other magnetic head 2B. The number of quantization bits is
The 16-bit PCM signal is divided into upper 8 bits and lower 8 bits, and the error detection / correction code is encoded using 8 bits as one symbol.

Data of (128 × 32 = 4096 symbols) is recorded in one segment. As shown in FIG. 4A, (L0, L2,.
··· L1438) The two-dimensional array of data consisting of even-numbered data Le of the L channel consisting of symbols and (R1, R3,... R1439) odd-numbered data Ro of the R channel is vertically and horizontally arranged. Error detection code for each direction
The coding of C1 and the error correction code C2 is performed. The C1 code using the (32,28,5) Reed-Solomon code is applied to the 28 symbols in the vertical direction. The parity data P of four symbols of the C1 code is arranged at the last position of the two-dimensional array. Further, the C2 code using the (32, 26, 7) Reed-Solomon code is encoded for 52 symbols in the horizontal direction. The C2 code is applied to 26 symbols of every two symbols of 52 symbols, and parity data Q including six symbols is generated for one code sequence. Parity data Q consisting of a total of 12 symbols of the C2 code is arranged at the center of the two-dimensional array. The same applies to the other 52 PCM data symbols located in the horizontal direction.
Two codes are encoded, and the parity data Q is arranged at the center.

The code configuration shown in FIG. 4B replaces the even-numbered PCM signal of the L channel in the code configuration of FIG. 4A with the even-numbered PCM signal of the R channel (R0, R2,... R1438). , R-channel odd-numbered PCM signals are replaced by L-channel odd-numbered PCM signals (L1, L3,..., L1439).

As shown in FIG. 3B, one PCM block is formed by adding a synchronization signal, a PCM-ID, a block address, and a parity to 32 symbols arranged in the vertical direction in these code configurations. You.

d. Reproduction signal processing circuit The present invention is applied to reproduction of PCM-ID in the reproduction signal processing circuit 18 of the above-mentioned rotary head type digital tape recorder. FIG. 5 shows a configuration of the reproduction signal processing circuit 18, and a reproduction signal is supplied to an input terminal indicated by 31.

The reproduced signal is supplied to a demodulation circuit 32, where 10 bits per symbol are demodulated into 8 bits per symbol. Magnetic tape 3
When recording on a digital signal, 8 bits of one symbol are subjected to a digital modulation process which is converted into a preferable pattern of 10 bits in order to reduce low frequency components as much as possible. The reproduction data from the demodulation circuit 32 is supplied to the data bus 35 for each symbol via the data register 33 and the buffer 34.

The data bus 35 is connected with a buffer RAM 36 and an error correction circuit 37. Data bus 35 to buffer RAM3
The reproduced data is taken into 6 and the data stored in the buffer RAM 36 is read and read by the error correction circuit 37.
An error correction process is performed by the Solomon code. The error-corrected PCM signal is supplied to an interpolation circuit 38, where an uncorrectable error is interpolated, and a reproduction PCM signal is extracted from an output terminal 39. This reproduced PCM signal is supplied to a D / A converter 19 (see FIG. 1). The subcode is subjected to processing such as error correction by a subcode decoder (not shown), and is taken out to a subcode output terminal.

The PCM-ID (W1), block address (W2), and parity obtained from the demodulation circuit 32 are supplied to the error detection circuit 40, and the error detection circuit 40 performs error detection using simple parity. The error detection circuit 40 generates an error pulse indicating the presence or absence of an error. This error pulse becomes “1” when there is an error, and becomes “0” when there is no error. The error pulse is supplied to the ID match detection circuit 41. As will be described later, the ID coincidence detection circuit 41 performs the PCM-ID overwriting using the block address (W2).
Is performed. The request controller signal generated in the ID match detection circuit 41 is a request signal generation circuit.
Supplied to 42.

The request signal generation circuit 42 is supplied with the write request signal from the demodulation circuit 32 and generates an ID request signal. This ID request signal is supplied to the request controller 43. Another request signal such as a request signal for error correction is supplied to the request controller 43, and a buffer control signal generated from the request controller 43 is supplied to the buffer 34. When the buffer control signal is “0”, the buffer becomes active and the PCM-ID is written to the buffer RAM via the data bus.

As shown in FIG. 6, the ID match detection circuit 41
It is constituted by the number of coincidence detection circuits 51, 52, 53, 54.
The match detection circuit 51 is connected to the registers 55 and 56 of one symbol and EX.
-OR gate (exclusive OR gate) 57
The EX-OR gate 57 detects whether the contents of the register 55 match all the bits of the contents of the register 56. When the symbols stored in both the register 55 and the register 56 match, the output of the EX-OR gate 57 becomes "0". The capture of data from the input terminal 61 to the register 55 and the register 56 is performed by an enable pulse generated from the controller 58.

The other match detection circuits 52, 53, and 54 are the match detection circuit 51 described above.
It has the same configuration as An enable pulse generated in the controller 58 is supplied to each of the coincidence detection circuits 52, 53, 54. The detection output signals of the four coincidence detection circuits 51, 52, 53, 54 are supplied to a control signal generation circuit 62, and a request control signal formed by the control signal generation circuit 62 is obtained at an output terminal 63. This request control signal is supplied to the request signal generation circuit 42 as described above. Control signal generation circuit 62
Detects that the respective detection output signals of the coincidence detection circuits 51, 52, 53, 54 have become "0" first, and holds the request control signal at "0".

The enable pulse supplied to the coincidence detection circuits 51, 52, 53, 54 is generated from the block address from the terminal 59 and the error pulse from the terminal 60. That is, the error detection circuit 40 determines that there is no error, and the data is taken into the register of the coincidence detection circuit corresponding to the block address (W2) in which the error pulse is “0”.

FIG. 7 shows a data configuration in which a plurality of continuous PCM blocks are arranged in the vertical direction. PCM-ID (W1) is 8
Multiple writing is performed in the cycle of the block. Therefore, the same PCM-ID is recorded (128/8 = 16) times in one segment. However, in PCM-ID (A, B, C, D) (hexadecimal)
Are the standardized ID signals, and eight symbols (E, F, G, H, I, J, K, L) (in hexadecimal) are optional. Code. Since it is not specified that the optional code is overwritten, the ID coincidence detecting circuit 41 is used for reproducing four standardized symbols.

The block address (W2) is from (00) to (7F)
The ID signal and the optional code can be distinguished by the lower three bits of the block address. The control 58 of the ID match detection circuit 41 is a PCM-ID when the lower 3 bits of the block address are (000).
The enable pulse for taking (A) into the match detection circuit 51, the enable pulse for taking PCM-ID (B) when it is (010) into the match detection circuit 52, and this (100)
An enable pulse for capturing the PCM-ID (C) at the time of (1) into the match detection circuit 53 and an enable pulse for capturing the PCM-ID (D) at the time of (110) in the match detection circuit 54 are generated. Therefore, by each of the coincidence detection circuits 51, 52, 53, 54,
The four PCM-IDs are separately matched.

FIG. 8A shows the timing of the block synchronization synchronized with the reproduction signal, and FIG. 8B shows the timing of the write request signal from the demodulation circuit 32. This write request signal includes PCM-ID (W1) and data d ₀ , d ₁ ,
Generated corresponding to each symbol of the ··· d _31. This write request signal is controlled by a request control signal (FIG. 8C) from the ID match detection circuit 41,
This is a request signal. As shown in FIG. 8C, when the request control signal is “1”, the PCM-ID (W
The write request corresponding to 1) is invalidated, and generation of the ID request signal is prohibited. The request control signal becomes “1” in the ID match detection circuit 41.
This is a case where the coincidence of the multiple-written PCM-ID is not detected. If no error was detected in error detection
The PCM-ID and the block address are reproduced twice, and if they match, the request control signal shown in FIG. 8C becomes "0" and an ID request signal is generated. The PCM-ID for which the ID request signal is “0” is written to the buffer RAM 36 via the data bus 35.

In FIG. 8C, the request control signal corresponding to the optional code is always set to "0", and the optional code is always written in the buffer RAM 36.

The above description is of the case where the present invention is applied to the reproduction of PCM-ID, but the present invention can also be applied to the reproduction of sub-codes which are multiplex-written. The subcode is 1
The same data for every two blocks is repeatedly recorded in each of the subcode 1 and the subcode 2 (see FIG. 3A) in the segment. Further, the present invention can be applied to the case of reproducing multiplex-written data other than the digital tape recorder.

〔The invention's effect〕

According to the present invention, the data determined to be correct as a result of the error detection, and the data for which the coincidence is detected are determined to be valid reproduced data. The correct data can be taken into the computer.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the overall configuration of a rotary head type digital tape recorder to which the present invention can be applied, and FIG. 2 is a schematic diagram showing a tape format of the digital tape recorder. FIG. 3 is a schematic diagram used to describe the track format and block format of the digital tape recorder, FIG. 4 is a schematic diagram used to describe the error correction code of the digital tape recorder, and FIG. 5 is an embodiment of the present invention. A block diagram of the main part of the example, FIG.
FIG. 7 is a block diagram of an ID match detection circuit, FIG. 7 is a schematic diagram showing a time series of a PCM block, and FIG. 8 is a time chart used for explaining the operation of one embodiment of the present invention. Explanation of main reference numerals in the drawings 1: drum, 2A, 2B: magnetic head, 3: magnetic tape, 13: recording signal processing circuit, 18: reproduction signal processing circuit, 32: demodulation circuit, 3
4: Buffer, 35: Data bus, 36: Buffer RAM, 40: Error detection circuit, 41: ID match detection circuit, 42: Request signal generation circuit, 51, 52, 53, 54: Match detection circuit, 58: Controller, 62: Control signal generation circuit.

Continuation of the front page (72) Inventor Kentaro Odaka 6-7-35 Kita-Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation (56) References JP-A-57-73577 (JP, A) JP-A-57-53802 (JP, A)

Claims (1)

(57) [Claims] A first sub-code block comprising an identification code, a parity code added to the identification code, and a sub-code, provided at both ends of an inclined track formed on a magnetic tape; Data for reproducing data from a magnetic tape provided on the inclined track with a PCM block including an identification code, the parity code added to the identification code and PCM data sandwiched between the first and second subcode blocks. In the reproducing apparatus, demodulating means for demodulating data recorded on the inclined track, error detecting means for determining whether or not the identification code obtained from the demodulating means has an error, and no error by the error detecting means Means for allocating the first and second subcode blocks and the PCM block, The first and second sources, which are distributed by the control means,
And an identification code coincidence detecting means for comparing identification codes multiplexed and recorded for each unit of the PCM block. The first and second subcodes are detected by the identification code coincidence detecting means. A data reproducing apparatus characterized in that data determined to be identical in identification codes multiplexed and recorded in units of a block and the PCM block is determined as valid reproduced data.