JPS6025066A - Pcm reproducing device - Google Patents

Abstract

PURPOSE:To use only on CRC checking circuit and reduce the circuit scale of a PCM reproducing device by placing the CRC checking circuit on the output side of a memory, and employing parallel input constitution for the CRC checking circuit. CONSTITUTION:A signal read out of each track is inputted to an input circuit provided to each track. Data written in the memory 17 temporarily is transferred, byte by byte, to a main memory by an MPX6 at specific timing. The CRC circuit 30 connected to a bus line receives the data, byte by byte, during the transfer and performs CRC arithmetic to detect an error. A 16-bit register after being set to an initial value inputs a specific number of bytes and then checks on whether or not an error occurs to data sent afte an OR circuit checks on whether the value of each register is all''O'' or not. consequently, this device is able to operate eight times as fast as a conventional circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a PCM playback device for digital audio tape that records and plays back signals on a plurality of tracks.

[Background of the invention]

FIG. 1 shows the configuration of a conventionally proposed multihead PCM decoder. FIG. 2 shows the detailed configuration of the decoder. FIG. 3 shows the recording pattern on the tape.

In FIG. 1, 1 is a tape, 2 is a magnetic head, 6 is a reproduction amplifier, 4 is a decoder circuit, 5 is an input circuit including bit synchronization, frame synchronization, error detection and buffer memory,
6 is a memory, an MPX for switching memory output, and 7 is a main memory error correction unit that stores data from the buffer memory.

〃This is a circuit that performs A. FIG. 2 shows a more detailed explanation of the input circuit 4, in which 10 is a frame synchronization circuit;
1 is a bit synchronization circuit, 12 is a reference oscillation circuit, 13 is a code demodulation circuit, and 15 is a latch circuit.

16 is a CRC check circuit, 17 is a memory, and 18 is a memory address circuit.

I will now explain this operation. multitrack pcm
The recorder records signals on each of n tracks as shown in FIG. At this time, synchronization signals are inserted at regular intervals. One frame of data consists of a synchronization signal, data, and a CRC code that checks for errors in the transmitted data.

During playback, signals for each trunk are read out by n magnetic heads 2 corresponding to each track and then input to the encoder circuit 4. Here, the encoder circuit 4 synchronizes the input signals for each trunk with the bit synchronization circuit 11, and then extracts the synchronization signal of the input signal string with the frame synchronization circuit 10 to achieve frame synchronization.

Based on this synchronization signal, the modulated signal is sent to the code demodulator 1.
3 to demodulate. The demodulated signal is once latched by the latch circuit 15 and then written to the memory 17. On the other hand, this signal is serially input to the CRC check circuit 16 to check whether the data written in the memory 17 is correct.

Generator polynomial x16+x12+ of CRC-CCiTT standard
The x5+1 C'RC check circuit is shown in FIG. 2o
is a 5-bit shift register, 21 is a 7-bit register, 22 is a 4-bit register, 23, 2.4, and 25 are Ex-OR circuits, and 26 is an OR circuit. For error detection, input one bit at a time from input iN, and when all data is input, the value of each register is att '0'', that is, x
``+x12+:t5+'' Errors are detected based on whether it is divisible by i.

For details about CRC code, see CRC check ICEC8
5059 manual, etc.

The data once stored in the memory 17 is sent to the error correction circuit 7 together with the result of the CRC check circuit at the timing selected by the MPX 6, and after de-interleaving and error correction are performed, it is output to the D/A.

Figure 5 shows the Read/ll'rite of memory 17.
(7) Indicate timing. Data is stored in memory 17 using the synchronization signal extracted from the input signal string as a start signal.
write to. Once written data is checked by the CRC, and then sequentially selected by the MPX 6 starting from the first track. Until the next Sync signal arrives, the data written in the memory 17 for 72 times is sent to the memory on the correction circuit side. Since the readout time is short compared to the readout time, data is generally transferred to the correction circuit in multiple bits (for example, 1 byte, 411th position).

The conventional example described above has the drawback that the CRC circuit is required for each track, increasing the circuit scale. Also, conventional C
The RC check circuit has a serial input, so if you want to perform CRC check when reading memory, you will need a parallel-to-serial conversion circuit, and since the data read is fast, the CRC check circuit must operate at high speed. was there.

[Purpose of the invention]

It is an object of the present invention to eliminate the drawbacks of the prior art and to provide a multi-head PcM decoder with a reduced circuit configuration.
Our objective is to provide a CM playback device.

[Summary of the invention]

In the present invention, by placing the CRC check circuit on the output side of the memory and configuring the CRC check circuit in parallel, the number of CRC check circuits is reduced to one, whereas in the conventional example, the number of CRC check circuits is required for each track. The circuit scale is reduced as follows.

[Embodiments of the invention]

FIG. 6 shows the configuration of a multi-head PCM Tecoder according to the present invention. The same symbols as in FIG. 2 have the same functions. 30
performs CRC check in parallel for each byte.
It is an RC circuit. FIG. 7 shows the configuration of the CRC cheek circuit 30.

The operation will be explained below. The signals read from each track are input to an input circuit 5 provided for each track. Here, the input circuit 5 operates in the same manner as described in the conventional example. However, a CRC check is not performed. The data once written to the memory 17 is transferred byte by byte from the MPX 6 FC to the main memory at a predetermined timing. During this transfer, the CR connected to the path line
The C circuit 30 receives data in bytes, performs a CRC operation, and performs error detection. The CRC byte calculation circuit is shown in FIG. 7, and the procedure for deriving the logical configuration of the CRC byte calculation circuit is shown in FIG.

The CRC byte operation will be explained below.

Figure 8 shows the CRC-CCiTT standard (generator polynomial, 1g+
This describes the changes in each register of the 080 circuit (x+z+, s+i). The value of each register before data is input! ,,,T2..."+4,
This table shows the changes in each register when data D, D2, . . . D8 are input one bit at a time. 1st bit is x
, -+ x, (j') x, ■D4■D8, 2nd bit x2→X. ■"14■〃30nD,・
...changes. (■ indicates Ex -OR.) FIG. 7 shows this logical formula replaced by a circuit. For the 16-bit registers, after setting the initial value and inputting the predetermined number of bytes, the OR circuit checks whether the values of each register are a, tl, and D to check whether there are any errors in the sent data. It is something. According to the circuit described above, it is possible to operate at eight times the speed of the conventional serial input CRC check circuit.

FIG. 9 shows the configuration of a 4-bit parallel input CRC check circuit. The configuration of this logic circuit can be seen from the logic equation of the 4th bit among the changes in each register shown in FIG.

FIG. 10 shows logical expressions for each register value of a 16-bit parallel input CRC check circuit. Here, 21～”
+6 is the initial value of the register, and D, to D, and 6 are data that are sequentially input during serial processing.

As is clear from the above description, any n-pit parallel input CRC check circuit can be easily constructed from the logical expression of each register value when n-bit data is serially input.

FIG. 11 explains processing when the data bit length is not an integral multiple of the number of CRC parallel input hit inputs. In a 080 circuit with 8-bit parallel input, the data bit length is 212 bits (4+8×26), leaving 4 bits. As a result, the first input data is A1-A4.
D, ~D Input as 408 bits. Generally, the register of the 080 circuit is initially set as Qtt O or (ltt"1 busy, but when αtl' is 00, it is A. If ~A4=0, according to the logical formula in Figure 8, ~A4 is involved in the CRC calculation. However, when Qul is set, regardless of the value of A1-A4, the data of A1-A4 will also be CR.
Perform C calculation. A added to prevent this, ~A4
When the data is σttO and the register is set to the value shown in Figure 10 (10000111000111), each register of the CRC becomes au-'''1'' when the A1 to A4 data is input, and the initial state 1 is set. It will be the same as time. The CRC calculation will be started from the data of D1 to D4. In the embodiment, an explanation has been given of the case where 4-bit additional data is added, but other examples can be easily realized by setting the initial value from the logical expression of FIG. 8 or FIG. 10.

As shown in FIG. 6, by connecting the parallel input cRc circuit 30 to the output side of the MPX 6, the data of each track is stored in the memory 17 and then sequentially
It is selected by PX6 and the data is output on the hash line. Cheeking can be performed using the 080 circuit connected in parallel to this bus line. This makes it possible to reduce the number of CRC diodes, which conventionally required the number of tracks, to one.

〔Effect of the invention〕

According to the present invention, a system configuration yg of a multi-head decoder that conventionally required a CRC circuit corresponding to the number of tracks,
It has become possible to realize a simple system configuration in which the number of CRC circuits is reduced to one.

[Brief explanation of the drawing]

1 and 2 are configuration diagrams of a conventional multi-head PCM encoder, FIG. 5 is a tape recording pattern diagram, and FIG. 4 is a CRC circuit diagram for serial processing. FIG. 5 is a timing diagram of a conventional encoder, FIG. 6 is a configuration diagram of an encoder according to the present invention, FIG. 7 is a CRC circuit diagram of a parallel configuration, FIG. 8 is a diagram showing logical formulas, and FIG. FIG. 11 is a diagram showing one frame configuration, and FIG. 12 is a diagram showing initial value set values. 1. Tape. 2...Magnetic head. 3...Reproduction amplifier. 4...Decoder circuit. 5...Input circuit. 6...MPX. 17...Memory. 20, 21, 22...shift register. 23, 24, 25---E2-OR. 60..., CRC circuit. 1st Fig. 416 No. Zkon/θ No. 3 Zutsukuri 4 Fig. 5 no.

Claims (1)

[Claims] 1. A PCM signal consisting of a CRC signal consisting of m bits to bits is recorded on a plurality of tracks on a tape, and the synchronization signal is used as the basis for playback. The Data signal and the CRC signal are reproduced, and an error occurring in the Data signal is detected using the CRC signal.
A PCM playback device that corrects errors and outputs signals using a signal is provided with a register consisting of P bits and an Ex-OR circuit that receives the output of the register as input, and performs the Ex-OR circuit.
The output of the circuit is input to the register, and the Data signal consisting of n bits and the CRC signal consisting of P bits are input to the Ex-OR circuit at the 41st position with q bits (q≧2), and the q bit parallel input 1. A PCM playback device comprising a CRC check circuit for checking the signals of the plurality of tracks for errors. 2. In claim 1, after the signals of the plurality of tracks are once stored in the memory. A PCM playback device characterized in that a signal read out in units of q bits from the memory is input to the CRC check circuit to perform an error check on the signal of each track.