JPH0770160B2 - Synchronous circuit - Google Patents

Description

The present invention relates to a PCM signal recording apparatus, and more particularly to a synchronizing circuit suitable for a rotary head PCM recorder.

[Conventional technology]

The conventional device divides the input data into fixed time units called frames and compresses the data in one frame on the time axis like the PCM data recording device described in JP-A-58-188314. , Was recorded on a magnetic tape using a rotary head. The data at the beginning of the frame is the L channel (left) data.

[Problems to be solved by the invention]

The above conventional apparatus does not synchronize the frames when directly recording the PCM data input from the outside, and the frames of the input data and the frames of the data recorded on the tape are asynchronous.

An object of the present invention is to provide a synchronizing circuit for recording PCM data by performing frame synchronization with a frame synchronizing signal included in an input signal or a frame signal input from the outside.

[Means for solving problems]

The purpose of the above is to synchronize the timing generation circuit at the position of the head data of the frame when the frame sync signal indicating the beginning of the frame exists in the input signal, and to the input signal when the frame sync signal does not exist in the input signal. This is achieved by synchronizing the timing generation circuit in word units from the external identification signal added in word units.

[Action]

When the frame sync signal does not exist in the input signal, the sync signal generation circuit generates the sync signal in the channel cycle, so that the clear signal is generated only when the data of either channel is input, and the first data of the frame Can always be synchronized with the data of one channel. When the timing generation circuit generates the timing for one frame, it enters the synchronization signal waiting state, the clear signal is generated by the first synchronization signal in this state, and the timing generation circuit resets the frame.

If a frame sync signal is present in the input signal,
Frame synchronization can be performed by generating a signal in synchronization with the frame synchronization signal by the synchronization signal generation circuit.

If there is no frame sync signal in the input signal,
By using the frame signal selection circuit to put the clear signal generation circuit in a synchronization waiting state by an external frame signal, frame synchronization with the external frame signal can be performed.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. This figure is a block diagram of a rotary head PCM recorder. In the figure, 1 is an extraction circuit that extracts a frame synchronization signal from input data, 2 is a synchronization signal generation circuit that generates a synchronization signal, 4 is a timing generation circuit that controls the operation timing of each part, and 3 is a timing generation circuit 4. A clear signal generating circuit for initializing, 5 is a frame signal selecting circuit for selecting a frame signal, and 8 is extracted by the extracting circuit 1.
RAM for temporarily storing the PCM signal, 6 for an address generation circuit for controlling the address of RAM 8, 9 for a write control circuit for sending a write command to RAM 8, and 7 for adding error correction parity to the data stored in RAM 8. Encoding circuit, 10 is RAM8
A modulation circuit that modulates the data of 11, a recording circuit including a recording amplifier, 12 is a magnetic tape, 13 is a rotating cylinder, and 1
4,15 are heads.

Further, 16 is a data input terminal, 17 is an external frame signal input terminal, and 18 is a frame signal selection input terminal.

First, the recording operation of the rotary head PCM recorder will be described.

The extraction circuit 1 extracts the PCM signal 20 in the input data 19 input from the data input terminal 16 and writes it in the RAM 8.
Next, the PCM signal is read from the RAM 8 to the encoding circuit 7, an error correction parity is generated, and the parity is written to the RAM 8. The parity and the PCM signal are read again from the RAM 8, modulated by the modulation circuit 10, amplified by the recording circuit 11, and recorded on the magnetic tape 12 using the heads 14 and 15.

The input data 19 input from the data input terminal 16 is the second
It follows the format shown. One subframe is composed of 32 bits, and the subframe is 4-bit SYNC.
40,8-bit auxiliary data 41,16-bit PCM data 42 (1 sample data of audio signal), 1-bit flag
43,1 bit frame sync 44,1 bit status indicator 45,1 bit parity 46.

The SYNC 40 indicates the beginning of a subframe and specifies the channel (left or right) of PCM data.

The auxiliary data 41 is data for adding auxiliary information to the PCM data 42 and is data such as a subcode in the DAT.

The flag 43 indicates the validity of the PCM data 42 and is used as an option.

The frame sync 44 includes the frame sync signal 2 and the presence or absence of the frame sync signal 22 is designated by the status display 45.

The status display 45 forms one set of information in 192 subframes, and specifies the presence or absence of the frame synchronization signal 22, the sampling frequency, the number of channels, and the like.

Parity 46 is the exclusive OR of 32-bit data in one subframe.

In the actual transfer, bi-phase modulation is applied, and it is necessary to demodulate this.

The extraction circuit 1 extracts the master clock 29 from the input signal 19 and operates the timing generation circuit 4. Further, bi-phase demodulation is applied to extract the PCM data 42 and send it to the RAM 8. In addition, the SYNC 40 determines the channel and outputs the channel selection signal 21 and the frame synchronization 44 the frame synchronization signal 22 to the synchronization signal generation circuit 2.

Frame sync signal 22, channel selection signal 21, PCM data 2
The timing of 0 is shown in FIG. In the figure, L _n-1 , L _n , L
₀ …… is the data of L channel (left), R _n-1 , R _n , R ₀ ……
Indicates the data of the R channel (right).

The channel selection signal 21 is synchronized with the PCM data 42, and L
The channel data is low level, the R channel data is high level, and the frame synchronization signal 22 is
It is a signal that goes low only when it is L ₀ data.
Further, the relationship with the timing generation circuit 4 is such that the internal frame signal 25 is synchronized such that it falls at the start of the L ₀ data.

On the other hand, when the frame synchronization signal 22 does not exist in the input data 19, it is necessary to synchronize the falling edge of the internal frame signal 25 with the falling edge of the channel selection signal 21.

A circuit diagram of the clear signal generation circuit 3 and the frame signal selection circuit 5 is shown in FIG. In the figure, 50 is a latch circuit with a set, 51 is a selection circuit, 52 is an edge detection circuit, 53 is an AND,
54 is OR. The latch circuit 50 operates at the falling clock and the set signal is set at the high level.

The operation of FIG. 4 will be described below with reference to FIGS.

FIG. 5 shows the case where the frame synchronizing signal 22 (FIGS. 1 and 5) is present in the input data 19 of the extracting circuit 1 in FIG. 1, and in this case, the synchronizing signal generating circuit 2 (first (Figure)
Outputs the sync signal 23 such that it becomes high level before and after the falling edge 73 of the frame sync signal 23. First, the internal frame signal from the timing generation circuit 4 (FIG. 4)
Edge detection circuit 52 when 25 falls at timing 70
Outputs a signal 61 so that it becomes high level at timing 71. From the frame signal selection input terminal 18, select circuit 51
By inputting the frame selection signal 28 so that the signal 61 selects the signal 61, the latch circuit 50 is set and the output signal 62 becomes high level. Next, when the falling edge 73 of the synchronizing signal 23 is input, the output signal 62 is at the high level, so the signal passes through the AND53 as it is, and the falling edge 73 of the synchronizing signal 23 causes the latch circuit 50 to be latched at the low level, and the signal 62 becomes the low level. Becomes As a result, the clear signal 24 which is the output of OR54 becomes as shown in the figure. Timing generation circuit 4 uses a clear signal
When 24 is at high level, the initialization is performed so that it becomes the timing of the beginning of the frame. Therefore, the synchronization is performed so that the falling edge of the frame synchronization signal 22 is at the beginning of the frame. After this, when the time for one frame elapses, the cycle of the frame synchronization signal 22 and the cycle of the timing generation circuit 4 are equal (the timing generation circuit 4 operates by the master clock 29 extracted by the extraction circuit 1). Therefore, the input timing of the synchronization signal 23 and the timing of the falling edge detection signal 61 of the internal frame signal 25 match, and the falling edge 78 of the channel selection signal 21
Then, the timing generation circuit 4 is initialized, and thereafter this timing is maintained. As described above, the frame synchronization can be performed from the input data 19.

FIG. 6 shows the timing when there is no frame synchronization signal 22. In this case, the synchronization signal generation circuit 2 outputs the synchronization signal 23 at every falling edge of the channel selection signal 21. However, the latch circuit 50 operates in the same manner as at the timing shown in FIG. 5, and becomes high level only after the falling of the internal frame signal 25 until the falling of the synchronizing signal 23 (waiting state for synchronizing signal). . Therefore, the output signal 63 of the AND53 becomes high level only at the timings (one frame interval) indicated by 110 and 111 in FIG. 6, and once the synchronization is applied at any one of the falling edges of the channel selection signal 21, The operation is similar to the case of FIG. In this way, the fall of the channel selection signal 21 and the beginning of the frame can be synchronized.

Similarly, when there is no frame synchronization signal 22, the beginning of the frame can be defined by inputting the external frame signal 26 having the same frame cycle as the timing generation circuit 4 from the external frame signal input terminal 17. . The timing in this case is shown in FIG.

In this case, the selection circuit 51 outputs the frame selection signal 28.
By inputting to select 60, the latch circuit 50
The set signal 27 becomes high level when the falling edge detection signal 60 of the external frame signal 26 becomes high level, and the synchronization signal waiting state is the output signal 62 of the latch circuit 5 of FIG. The high level 82 in FIG. 7 indicates that the timing generation circuit 4 is initialized at the clear timing 92. In addition, the synchronization signal waiting state is high level 86 when the time for one frame has passed, and the clear timing is
It becomes 91, and thereafter this timing relationship is maintained. As described above, the head of the frame can be synchronized with the external frame signal within the delay time of one cycle of the channel selection signal 21.

In the above case, when the external frame signal 26 and the channel selection signal 21 are asynchronous, the external frame signal 26
If the trailing edge of is close to the trailing edge of the channel selection signal 21 and has jitter or the like, there is a risk that the clear timing may be advanced or delayed by one cycle of the channel selection signal 21.

FIG. 8 is a circuit diagram of the frame signal selection circuit 5 for solving this problem. In the figure, 101 is A
It is ND. Further, the signal 100 is a low level only when the recording is actually performed, and is a high level when the recording on the magnetic tape 12 is not performed due to the initialization of the RAM 8 and the pulling of the clock of the extraction circuit 1. . In other words, the selection circuit 51 selects the signal 60 and performs frame synchronization only when the extraction circuit 1 performs a clock pull-in operation or the like to prepare for recording. In the synchronized state, the clear signal 24 is generated irrespective of the external frame signal to prevent the frame cycle from varying.

Note that the advantage of performing frame synchronization as described above is that when recording from one playback device to a plurality of recording devices,
It is possible to make a plurality of identical recording tapes with the same frame heads at the same time.

In the above description, the recording device is an example, but the frame synchronization by the external frame signal can be applied to the reproducing device. That is, it is possible to reproduce a plurality of tapes that are frame-synchronized by the above-described method by a plurality of reproducing devices at the same timing when the heads of the frames match.

FIG. 9 shows a block diagram when the present invention is applied to a rotary head PCM reproducing apparatus. In the figure, 110 is a reproducing circuit for equalizing the waveform of the reproduced signal from the magnetic tape 12, 11
1 is a demodulation circuit for performing demodulation 112 is a decoding circuit for performing error correction,
113 is an interpolation circuit that interpolates data that cannot be corrected by the decoding circuit 112, and 114 is D / that exchanges PCM signals for analog signals.
An A converter, 115 is an audio signal output terminal, and 116 is an identification signal generation circuit that generates a channel selection signal according to the timing generated by the timing generation circuit 4.

Further, when a plurality of tapes that are continuously spliced and recorded by a plurality of recording devices that are frame-synchronized by using the present invention are continuously spliced and reproduced by a plurality of reproducing devices, by using an external frame signal according to the present invention, By applying frame synchronization to all playback devices, continuous playback is possible without interruption.

〔The invention's effect〕

According to the present invention, in the PCM signal recording apparatus, channel synchronization can be automatically selected when there is no frame synchronization signal in the input signal, and frame synchronization can be automatically selected when there is a frame synchronization signal.

Further, even when there is no frame synchronization signal, the frame signal can be synchronized by inputting a frame signal having a frame period. In this case, a preparatory state in which recording or reproduction is not performed is provided, and by synchronizing with the external frame signal only in this preparatory state, the external frame signal and the channel selection signal are asynchronous when actually recording or reproducing. Therefore, it is possible to prevent the operation from becoming unstable.

[Brief description of drawings]

FIG. 1 is a block diagram of a rotary head PCM recorder according to an embodiment of the present invention, FIG. 2 is a format diagram of input data, FIG. 3 is a timing chart diagram showing the relationship between frames and data, and FIG. Is a circuit diagram of the clear signal generation circuit and the frame signal selection circuit, and FIG. 5, FIG. 6, FIG.
FIG. 8 is a timing chart showing the circuit operation of the figure, FIG. 8 is a circuit diagram of a clear signal generation circuit and a frame signal selection circuit, and FIG. 9 is a block diagram of another embodiment of the present invention. 1 ... Extraction circuit, 2 ... Synchronization signal generation circuit, 3 ... Clear signal generation circuit, 4 ... Timing generation circuit, 5 ... Frame signal selection circuit, 21 ... Channel selection signal, 22 ... Frame synchronization signal, 23 ... Synchronization signal, 24 ... clear signal, 25 ... internal frame signal, 26 ... external frame signal, 116 ... identification signal generating circuit.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Shinichi Wakumura 4-2610 Hanazono, Tokorozawa-shi, Saitama Pioneer Co., Ltd. Tokorozawa Plant (72) Inventor Ichiro Miyake 4-2610 Hanazono, Tokorozawa-shi, Saitama Pioneer shares Company Tokorozawa factory

Claims (5)

[Claims] 1. A synchronization having a timing generation circuit for forming PCM data input from an input terminal in a frame unit and recording it on a medium through a recording unit, and for generating an operation timing signal in a frame unit in the recording unit. In the circuit, in the frame unit at the input terminal
When the frame synchronization signal indicating the beginning of the frame unit is present in the PCM data, the position of the beginning data of the frame unit generated by the timing generation circuit is synchronized with the position of the beginning data of the frame unit, and A synchronizing circuit characterized by comprising a control means for synchronizing the head data in the frame unit generated by the timing generating circuit by the identification signal added to the PCM data when the synchronizing signal does not exist. 2. The synchronizing circuit according to claim 1, wherein the PCM data includes left channel data or right channel data, and the identification signal is a channel identification signal added to the PCM data. The control means, an extraction circuit for extracting the frame synchronization signal and the channel identification signal from the PCM data, and a synchronization signal for synchronizing the position of the head data in the frame unit generated by the timing generation circuit, If the frame sync signal does not exist, the head data in the frame unit is either the left channel or the right channel, and the frame sync signal is generated by the frame sync signal or the channel identification signal extracted by the extraction circuit. A synchronous circuit characterized by being fixed to the crab. 3. A synchronization having a timing generation circuit for generating PCM data input from an input terminal in a frame unit and recording it on a medium through a recording unit and generating an operation timing signal in a frame unit in the recording unit. In the circuit, an external frame signal input means for inputting an external frame signal is provided, and the position of the head data in the frame unit generated by the timing generation circuit using the external frame signal input by the external frame signal input means is set. A synchronizing circuit comprising control means for synchronizing. 4. The synchronization circuit according to claim 3, wherein the control means is configured to control the external frame signal and the external frame signal.
A synchronization circuit characterized in that the position of the head data in the frame unit generated by the timing generation circuit is synchronized by using the identification signal added to the PCM data. 5. The synchronizing circuit according to claim 4, wherein the PCM data includes left channel data or right channel data, and the identification signal is a channel identification signal added to the PCM data. The control means extracts, by the extraction circuit, an extraction circuit for extracting the channel identification signal from the PCM data and a synchronization signal for synchronizing the position of the head data in the frame unit generated by the timing generation circuit. And a synchronization signal generating means for generating the generated channel identification signal, wherein the start data in frame units is fixed to either the left channel or the right channel.