JPS6443872A - Synchronizing circuit - Google Patents

Synchronizing circuit

Info

Publication number
JPS6443872A
JPS6443872A JP19985987A JP19985987A JPS6443872A JP S6443872 A JPS6443872 A JP S6443872A JP 19985987 A JP19985987 A JP 19985987A JP 19985987 A JP19985987 A JP 19985987A JP S6443872 A JPS6443872 A JP S6443872A
Authority
JP
Japan
Prior art keywords
signal
frame
synchronizing
external
synchronizing signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19985987A
Other languages
Japanese (ja)
Other versions
JPH0770160B2 (en
Inventor
Yuji Hatanaka
Hiroo Okamoto
Shinichi Wakumura
Ichiro Miyake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Pioneer Corp
Original Assignee
Hitachi Ltd
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Pioneer Electronic Corp filed Critical Hitachi Ltd
Priority to JP19985987A priority Critical patent/JPH0770160B2/en
Publication of JPS6443872A publication Critical patent/JPS6443872A/en
Publication of JPH0770160B2 publication Critical patent/JPH0770160B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the instability of operation by synchronizing a timing generating circuit by an external identifying signal, when a frame synchronizing signal is not contained in an input signal. CONSTITUTION:When the frame synchronizing signal 22 is not contained in input data 19, a synchronizing signal generation circuit 2 outputs the synchronizing signal 23 at every trailing edge of a channel selecting signal 21. If synchronization is attained once by one of the channel selecting signals 21, the head of a frame can be synchronized. Besides, when the frame synchronizing signal does not exist, the head of the frame can be synchronized with an external frame signal by inputting the external frame signal 26 which has the same frame period as the timing generating circuit 4, from an external frame signal input terminal 17.
JP19985987A 1987-08-12 1987-08-12 Synchronous circuit Expired - Fee Related JPH0770160B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19985987A JPH0770160B2 (en) 1987-08-12 1987-08-12 Synchronous circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19985987A JPH0770160B2 (en) 1987-08-12 1987-08-12 Synchronous circuit

Publications (2)

Publication Number Publication Date
JPS6443872A true JPS6443872A (en) 1989-02-16
JPH0770160B2 JPH0770160B2 (en) 1995-07-31

Family

ID=16414836

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19985987A Expired - Fee Related JPH0770160B2 (en) 1987-08-12 1987-08-12 Synchronous circuit

Country Status (1)

Country Link
JP (1) JPH0770160B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005314845A (en) * 2004-04-30 2005-11-10 Seiren Co Ltd Inkjet printing cloth and method for producing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005314845A (en) * 2004-04-30 2005-11-10 Seiren Co Ltd Inkjet printing cloth and method for producing the same

Also Published As

Publication number Publication date
JPH0770160B2 (en) 1995-07-31

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees