JPS60245334A - Digital signal regenerating device - Google Patents

Abstract

PURPOSE:To prevent out-of-synchronism caused by a cycle slip of a PLL circuit, by controlling the width of a gate signal for detecting a synchronizing signal, by a value of an output of a counter for deciding the out-of-synchronism. CONSTITUTION:A reference value is set in advance to a decoder 14, and at the time point when a carry signal 8a of a counter 8 has counted up to this value, a selecting signal 14a becomes a logical value ''1'', and a gate signal 16a is switched to a gate signal 16b having large pulse width. Accordingly, when the quantity of a cycle slip of a PLL circuit 4 is within a bit clock of a specified value, a synchronizing signal can be detected again, and no out-of-synchronism is caused. Accordingly, it can be prevented that a jarring sound of a digital signal regenerating device is regenerated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital signal reproducing device for reproducing digital signals.

Conventional configurations and their problems In recent years, development of digital audio equipment that applies digital technology to the consumer field, mainly in the audio industry, has become active. FIG. 1 shows the format of a digital signal recorded on a record carrier of such digital audio equipment, such as a disk or tape. The data 2 to be finally reproduced as an audio signal is divided into blocks for each unit time along with an error correction code for correcting data errors caused by scratches on the record carrier, etc., and synchronization is performed at the beginning of each block. It is recorded with a synchronization signal 1 added thereto. This one block is called one frame. To read such a digital signal, as is known, bit synchronization is performed in advance using a PLL circuit or the like, and a bit clock that is an output from this PLL circuit is used. This makes it possible to determine whether the logical value is 01'' or ``o''.Next, the synchronization signal 1 is detected and sent to the synchronization circuit along with the bit clock to establish frame synchronization.

FIG. 2 shows the configuration of a conventional device 6 like this. The digital signal 3 read from the record carrier is input to the PLL circuit 4 and a synchronization pattern detection circuit 5 for detecting a synchronization pattern of a predetermined synchronization signal. The PLL circuit 4 outputs the bit clock 4a. The output 5a of the synchronization pattern detection circuit 5 is inputted to the synchronization detection determination circuit 7 through an AND gate 6. The synchronization detection determination circuit 7 outputs a synchronization detection signal 7a when a synchronization signal is detected, and outputs a synchronization non-detection signal 7b to a counter 8 or 9 when no synchronization signal is detected. When the counters 8 and 9 count up to their respective predetermined values, they output a carry signal 8a or 9a to reset or set a set resect flip 70 knob (hereinafter referred to as 5R-FF) 10. SR-, FF10 output 10
a is input to one end of the OR gate 11. On the other hand, the gate signal generation circuit 12 is synchronized with the synchronization detection signal 7a, and is ORed with the gate signal 12a for turning on the AND gatero only a little before and after the time when the synchronization signal of the next frame is to be detected. The signal is output through all gates 11. The timing generation circuit 13 also receives the synchronization detection signal 7a.
Timing is adjusted at , and an internal synchronization signal 13a necessary for synchronization detection determination is output to the synchronization detection determination circuit 7.

The operation of the synchronous circuit configured as above will be explained using the timing charts of FIGS. 31 and 4. Ashizu No. 3
In the figure, an output 6a is generated in accordance with the end of the synchronization signal 1 due to the synchronization signal 1 of the digital signal 3 inputted to the synchronization pattern detection circuit 6. On the other hand, the gate signal 11a
is the AND gate 6 for a certain period of time before and after this output 6a.
'f: Turns on. The purpose of this is to prevent a digital signal with the exact same pattern as sync signal 1 from occurring in a place where sync signal 1 should not exist due to a dropout of digital signal 3 (hereinafter referred to as dropout) caused by a corner of the record carrier, etc. This is to prevent erroneously detecting this as a correct synchronizing signal, thereby disturbing the operation of the synchronizing circuit and causing data errors. Next, an output a is generated from the synchronization determination circuit 7 at the same timing as the output 6a of the synchronization pattern detection circuit 6. As in the third frame, when the synchronization signal is lost and not detected due to dropout D or the like, an output cuff b occurs. The timing of the internal synchronization signal 13a is adjusted by the synchronization detection signal 7a output one frame before.
It is generated at the timing when the bit clock 4a is counted by a number corresponding to one frame. Furthermore, if the output 10a of the 5R-FF 10 has a logical value IIO", it is clear that the gate signal 11a is the same signal as the output 12& of the gate signal generation circuit 12, and this output 1
Similarly to the internal synchronization signal 13a, the timing of the bit clock 2a is also synchronized using the synchronization detection signal 7a output one frame before, and synchronization is performed using the timing of the period obtained by counting the bit clock 4a by a number corresponding to one frame. The output 5a of the pattern detection circuit 6 is generated only for a short period before and after the output 5a should be generated.

If the synchronization signal is not detected by the drop alarm (D) or the like, timing is adjusted using the internal synchronization signal 13a.

Next, using FIG. 4, calculate the counter 8 and the counter 9.
Explain the operation. Each counter is used to determine whether synchronization has been established or synchronization has been lost. That is,
Now the counter 8 has a count value of 62'' and the carry signal 8a
On the other hand, if the counter 9 is set to output the carry signal 9a with a count value of "3", and there is a dropout D1 over three frames in the digital signal 3, the output of the 5R-FF10 is 10a outputs a logical value of 11'' when the carry signal 9a is output.

When the output 10a has a logical value of "0", it indicates that synchronization has been established, and when the output 10a has a logic value of 1#, it indicates that synchronization has been lost.

Generally, in the digital signal reproducing apparatus as described above, if a synchronization signal is not detected a predetermined number of times in a row, it is determined that synchronization has been lost. this is,
In addition to simply having a dropout in the digital signal 3 and not being able to detect the synchronization signal, a dropout occurs in a part of the digital signal 3 due to a phenomenon called cycle slip that occurs in the PLL circuit 4, resulting in bit synchronization. Although the synchronization signal itself is not incorrect,
First, the gate signal generation circuit 12 and the timing generation circuit 13 are disturbed by the generation of too much or too little bit clock 4a, and as a result, the gate signal 12a is distorted by the synchronization pattern detection circuit U.
This is because if the output 6d of tS is generated at the wrong timing when it cannot be gated, a state may occur in which the synchronization signal cannot be detected continuously. The timing disturbance caused by this cycle slip is usually about ±1 to 3 bit clocks, so taking this into consideration, the gate signal 1
The width of 2a is set to approximately ±5 pit clocks with respect to the output 5a of the synchronization pattern detection circuit 5. On the other hand, the setting values of the counters 8 and 9 are determined by considering the correction ability of the error correction code, and the setting values for the counter 8 are @11I or "2", and the setting values for the counter 9 are values that can be sufficiently covered by the correction ability, for example, 8 consecutive frames of error code. 6” to 17 if possible to correct
In addition, even if the correction capability is exceeded, the value may be set to exceed 8'' if the audio signal finally reproduced does not become audibly unpleasant due to interpolation or the like. However, if interpolation is performed continuously, the sense of distortion may increase to some extent.

As mentioned above, in the conventional configuration, even one cycle slip of the pPLL circuit 4 due to dropout etc.
If the 6-bit chronograph is exceeded, even if there is no error in the digital signal, it will become out of synchronization.
As a result, data errors may occur over several frames, and in some cases, aurally unpleasant sounds may be reproduced. In addition, if you set a gate signal width sufficient for the amount of cycle slip (for example, about ±16 bit clocks), the pattern will be exactly the same as the synchronization signal that exists in the input data due to dropouts etc., as mentioned earlier. The problem was that the operation of the synchronization circuit was often disturbed by the digital signals of .

OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional problems, and provides a digital signal reproducing device f that can prevent continuous data errors due to out of synchronization caused by cycle slips in a PLL circuit. With the goal.

Structure of the Invention The present invention comprises: a synchronization pattern detection circuit that detects a synchronization signal from a digital signal to which the synchronization signal is added; a first counter whose timing is adjusted by the output from the detection circuit; A gate signal generation circuit that is driven by a counter and generates a gate signal that gates the output of the detection circuit for a certain period of time before and after the detection of the synchronization signal, and a synchronization that occurs when the detection circuit does not detect the synchronization signal. It has a second counter that counts non-detection signals, and by controlling the width of the game signal using the output value of the second counter, it is possible to prevent synchronization due to cycle slips in the PLL circuit. It is something.

DESCRIPTION OF EMBODIMENTS FIG. 5 is a block diagram of a digital signal reproducing apparatus in one practical example of the present invention. In FIG. 5, a PLL circuit 4, a synchronization pattern detection circuit ts, an AND gate 6, a synchronization detection determination circuit 7. Counter 8. Counter 9.5R-FF10.
OR gate 11. The timing generation circuit 13 has the same configuration as the conventional example.

The timing of the counter 16 is adjusted using the synchronization detection signal 7a. ROM (read only memory) 16
decodes the output 15a of the counter 16 and outputs the gate signal 16 with a ±5-bit clock or ±15-bit clock width to the output 5a of the synchronization pattern detection circuit 5, for example.
a or 16b is output to the selector 17. Selector 1
The select signal 14a of No. 7 is a signal obtained by decoding the output 9b of the counter 9 by the decoder 14. Gate signal 16a
Or 16b is selected by this select signal 14a and passes through OR gate 11 as output 17a and gates AND gate 6.

The operation of the digital signal reproducing apparatus of this embodiment configured as described above will be explained using the timing chart shown in FIG. First, the set value at which the carry signal 8a of the counter 8 is output is 2", the set value at which the carry signal 9a of the counter 9 is output is 6", the decoder 14 decodes the output 9b, and if the output 9b is less than 3, the logic is If the select signal 14a is the logical value “φ”, the selector 17 outputs the gate signal 16aff,
, if the logical value is "1", the gate signal 16b is selected. As shown in FIG. 6, if the digital signal 3 causes a data error over two frames due to the dropout D2, and the PLL circuit 4 causes a cycle slip around time 1=1A, the amount of which causes a 15-bit clock. The subsequent OR gate output 11a is generated at a timing relatively delayed from the timing at which the correct synchronization signal is detected. Therefore, the synchronization signal immediately after dropout cannot be detected even if it is not erroneous. In the conventional case, the synchronization non-detection signal 7b would be generated continuously as it is, and when the counter 9 counts 6, the carry signal 9a will be generated and it will be determined that the synchronization is out of synchronization, and the OR gate output 11a will always be the logic value "1u" and synchronization will occur again. An operation for establishment is performed. During this time, all data for 6 frames become data errors. However, in this embodiment, the time t = t when the counter 9 counts up to 3
At B, the select signal 14a becomes the logical value "11+", so the gate signal is switched to the wide gate signal 16b. Therefore, if the amount of cycle slip is within 115 bits, the synchronization signal is switched again at time 1=10. As described above, according to this actual example, the decoder detects that the value of the output 9b of the counter 9, which is used to determine the loss of synchronization, becomes 3''. The logic value of the select signal 14a from 14 is set to 1", and the gate signal 16
By switching to the a'i gate signal 16b, loss of synchronization due to cycle slips can be prevented, and data errors of 6 frames can be reduced to 3 frames instead of 6 frames due to loss of synchronization.

Effects of the Invention The present invention prevents synchronization caused by cycle slips in a PLL circuit by controlling the width of a gate signal for detecting a synchronization signal based on the output value of a counter that determines synchronization. It is possible to suppress extremely long consecutive data errors caused by data errors to relatively short data errors, and prevent data errors from occurring that exceed the correction ability of the error correction code and move to interpolation due to loss of synchronization. Accordingly, it is possible to realize an excellent digital signal reproducing device that can prevent undesirable sounds from being reproduced.

[Brief explanation of drawings]

Figure 1 is a diagram showing the format of a digital signal, Figure 2 is a block diagram of a conventional digital signal reproducing device, Figures 3 and 4 are diagrams showing the format of a digital signal.
The figure is a timing chart for explaining the operation of a conventional digital signal reproducing apparatus, FIG. 5 is a configuration diagram of a digital signal reproducing apparatus in an actual case of the present invention, and FIG. 6 is an explanation of the operation of the digital signal reproducing apparatus. This is a timing chart for 5... Synchronization pattern detection circuit, 9...
Counter, 14...Decoder, 15...Counter, 16...ROM, 1y...Selector. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2 Figure 3 Figure 1〉Shiho also Figure 5 Figure 6 Figure 1 : : tAtB tC 1 hour t

Claims (1)

[Claims] A device for reproducing a digital signal to which a synchronization signal of a predetermined bit pattern is added to data divided into blocks for each unit time, the device comprising: a synchronization pattern detection circuit for detecting the synchronization signal from this digital signal; , a first counter whose timing is aligned by the output from the detection circuit; and a gate signal driven by the first counter to gate the output of the detection circuit for a certain period of time before and after the synchronization signal is detected. It has a gate signal generation circuit that generates a gate signal, and a second counter that counts a synchronization non-detection signal that is generated when the detection circuit does not detect a synchronization signal. A digital signal reproducing device characterized by controlling the width of the signal.