JP2585536B2 - Digital data reproducing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital data reproducing apparatus such as a PCM recorder, and more particularly to a digital signal processing circuit suitable for use in special reproduction such as variable speed reproduction.

[Conventional technology]

The conventional device is the IEICE Technical Report Vol.82 No.1
As discussed in paragraphs 1 to 8 of 90EA82-46, the system supports special playback at high speeds, such as high-speed random access and a search function with 200-times speed playback. No specific consideration has been given to the means or detection circuit suitable for detecting the control code to be performed.

[Problems to be solved by the invention]

In the above prior art, no specific consideration is given to signal detection means at the time of high-speed random access, and a control signal required for access cannot be detected when a tape is run at high speed, and an access operation cannot be performed normally. Or there was a problem that it took time.

An object of the present invention is to make it easier to detect a control signal for access at the time of the random access than at the time of normal reproduction,
An object of the present invention is to provide a digital data reproducing apparatus capable of performing an access operation stably and quickly.

[Means for solving the problem]

The object is to apply a control signal from the outside at the time of high-speed reproduction, to eliminate a limitation by a detection window of a synchronization signal and an area signal when detecting a synchronization signal and an address signal, and to detect a synchronization signal and an address signal in all regions. In addition, by relaxing the detection conditions, the synchronization signal added during recording,
This is achieved by making it easier to detect the address signal and increasing the ability to detect the access control signal.

[Action]

Relaxing the conditions for detecting the synchronization signal and address signal during high-speed access increases the number of erroneous detections of the synchronization signal and address signal, but does not involve sound output, and access control added as the same signal over multiple blocks during recording When the purpose is to detect a signal, no particular problem occurs, but the effect of increasing the probability of detection of a control signal is greater, and a more stable access operation is enabled.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. FIG. 1 is a circuit block diagram of a PCM reproducing apparatus using a rotating head, and FIG. 2 is a recording signal format showing a configuration of a data signal generated at the time of recording.
In FIG. 2, reference numeral 2 denotes a recording tape, and reference numeral 24 denotes a track format diagram showing a signal configuration of one track recorded during 90 ° when the rotary head contacts the tape. The structure of this one track is as follows. A signal to be recorded is recorded in the PCM area and the subcode area (SUB-1, SUB-2) as shown in FIG.
And signals for tracking servo ATF1 and ATF
Consists of two. Furthermore, the PCM area has 128 blocks, SBU1,
SUB2 is composed of eight blocks each. As shown in (b), the configuration of one block includes a synchronization signal S1 word, a control information code ID word, a block address BA1 word,
Consisting parity code P1 word and data w ₀ to w ₃₁ 32 words a total of 36 words. Here, the ID code is a control information code provided to reproduce a mode at the time of recording, such as a sampling frequency, the number of quantization bits, and a tape speed, at the time of reproduction. The block address BA is an address signal assigned to each block, and in the PCM area, “0”
7F "," 80-87 "in SBU1 area," 88-8F "in SUB2 area
And the most significant bit is “0” in the PCM area,
“1” becomes a subcode area. Also, the parity code P
Is the modulus of each of the two words ID and BA
Is a simple parity code generated by adding Data w ₀ to w ₃₁ is composed of codes for PCM signal or correction entered during recording. The configuration and operation of the present embodiment for reproducing the signal thus recorded will be described below.

FIG. 1 shows a rotary cylinder on which a magnetic head is mounted,
2 is a magnetic tape, 22 is a reproduction amplifier, 21 is a rotation system, a tape driving system and a servo circuit for tracking, 10 is a circuit for generating timing necessary to operate each circuit of the reproduction system, and 23 is an oscillator. is there. The reproduction signal read from the magnetic tape is synchronized in a word unit by the synchronization circuit 3 by detecting the synchronization signal and protecting the loss, and is demodulated by the demodulation circuit 4. Parity added at the time of recording is checked from the demodulated data by a parity check circuit 5, and an address latch circuit 6 and an ID code latch circuit 7 latch a block address and an ID code.
The reliability of the latched ID code is further checked by an ID code detection circuit 8, and a current reproduction mode, for example, a mode such as a sampling frequency or a tape speed is determined, and necessary timing is changed.

The result of the parity check is used as a factor for evaluating the reliability of the detected synchronous signal and the block address, and is used as a condition for detecting and protecting the synchronous signal and as one condition for the block address detection and protection in the address circuit 9. Further, by comparing the fetched block address (BADR) with a memory access address (C1ADR) for error detection and correction processing, which will be described later, control is performed so that data after correction on the memory is not rewritten due to erroneous address detection. If the beginning of the data is lost due to dropout or the like, the data to be written to the memory is set (PRSET output) in order to reduce the probability of occurrence of erroneous detection and erroneous correction in the error detection and correction processing (PRSET output). An address for writing the detected and protected block address to the memory is generated by the reproduction address generation circuit 17, and is written to the memory 12 (for example, RAM) via the interfaces 11, 16 together with the demodulated data.

The data written in the memory is then read out by the correction address generation circuit 18, the error correction and correction are performed by the correction circuit 13, the data is written back to the memory, and the corrected data is read out by the output address generation circuit 19. The signal is converted into an analog signal by the D / A conversion circuit 14 and output.

The feature of the present invention is that, during the high-speed reproduction, the sound signal detection protection and the block address signal detection protection processing are switched between the normal reproduction and the normal reproduction by the control signals AC0 and AC1 shown in FIG. In this way, a stable and high-speed access operation is performed by making it easier to detect the signal.

Hereinafter, the operation by the control signals AC0 and AC1 will be described in detail in order.

The control signal AC0 is a signal that acts on the detection and protection circuit of the synchronization signal and operates at the time of high-speed random access.

FIG. 3 shows an embodiment of the synchronization circuit according to the present invention. In the figure, the same reference numerals as those in FIG. 1 denote the same contents having the same functions. The synchronizing circuit comprises 31 to 39 in the figure, 31 is a synchronizing signal detecting circuit for detecting a synchronizing pattern from a reproduced signal, 35 is a flag for generating and processing various flags for detecting and protecting a synchronizing signal, and , 34, 36, and 38, a flag processing circuit 32 for synchronizing a synchronization signal detected by the reproduction clock with the master clock MCK by the internal crystal, and 33 a word, for example, 10 words, by the reproduction clock. A bit counter that divides each bit, a word counter that counts the number of data extracted from the reproduced signal in word units, a window counter for generating a synchronization signal detection window and various timing clocks, and a 37 for the above. Decoder circuit for generating timing clock, 38 is 1 to protect the synchronization signal detection cycle.
A block, for example, a counter for dividing and counting every 360 bits, and a decoder circuit 39 for generating a protected clock PCK. In the figure, 41 is a conversion circuit for converting a reproduced serial signal into a parallel signal, 42 is a latch circuit for taking in a reproduced signal in word units, 43 is a demodulation circuit, 45 is a latch circuit for latching demodulated data, 44
Is a demodulation error detection circuit for detecting a signal other than predetermined data as an error during demodulation. The synchronization signal DSYNC detected from the reproduction signal by the synchronization signal detection circuit 31 is compared with a detection window generated at a predetermined timing by the flag processing circuit 35, and the signal detected within the detection window is converted to a BSYNC signal. To synchronize the word counter with the bit counter 33 and the word counter which are operated by the reproduction clock.

The BSYNC signal is synchronized with the reproduction clock, and the synchronization circuit 32 further generates a signal CSYNC synchronized with the master clock MCK by the internal crystal.
The window counter 36 and the protection counter 38 operated by the master clock MCK are set to predetermined values by the CSYNC signal. (SET ₀ , SET ₁ , SET ₃ signals) The flag processing circuit includes, for example, an error flag (EF signal) at the time of demodulation, a parity flag (PF signal) which is a check result of a parity code added at the time of recording, and a detected block. The address value is detected by a discrimination signal such as an address flag (ADRF signal) which is a comparison result of whether or not the address value is an appropriate value preceding the address for accessing the memory for performing the error correction processing shown in FIG. It is determined whether the BSYNC signal is correct or due to an erroneous detection, and only when the BSYNC signal is correct, the counters 36 and 38 are set to predetermined values again (SET ₂ signal).

The window counter 36, which is corrected on the basis of the detection synchronization signal DSYNC, is decoded by the decoder circuit 37 to generate the ID code shown in FIG. 2, the latch clocks IDCK and ADRCK of the block address BADR, and the parity check. signal WD ₀ to open the detection window as described above generates the use clock CHCK at a predetermined timing, DSYNC signal in closing signal WD ₁ and the detection window is generated by decoding the NSYNC signal when not detected. When DSYNC is detected in a cycle of 360 bits per block as shown in FIG. 2, the window counter divides the frequency by 360 or more, for example, at a maximum of 370, and the detection window is ± 3 bits. W to detect DSYNC at the center when it has a length and is normal
D ₀ signal is generated by decoding the position of "357" of the window counter, WD ₁ is generated by decoding the "363". Originally BSYNC is detected at the position of "360", close the detection window with loading "2" by SET ₁ signal for CSYNC is delayed further by one clock in the synchronization circuit. When BSYNC is not detected, the window counter does not receive the SET ₁ signal, and when the count reaches “364” to continue counting, the WD ₁ signal is generated, the detection window closes, and further reaches “367”, for example. The NSYNC signal is generated and the window counter is set to “8”
To maintain 360 division by loading. Also, the protection counter is constantly 360 blocks, which is one block long.
The frequency division is maintained, and a reliable detection synchronization signal is discriminated by flag processing and corrected (SET ₀ , SET ₂ , SE
T _3). Further, by decoding from this protection counter, a clock PCK in which the cycle of one block and its timing are protected is generated.

FIG. 4 is a specific configuration example of the flag processing circuit shown in FIG. In the figure, the same signal names as those in FIG. 3 represent the same signals having the same functions. The generation circuit of the detection window as described above is 352, 357 denotes an AND gate for detecting whether present in DSYNC is within the detection window 353 and the first head flag (F ₁ flag which represents at the beginning of the reproduction data abbreviations To) generation circuit, 35
4 second head (abbreviated as F ₂ flag) flag generating circuit, 355 generator flag that identifies the state detected the BSYNC (abbreviated as A ₁ flag), 356 when the BSYNC is not detected, i.e. generator of the flag that identifies the state of detecting the NSYNC signal (a ₂ flag abbreviated), 351 wherein F _1,
The method of setting the window counter and protection counter (SET _{0 to} SET ₃ ) is selected according to the state of the F ₂ , A ₁ , A ₂ flags, the PF, EF, ADRF signals, and the presence or absence of the CSYNC, WD ₀ , and WD ₁ signals. This is a control circuit that sets or resets various flags in order to determine the processing method of the synchronization signal detection protection in the block.

An example of the processing algorithm of this control circuit is shown in the flowchart of FIG. First, as shown at the input terminal 35D in FIG. 4, the control circuit initializes each flag to an initial state by, for example, an STP signal indicating the head of an area signal indicating an area to which reproduced data is to be input. For example F ₁ flag = ON, F ₂ flag = ON, A ₁ flag = OFF, A ₂ flag = OFF, the detection window = ON. Further switches and conditions algorithm for detecting a first first of synchronizing signals of the head by F ₁ flag, the detection algorithm of the second or later. That is, at the time of the first synchronization detection, the protection counter is set only once by the first BSYNC (SET ₀ ), parity check (PF), address check (ADRF flag), demodulation error check (E
Setting the protection counter again with the all satisfied when the detection window and F ₁ flag OFF F) (SE
T _2). Processing the synchronization signal detection protection of the second and subsequent sets the protection counter as reliable enough synchronization signal when the BSYNC is detected consecutively twice by A ₂ flag (SET _3). If BSYNC is not detected twice consecutively, the timing for opening the detection window may be deviated from the predetermined timing at which DSYNC occurs. Therefore, the next DSYNC occurs without closing the detection window. Keep the window open until.

By the above processing, during normal reproduction, the synchronization signal detection protection at the beginning of the data can be accurately performed, and even when the leading data is lost, the synchronization signal can be quickly pulled in and synchronized. Also, at the time of double speed reproduction or random access exceeding a certain speed at which the synchronization signal cannot be detected within the opening time of the detection window described above, by the control signal AC,
Without closing the detection window and fixing each flag to the state at the time of initialization, the detection algorithm at the beginning is repeatedly operated. This does not protect against erroneous detection of the synchronization signal, but does not require sound output, and performs high-magnification randomization for the purpose of detecting a block address and a control ID code for access or the like in which the same signal is recorded over a plurality of blocks. There is no particular problem at the time of access, and synchronization signal detection is often omitted. In these special reproductions, the effect is that it is possible to perform normal access operation by processing all detected synchronization signals instead. Occurs.

In addition, these high-speed access, the detection window signal using a reliable identification signal of the data area at the time of special reproduction such as medium-speed search or the like, or the generation period of the detection window signal is made variable and lengthened. The same effect can be obtained by using means such as relaxing the detection conditions according to the flowchart shown in FIG.

FIG. 6 shows an embodiment of the flag processing circuit of the synchronous circuit according to the present invention. 4, the same signal names as those in FIG. 4 are the same signals having the same functions as described above. Also, 3510 and 3511 are latch circuits, 4400 is a shift register, and others are gate circuits. Further, the detection window generating circuit is constituted by from 3,521 to 3,523, F ₁ flag generating circuit 3561,3562, F ₂ flag generation circuit
3541,3542, A ₁ flag generating circuit 3551,3552, A ₂ flag generating circuit 3561,3562, control circuit is constituted by 3510 to 3519 and 4400,4401,5000,, 3571 Fourth diagram of a gate circuit 357 Is a circuit corresponding to. Here, various flag generation circuits including a detection window generation circuit are realized by set / reset flip-flop circuits using NAND gates, and latch circuits 3510 and 3511 are circuits for processing each flag and timing control of the SET _{0 to} SET ₃ signals. is there. Gate 3512
3518 are logic circuits for performing the condition determination processing shown in FIG. 5. Parity, address, and demodulation error flags are processed by a latch circuit 4400 and gates 4401, 5000.
The output of the gate 5000 becomes "H" level when all the three flags satisfy the conditions.

Here, the control signal AC0 is set to “H” level at the time of high-speed random access that does not produce sound, and the NOR gate 3519 fixes each flag constituted by the set / reset flip-flop to the initial value. Keep the “L” level open. Thus, the protection counter and the window counter are set (SET ₀ , SET ₁ ) by all the synchronization signals detected at the time of high-speed access, so that the correct block address and ID code can be easily taken in from the reproduced signal.

Next, a control operation of the address circuit by the control signal AC1 will be described. FIG. 7 shows an embodiment of the address circuit according to the present invention. In the figure, the same reference numerals as those in FIG. 1 indicate the same contents having the same functions. Reference numeral 94 denotes a circuit for switching between the offset value and the latched address data according to the control signal ATF, reference numeral 95 denotes an area counter for determining an area of reproduced data, reference numeral 96 denotes an area generation circuit as a decoder thereof, and reference numeral 97 denotes an address counter that operates only in the data area. , 93 is a head flag processing circuit for determining the head of data (E signal), 92 is a continuous check circuit for determining whether the latched block address is continuous with the previous address (C signal), 91 is a latched block address Is an address comparison circuit that determines whether the correction signal C1ADR is ahead of the correction address C1ADR (signal B) and compares the magnitude with a predetermined value (signal A) 98. The output comparison circuit 98 includes the output signals A, B, C, and E , And the D signal as a parity result, the latched block address is loaded into the address counter 97 or counted. The discrimination circuit 900 that generates a LOAD signal that controls whether the
This is a data set circuit that determines data loss at the beginning and sets data to be written to the memory to a fixed value (PRSET signal).

This address circuit performs a discrimination processing operation as shown in the flowchart of FIG. 8, for example, in order to detect or protect a block address from a reproduction signal during normal reproduction. In the figure, A to E correspond to the outputs of the respective circuit blocks shown in FIG. First, when detecting the tracking signal ATF detected from the reproduction signal, the area counter 95 shown in FIG. 7 loads an offset value and outputs a timing signal (AR) indicating an area to which a data portion of the reproduction signal is to be input.
Signal) is decoded and generated by an area generation circuit 96. When data is input by the switching circuit 94, the block address signal is detected from the reproduced signal, and only the correct address value is loaded, so that the area counter and the area signal AR decoded from the count value are read. Self-correct. When the area signal is outside the area based on this area signal, the head flag circuit and the address counter are initially set as shown in FIG. 961, and the address detection operation is not performed. The address detection algorithm at the head in the area first checks the parity, and then checks, for example, 15 or less to determine whether the latched address is a value near the head. If it is not less than 15, a continuous check is performed in consideration of the return when the head is missing. Finally, whether the detection address BADR precedes the correction address C1ADR (BADR ≧ C1A
DR) is determined, and when the above condition, that is, when D.E.A.B or D.E.C.B is satisfied, the head flag is released and the detected address is loaded into the address counter 97. Otherwise, write data is set, the address counter is counted up, and the set data is written to the memory.

In cases other than the head, the condition detection algorithm for address detection is switched according to the head flag. That is, parity check, continuous check, and BADR ≧ C1ADR are all OK.
At this time, the (D..CB) detection address is loaded into the address counter. Otherwise, the detected address is protected by counting up. As described above, the load determination algorithm can be realized by the following logical expression.

LOAD = D • E • A • B + D • E • C • B + D •• C • B-(1) The data set signal PRSET is output only when the head flag is set in the area.

The above is the block address detection protection operation performed during normal playback.For example, during high-speed double-speed playback such as random access, the detection state of the ATF signal and address signal becomes unstable, and the area signal is generated at a shifted position. It can happen enough. Applying the above condition discrimination at the time of high-speed reproduction results in too strict conditions, which often makes it impossible to perform an access operation normally. Therefore, at the time of medium-speed random access such as 30 to 50 times speed, the address detection condition is first relaxed by the above-described control signal AC0 to facilitate address detection. For example, an address and an ID code are detected only by a D signal by parity check and a B signal by address comparison. Further, at the time of high-speed random access such as 100 to 200 times speed, the control signal AC1
Thus, the restriction by the area signal is released, and the address signal is detected over the entire area under the relaxed detection condition as described above.

As described above, by loosening the detection conditions at the time of high-speed random access in which the reproduced data is unstable and by releasing the restriction by the area signal, erroneous detection of the address is increased. Omission of detection is suppressed, the address and ID code are easily detected, and the effect of performing the access operation normally is higher.

FIG. 9 is a specific circuit diagram of one embodiment according to the present invention. In the drawing, the input / output signal names are the same as those shown in FIGS. 1 to 8, SBAR is an input signal indicating a subcode area, and AR is an area signal indicating a timing to input data. It is. 911 is a comparison circuit, 922 is an addition circuit, 921,931,986 are D-flip-flop circuits,
The rest is a gate circuit. Here, the address comparison circuit shown in FIG. 7 is composed of 911 to 916, the continuous check circuit is 921 to 925, the head flag circuit is 931 and 932, and the discrimination circuit is 981.
986, the data set circuit is composed of 902 to 904. In the address comparison circuit, the output B of the comparator 911 is B
Compare the ADR 8-bit and C1ADR 8-bit addresses, and
Outputs "H" level when ≤ BADR. Top 1 in BADR
The bit is a signal of “L” level in the PCM area, and a signal of “H” level in other cases. Since the lower four bits are free, the gate 912 satisfies BADR ≦ 15 for both the PCM area and the subcode area. Only when this occurs, the “H” level is output. Further, gates 913 to 916 extract only the PCM area. In the continuous check circuit, the BADR is latched by the D-flip-flop circuit 921, delayed by one block, and the inverted output and the BADR are added, so that in the case of a continuous address, the lower 8 bits of the added value are all " carry-out C ₀ becomes 0 "to become H level, the gate 925 output is at the L level. Further, the continuous check is extracted by the gate 926 only in the PCM area, and the output C is fixed at the H level in the subcode area. In the leading flag circuit, the D-flip-flop circuit 931 is reset by the area signal AR so that the E output is fixed to the H level in other than the area, and when the signal of the discriminating circuit is output during the area, When an address is detected for the first time, the E output is changed to L level. Hereinafter, the E output does not change until the next area signal AR reset.

The gates 981 to 985 are logic circuits for realizing the algorithm of the above-described discrimination circuit, that is, the logic equation (1), and the discrimination circuit is latched by the D-flip-flop circuit 986. The data set circuit outputs the PRSET signal until the LOAD signal is output in the area. However, when a medium-to-high-speed random access signal is performed, the AC1 signal is applied, and the gate-based 902 cancels the area restriction condition (AR signal). Furthermore, by applying the control signal AC0 to the gate 984 only at the time of high-speed access, the address detection condition is relaxed as only parity and C1ADR ≦ BADR.

〔The invention's effect〕

According to the present invention, in a high-speed random access operation, a control signal is used to switch to a detection circuit in which detection conditions of a normal synchronization signal and an address signal are relaxed in accordance with each mode, thereby obtaining a synchronization signal and an address signal. Further, since the probability of detecting an access ID code can be increased, there is an effect that high-speed random access can be suppressed and malfunctions can be suppressed.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of one embodiment of the present invention, FIG. 2 is a data format diagram of a recording signal, FIG. 3 is a circuit block diagram of one embodiment of a synchronous circuit according to the present invention, and FIG. FIG. 5 is a circuit block diagram showing an example of a flag processing circuit of a synchronous circuit according to the present invention. FIG. 5 is a flowchart showing an example of a processing algorithm of the flag processing circuit. FIG. 6 is an embodiment of the flag processing circuit according to the present invention. A circuit diagram, seventh
FIG. 8 is a circuit block diagram of an embodiment of an address circuit according to the present invention. FIG. 8 is a flowchart illustrating an example of a processing algorithm of the address circuit. FIG. 9 is an embodiment of a determination circuit of the address circuit according to the present invention. FIG. 3 is a circuit diagram. 3 ... Synchronous circuit, 9 ... Address circuit, 35 ... Flag processing circuit, 98 ... Discriminating circuit, 900 ... Data set circuit, AC0 ... Control signal of synchronous signal detection window at the time of access, AC1 ... Access Control signal of area signal at time.

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Hiroyuki Kimura 292 Yoshida-cho, Totsuka-ku, Yokohama-shi Inside the Home Appliance Research Laboratory, Hitachi, Ltd. (72) Keiji Noguchi 292 Yoshida-cho, Totsuka-ku, Yokohama Hitachi, Ltd. Inside

Claims (2)

(57) [Claims] The data is divided into blocks, and a block synchronization signal, a block address code, an ID code for control information, and a parity code generated for checking the block address code and the ID code are provided for each block. A digital data reproducing apparatus for reproducing a signal recorded in units of a plurality of blocks by adding a detection window signal for detecting a synchronization signal; and a detection window generating circuit for generating a detection window signal for detecting a synchronization signal. A synchronization circuit for detecting a synchronization signal; and a detection circuit for detecting a block address code, an ID code, and data based on the synchronization signal detected by the synchronization circuit, wherein the detection window generation circuit detects the synchronization signal. Generating a detection window signal that opens and closes in the vicinity of a predetermined timing to be generated, and when the detection window signal is in the open state, the synchronization signal A first mode in which a detection window signal is opened other than near a predetermined timing at which a synchronization signal is to be detected, and the detection operation of the synchronization signal is performed when the detection window signal is in an open state. Digital data reproducing apparatus having a second mode for performing 2. A method for dividing data into blocks, each block including a block synchronization signal, a block address code, an ID code for control information, and a parity code generated for checking the block address code and the ID code. A digital data reproducing apparatus for reproducing a signal recorded in units of a plurality of blocks by adding a detection window signal for detecting a synchronization signal; and a detection window generating circuit for generating a detection window signal for detecting a synchronization signal. A synchronization circuit for detecting a synchronization signal; a detection circuit for detecting a block address code, an ID code and data based on the synchronization signal detected by the synchronization circuit; and an area signal for controlling a block address code detection operation in the detection circuit. An area signal generation circuit for generating a synchronization signal, wherein the detection window generation circuit detects a synchronization signal. A first mode in which a detection window signal that opens and closes near a predetermined timing to be generated is generated and the detection operation of the synchronization signal is performed when the detection window signal is in an open state; and a predetermined timing at which the synchronization signal is detected. A second mode for generating a detection window signal that is open other than in the vicinity and performing an operation of detecting the synchronization signal when the detection window signal is open; In the mode, an area signal is generated in the vicinity of the area where the data is recorded, and the detection operation of the block address code is performed in the area. In the second mode, the area signal is fixed, and the block signal is fixed for the entire period. A digital data reproducing device for detecting an address code.