JP3699765B2 - Error flag generation circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
  The present invention relates to an error flag generation circuit for reading serial data, particularly serial data having sync detection sync bits.
[0002]
[Prior art]
  In recent years, information networks are being built on a global scale, and information communication is indispensable in today's information society. Various methods have been tried for data communication in order to reduce communication costs such as an increase in transfer speed and high reliability of transfer data.
[0003]
  As adopted for reading data from CDROM as one method of data communication, serial data is divided into frames, and sync bits for synchronization detection and redundant bits for error detection are added for each frame. A method for detecting synchronization of data transfer and improving reliability is used. Data reading from the CDROM is to extract sync bits from data sampled by a clock synchronized with the linear velocity of the rotating recording plate, and to extract the data bit portion and redundant bit portion determined from the sync bit position.
[0004]
  Hereinafter, an example of a data read operation from a conventional CD-ROM will be described with reference to the drawings.
[0005]
  FIG. 9 shows a conventional error flag generation circuit. In FIG. 9, reference numeral 101 denotes a sync detection circuit that detects sync bits in serial input data and generates a sync timing signal. Reference numeral 102 denotes an error determination for data and redundant bits excluding the sync bits in serial input data. An error determination circuit to perform, 103 is a data storage register for storing the data part in the serial input data, 104 is an error flag storage register for storing an error flag as an output result of the error determination circuit 102, and 105 is inputted with a sync timing signal When the error flag is judgedThe error flag iserrorNot in stateIn this case, a data read circuit 106 that generates a read clock signal, and a timing generation circuit 106 that outputs a control signal that triggers an operation timing to each component of the error flag generation circuit.
[0006]
  Hereinafter, the operation of the error flag generation circuit configured as described above will be described. First, as shown in FIG. 9, the serial input data 110 is input to the sync detection circuit 101, the error determination circuit 102, and the data storage register 103. When the sync detection circuit 101 detects a sync pattern from the serial input data 110 or receives the sync interpolation timing signal 111 from the timing generation circuit 106, the sync detection signal 112 is sent to the timing generation circuit 106 and the data read circuit. And 105.
[0007]
  Further, the error determination circuit 102 performs error determination on the serial input data 110 and outputs an error flag 113 as a determination result to the error flag storage register 104. The data storage register 103 once stores the data portion of the serial input data 110 and then outputs it to the error flag storage register 104.
[0008]
  Next, after receiving the sync timing signal 112, the data read circuit 105 receives the error flag 113.Contents ofIs an errorsoIf not, the data read clock signal 114 is output to the timing generation circuit 106.
[0009]
  Next, the timing generation circuit 106 that has received the data read clock signal outputs a read clock signal 115 to the data storage register 103, andSerial data stored in the data storage register 103 isVia the error flag storage register 104 based on the read clock signal 115Output to data read circuit 105.
[0010]
  FIG. 10 is a circuit diagram showing the configuration of a conventional data storage register and error flag storage register. As the data storage register, two shift registers having the same configuration are connected in parallel. One is the up-side data storage register 121, and the other is the down-side data storage register 123, which is used alternately for reading and writing. The error flag storage register will be described on the up side. The up side error flag storage register 122 is connected to the MSB of the up side data storage register 121 so as to form a shift register, and the error flag is stored by the sync timing signal. Is done.
[0011]
[Problems to be solved by the invention]
  However, in the conventional error flag generation circuit, as shown in FIG. 10, each data storage register 121, 123 and each error flag storage register 122, 124 constitute a shift register. A part that is not the original sync pattern may be recognized as a sync pattern during operation or due to a read error from a CDROM, or a sync timing signal may be erroneously output when the read clock is not operating normally. . As a result, the data read circuit erroneously determines the MSB value of the shift register as an error flag, and depending on the content of the error flag, reads incorrect data.NoHad the problem of causing the system to malfunction.
[0012]
  Hereinafter, an example of malfunction will be described.
[0013]
  FIG. 11 shows the structure of the sector of ADIP data adopted for address recording of the minidisc. As shown in FIG. 11, a CRC (= Cyclic Redundancy Check) circuit is used as an error determination circuit for reading out ADIP data. All error determination circuits are reset for each sector, and the output of the error determination circuit is an error. Outputs the state of none.
[0014]
  Address data and redundant bits of the address data are serially input to the error determination circuit, but the sector address data itself has a content in which all bits are incremented by 1 from 0. In a minidisk in which only a small number of sectors are allocated to itself, the upper bits of the address data have many contents of 0. After all the registers of the error determination circuit are reset for each sector, the result of the error determination is in an error-free state while a number of upper bits whose contents are 0 are input as address data. If this error-free judgment result is loaded into the error flag storage register by a sync timing signal due to a malfunction, the error flagContents ofIs error-freeStatusHowever, normal data is not stored in the data storage register. In other words, the error flag that the data read circuit can readContents ofEven if the data is read based on the read data, the read data has an incorrect content.
[0015]
  An object of the present invention is to solve the above-mentioned conventional problems and prevent malfunction of a system by preventing a data reading circuit from reading erroneous data.
[0016]
[Means for Solving the Problems]
  In order to achieve the above object, the present invention refers to an error flag storage register after referring to an error flag.ContentCannot be readIndicate stateThe content is rewritten.
[0017]
  Specifically, the solution provided by the invention of claim 1 is an error flag generation circuit, wherein the sync bit of the serial input data in which a sync bit for synchronization detection and a redundant bit for error detection are added to serial data. A sync detection circuit that detects and generates a sync timing signal, and includes the serial data and the redundant bitSerial inputdataNoAn error determination circuit for performing error determination and the serialinputData storage register for storing data and output from the error determination circuitFirstA first error flag storage register for storing an error flag and the first error flag storage register outputSecondA second error flag storage register for storing an error flag and the second error flag storage register when the sync timing signal is inputThirdDetermine the error flag andThe content of the third error flag iserrorNot in stateA data read circuit for generating a first read clock signal and outputting a second read clock signal to the data storage register when the first read clock signal is input, From the data storage register through the second error flag storage registerTo the data readout circuitSerialinputRead dataControltimingGenerationCircuit, and the first error flag storage registerContents of the second error flag output byThe second error flag storage register isThe secondImmediately after storing the error flag,The timingGenerationThe circuit is configured to be brought into an error state by a circuit.
[0018]
  The first error flag storage register according to claim 1The contents of the second error flag output byThe second error flag storage register isSecondTiming immediately after storing the error flagGenerationSince the error state is caused by the control signal output from the circuit, when the sync timing signal is erroneously output, the data read circuit is the second error flag storage register.Third error flag output byEven if the contents ofThus, the data reading circuit will not read wrong data..
[0019]
  According to a second aspect of the present invention, an error flag generation circuit detects the sync bit of serial input data in which a sync bit for detecting synchronization and a redundant bit for error detection are added to serial data to generate a sync timing signal A sync detection circuit that performs the serial data and redundant bitsSerial inputAn error determination circuit for determining an error in the data, and the serialinputData storage register for storing data and output from the error determination circuitFirstAn error flag storage register for storing an error flag and the error flag storage register when the sync timing signal is inputSecondDetermine the error flag andThe content of the second error flag iserrorIn stateA data read circuit for generating a first read clock signal and outputting a second read clock signal to the data storage register when the first read clock signal is input. , From the data storage register through the error flag storage registerTo the data read registerRead the serial dataControltimingGenerationCircuit, and the error flag storage registerContents of the second error flag output byImmediately after the serial data is read out,An error state is set by the data reading circuit.
[0020]
  According to the configuration of claim 2, an error flag storage registerOf the second error flags output by YongSince the data read circuit is put into an error state immediately after the data is read, even if the sync timing signal is erroneously output, the data read circuit always determines the contents of the error flag storage register. UnreadableThus, the data reading circuit does not read erroneous data.
[0021]
  According to a third aspect of the present invention, an error flag generation circuit detects the sync bit of serial input data in which a sync bit for synchronization detection and a redundant bit for error detection are added to serial data to generate a sync timing signal A sync detection circuit that performs the serial data and redundant bitsSerial inputAn error determination circuit for determining an error of data; a reset circuit for extracting the serial data from the serial input data; and the reset circuitWill outputThe data storage register for storing the serial data and the error determination circuit outputFirstAn error flag storage register for storing an error flag and the error flag storage register when the sync timing signal is inputSecondDetermine the error flag andThe content of the second error flag iserrorNot in stateA data read circuit that generates a read clock signal, and when the read clock signal is input, by outputting a read permission signal to the reset circuit, the error flag storage register from the data storage register ThroughTo the data readout circuitRead the serial dataControltimingGenerationAnd the reset circuit includes:Read outSerial dataFollowed byBy the control signal output from the timing generation circuit,The content of the second error flag is an error state.DoOutput dataIt is to be configured.
[0022]
  With the configuration of claim 3,Read outdataFollowed byThe timing generation circuit outputs a control signal to the reset circuit,Outputs data that sets the second error flag to an error stateTherefore, even if the sync timing signal is output by mistake, even if the data read circuit determines the contents of the error flag storage register, it is always in a read disabled state.Thus, the data reading circuit does not read erroneous data.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
  Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
[0024]
  FIG. 1 is a circuit diagram of an error flag generation circuit according to the first embodiment of the present invention. In FIG. 1, reference numeral 11 denotes a sync detection circuit that detects a sync bit of serial input data and generates a sync timing signal. Reference numeral 12 denotes an error determination on the data portion and redundant bit portion excluding the sync bit of serial input data. An error determination circuit to perform, 13 is a data storage register for storing the data portion of serial input data, 14 is a first error flag storage register for storing an error flag which is an output result of the error determination circuit 12, and 15 is a first error. A second error flag storage register 16 for storing an error flag output from the flag storage register 14, and the first error flag 56B is determined when the sync timing signal is input, and the first error flag 56B is determined. Data read that generates a data read clock signal that is a read clock signal Circuit, 17 is a timing generating circuit for outputting a control signal that triggers the operation timing with respect to each component of the error flag generator.
[0025]
  Hereinafter, the operation of the error flag generation circuit configured as described above will be described. Serial input data 50 is simultaneously input to the sync detection circuit 11, the error determination circuit 12, and the data storage register 13. The sync detection circuit 11 detects the sync pattern from the serial input or receives the sync timing signal 52 from the timing generation circuit 17 and the data read circuit when the sync interpolation timing signal 51 from the timing generation circuit 17 is input. 16 is output. Whether the sync timing signal 52 is generated from the sync detection timing or the interpolation timing is not the intention of the present invention, and thus detailed description thereof is omitted.
[0026]
  Further, the error determination circuit 12 performs error determination on the serial input data 50 and outputs an error flag 53 to the first error flag storage register 14. After the error flag 54 is output to the second error flag storage register 15, the first error flag storage register 14 is reset to a content indicating that reading is impossible by a control signal from the timing generation circuit 17.
[0027]
  The data storage register 13 reads the read data excluding the sync bit portion and the redundant bit portion of the serial input data 50.TAfter temporary storage, the data is output to the second error flag storage register 15. The data read circuit 16 determines the content of the error flag 56B output from the second error flag storage register 15 when the sync timing signal 52 is input, and if the content is in a readable state.From the data storage register 13Read data 56 </ b> A is read through the second error flag storage register 15. The timing generation circuit 17 controls the entire system based on the write clock, the data read clock signal 57 and the sync timing signal 52.
[0028]
  The details of the read operation of the error flag generation circuit will be described below with reference to FIGS.
[0029]
  FIG. 2 is a timing chart of the read operation, and FIG. 3 is a circuit diagram showing the configuration of the data storage register. As shown in FIG. 2, serial input data is arranged in one sector in the order of SYNC (sync bit), DATAk (data), and CRCk (redundant bit), and the next sector is arranged following the redundant bit. It is. The data are input to the sync detection circuit, the error determination circuit, and the data storage register in this order of arrangement. Here, k is the number of sectors of serial input data.
[0030]
  As shown in FIG. 3, the data storage register,It is composed of an up-side data storage register 13a and a down-side data storage register 13b.Yes. up sideData storage register 13a isThere are as many storage elements 131 as the number of bits of data to be stored.,Via selector 134 which is a selection element,It is connected serially when reading data, and when reading data is loadedDown side data storage register 13b andConnected in parallel. Incidentally, in each terminal of the memory element 131, D represents a data input terminal, Q represents a positive logic data output terminal, and CK represents a clock signal input terminal.
[0031]
  First, the previous sector data (DATA0) is serially input as write data to the down side data storage register 13b. That is, as for the write data, data corresponding to a predetermined number of bits is stored in the down side data storage register 13b in synchronization with the data storage clock shown in FIG.
[0032]
  Next, as shown in FIG. 2, the sync timing of the next sector including DATA1 is detected when the sync bit has been input, and the data (DATA0) of the previous sector on the down side shown in FIG. It is also used as a load timing for storing in parallel in the data storage register 13a.
[0033]
  Further, as shown in FIG. 2, the error determination circuit performs an operation on the data portion (DATA1) and the redundant bit portion (CRC1) of the sector, and the error determination result after the final clock of the error determination operation clock.Is an error flagIs output to the first error flag storage register. The first error flag storage register receives the control signal of the timing generation circuit and takes in the error flag at the first error flag storage timing. Thereafter, the second error flag storage register captures the error flag output from the first error flag storage register at the sync timing. First error flag storage registerContents ofAfter the second error flag storage register fetches the error flag, it receives the control signal from the timing generation circuit and is reset to the content indicating the unreadable state.
[0034]
  Next, as shown in FIG.WhatThe error flag of the previous sector isoutputIs done. The data read circuit determines whether or not to read data according to the contents of the error flag. If the error flag indicates a readable state, the data read circuit outputs a data read clock signal that is a first read clock signal. Output to the timing generation circuit. The timing generation circuit receives the data read clock signal and outputs a read clock signal which is a second read clock signal to the up side data storage register 13a shown in FIG. 3, thereby setting the second error flag storage register. The data in the previous sector (DATA0) is read out serially.
[0035]
  As described above, according to the present embodiment, the first error flag storage is performed during the period in which the first error flag storage register holds the error determination result like the first error flag storage timing shown in FIG. The period from the timing to the first error flag reset timing, that is, the period indicated as “DATA0 flag” or “DATA1 flag” shown in FIG. 2, and the sync timing signal is erroneously output within these periods. Even so, there is no problem because the content of the error flag output to the data read circuit is the original error determination result. Further, even if the sync timing signal is erroneously output during a period other than the “DATA0 flag” and “DATA1 flag” shown in FIG. 2, the content of the error flag output to the data read circuit is the data read Impossible stateShowingBecause, DeThe data readout circuitIncorrectRead dataTo doAbsent.
[0036]
  In other words, no matter how the sync timing is output at the wrong timing, the error flag output to the data read circuit isIf the data is incorrect, it indicates that the data cannot be read. If the data is normal, it indicates that the data can be read.ContentLinked toTherefore, the data reading circuit does not read erroneous data, so that the system malfunction can be prevented.
[0037]
  Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.
[0038]
  FIG. 4 is a circuit diagram of an error flag generation circuit according to the second embodiment of the present invention. In FIG. 4, 11 is a sync detection circuit that detects the sync bit of serial input data and generates the sync timing signal 52, and 12 is an error determination for the data part and redundant bit part excluding the sync bit of serial input data. 13 is a data storage register for storing the data portion of serial input data, 21 is an error flag storage register for storing an error flag 53 that is an output result of the error determination circuit 12, and 16 is a sync timing signal 52 When the error flag 56B is determined and no error has occurred when the data is input, after the data read clock signal 57 is generated, the error flag reset signal 61 that makes the error flag storage register 21 unreadable is set to the error flag. Reading data output to the storage register 21 Road, 17 is a timing generating circuit for outputting a control signal 58 as a trigger for the operation timing with respect to each component of the error flag generator.
[0039]
  The difference from the first embodiment described in FIG. 1 is that the error flag storage register 21 is connected only between the data storage register 13 and the data read circuit 16, and the data read circuit 16 is connected to the error flag storage register 21.Indicates the error statusIt is a point to reset to.
[0040]
  Hereinafter, the operation of the error flag generation circuit configured as described above will be described with reference to the drawings. FIG. 5 is a timing chart of the read operation, and FIG. 3 is a circuit diagram showing the configuration of the data storage register described in the first embodiment. As shown in FIG. 5, serial input data is arranged in one sector in the order of SYNC (sync bit), DATAk (data), and CRCk (redundant bit), and the next sector is arranged in order after the redundant bit. It is a configuration. The data are input to the sync detection circuit, the error determination circuit, and the data storage register in this order of arrangement.
[0041]
  First, in FIG. 3, the previous sector data (DATA0) is serially input as write data to the down side data storage register 13b. Specifically, as the write data, a predetermined number of bits of data are stored in the down-side data storage register 13b in synchronization with the data storage clock shown in FIG.
[0042]
  Next, as shown in FIG. 5, the sync timing of the next sector including DATA1 is detected when the sync bit has been input, and the data portion (DATA0) of the previous sector on the down side shown in FIG. It is also used as a load timing for storing in parallel in the side data storage register 13a.
[0043]
  Further, as shown in FIG. 5, the error determination circuit performs an operation on the data portion (DATA1) and the redundant bit portion (CRC1) of the sector, and the error determination result after the last clock of the error determination operation clock.Is an error flagIs output to the error flag storage register. The error flag storage register receives the control signal from the timing generation circuit and takes in the error flag at the error flag storage timing immediately after the final clock of the error determination calculation clock.
[0044]
  Next, as shown in FIG.WhatThe error flag of the previous sector is stored at each error flag storage timing.outputIs done. The data read circuit determines whether or not to read data according to the contents of the error flag, and waits for the input of the sync timing signal when the error flag indicates a readable state.
[0045]
  Next, the data read circuit receives the sync timing signal, stores data (DATA0) in the up-side data storage register 13a shown in FIG. 3, and then timings the data read clock signal that is the first read clock signal. Output to the generation circuit. The timing generation circuit receives the data read clock signal and outputs a read clock signal which is a second read clock signal to the up-side data storage register 13a shown in FIG.The data storage register isVia error flag storage registerTo data readout circuitRead the previous sector data (DATA0) seriallyControl.
[0046]
  Next, the data read circuit 16 shown in FIG.,After reading the read data 56A, an error flag reset signal 61 is output to the error flag storage register 21, and the error flag storage register 21 is output.Of error flags output byThe,Unreadable stateReset to error state.
[0047]
  As described above, according to the present embodiment, the error flag storage register holds the error determination result like the error flag / read data shown in FIG. 5 because the data read clock is output from the error flag storage timing. 5, that is, the “DATA0 flag” or “DATA1 flag” period shown in FIG. 5, even if the sync timing signal is erroneously output within these periods, it is output to the data read circuit. Since the content of the error flag is the original error determination result, there is no problem. Furthermore, even if the sync timing signal is erroneously output during the period from the error flag storage register reset timing to the next sector error flag storage timing shown in FIG. 5, the content of the error flag output to the data read circuit is the data Since the content indicates that reading is impossible, the data reading circuit does not read data.
[0048]
  I.e.How wrongEven if it is output, the error flag output to the data read circuit isIf the data is incorrect, it indicates that the data cannot be read. If the data is normal, it indicates that the data can be read. Since this is linked to the data contents, the data reading circuit will not read the incorrect data. Can be prevented.
[0049]
  Furthermore, although the generation period of the data read clock shown in FIG. 5 has a certain time width in the description of the timing chart, in the actual system, the data read period for one sector time is so small that it can be ignored. The error flag that is output to the data reading circuit indicates normal contents regardless of the timing at which the sync timing signal is output in error at any timing, so that the data reading circuit does not read out incorrect data. Can be prevented from malfunctioning.
[0050]
  Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.
[0051]
  FIG. 6 is a circuit diagram of an error flag generation circuit according to the third embodiment of the present invention. In FIG. 6, 11 is a sync detection circuit that detects the sync bit of the serial input data and generates the sync timing signal 52, and 12 is an error determination for the data portion and the redundant bit portion excluding the sync bit of the serial input data. , An error determination circuit 31, a reset circuit for extracting the data portion of the serial input data, 13 a data storage register for storing the data portion of the serial input data, and 21 an error flag 53 which is an output result of the error determination circuit 12 The error flag storage register 16 stores the error flag 56B when the sync timing signal 52 is input.,If no error has occurredDeThe data read circuit 17 for generating the data read clock signal 57 outputs a control signal 58 that triggers the operation timing to each component of the error flag generation circuit, and after reading the read data 56A, the reset circuitReadProhibition of protrusionToThis is a timing generation circuit that outputs a read inhibit signal 71B.
[0052]
  The difference from the first embodiment described in FIG. 1 is that the error flag storage register 21 is connected only between the data storage register 13 and the data read circuit 16, and the data storage register 13outputThe reset circuit 31 is newly provided in the preceding stage of the data storage register 13 so that the data to be read can be switched to the specific value indicating the unreadable state.
[0053]
  Hereinafter, the operation of the error flag generation circuit configured as described above will be described. FIG. 7 is a timing chart of the read operation, and FIG. 8 is a circuit diagram showing configurations of the reset circuit and the data storage register. As shown in FIG. 7, in the serial input data, one sector is arranged in the order of SYNC (sync bit), DATAk (data) and CRCk (redundant bit), and the next sector is arranged in order after the redundant bit. This is a configuration. The data are input to the sync detection circuit, the error determination circuit, and the reset circuit in this order of arrangement.
[0054]
  In FIG. 8, two shift registers having the same configuration are connected in parallel to the data storage register. One is the up-side data storage register 13c, and the other is the down-side data storage register 13d, which is used alternately for reading and writing. Each data storage register 13c and 13d has serially connected storage elements 131 corresponding to the number of bits of data to be stored. Incidentally, in each terminal of the memory element 131, D represents a data input terminal, Q represents a positive logic data output terminal, and CK represents a clock signal input terminal. The reset circuit is composed of AND gates connected to the LSB sides of the data storage registers 13c and 13d, the up side data storage register 13c has an up side reset circuit 132, and the down side data storage register 13d has a down side reset. The circuits 133 are connected to each other.
[0055]
  First, the previous sector data (DATA0) is serially input as write data to the up side or down side data storage register. Specifically, as the write data, a predetermined number of bits of data are stored in the up-side data storage register 13c or the down-side data storage register 13d in synchronization with the data storage clock shown in FIG.
[0056]
  Next, as shown in FIG. 7, the sync timing of the next sector including DATA1 is detected when the sync bit has been input, and the data of the previous sector (DATA0) on the up side or down side shown in FIG. After storing the data, read dataWhatCross-switch switching signal that switches the read clock signal to output the signal as the shift register clock signalSwitching timingIn addition, the switching signal of the cross switch that switches whether the output data is output from the data storage register on the up side or the down sideSwitching timingUsed as
[0057]
  Further, as shown in FIG. 7, the error determination circuit performs an operation on the data portion (DATA1) and the redundant bit portion (CRC1) of the sector, and the error determination result is displayed in the error flag after the last clock of the error determination operation clock. Output to the storage register. The error flag storage register receives the control signal of the timing generation circuit and determines the error flag storage timing immediately after the last clock of the error determination operation clock.Error judgment resultCapture error flags.
[0058]
  Next, as shown in FIG.WhatThe error flag of the previous sector is stored at each error flag storage timing.outputIs done. The data read circuit determines whether or not to read data according to the contents of the error flag, and waits for the sync timing signal to be input if the error flag is in a readable state.
[0059]
  Next, as shown in FIG. 6, the sync timing signal 52 of the next sector is detected, and the switching of whether the read data is output from the up side or down side data storage register shown in FIG. After finishingThe data read circuit 16A data read clock signal 57 is output to the timing generation circuit, and read data 56 A is read from the data storage register 13 via the error flag storage register 21. The reset circuit 132 or 133 in the shift register read by the up-side or down-side shift register shown in FIG.ReadPermit permissionEnable to representThus, the data read by the data storage register 13 is reset to the data content indicating the unreadable state when the data content after the LSB of the read data is shifted to the error flag storage register.
[0060]
  More specifically, the data read clock signal is composed of a pulse signal, and each time one pulse is output, the MSB of the data is output bit by bit, and the data read circuit has a predetermined number of bits of read data. A large number of data read clock signals 57 are output. Of the read data, valid data is read data from the MSB side corresponding to the number of bits corresponding to the number of outputs of the data read clock signal 57. As shown in FIG. 7, assuming that the number of effective bits of serial data is n, (n + α) data read clock signals are output. When (n + α) data read clock signals 57 are input, the timing generation circuit shown in FIG. 6 resets the read enable signal 71A including the read clock signal and the reset circuit enable signal shown in FIG. When the next (n + 1) -th data read clock signal 57 is input, a control signal with the reset circuit enable signal disabled is output.
[0061]
  As described above, according to the present embodiment, the data read clock is output from the error flag storage timing during the period in which the error flag storage register holds the error determination result as in the error flag / read data shown in FIG. 7, that is, the periods indicated as “DATA0 flag” and “DATA1 flag” shown in FIG. 7. Even if the sync timing signal is erroneously output within these periods, the data read circuit Since the content of the output error flag is the original error determination result, there is no problem. Further, even if the sync timing signal is erroneously output during the period from the n + 1 data read clock signals shown in FIG. 7 to the error flag storage timing of the next sector, the contents of the error flag output to the data read circuit are the data read The data reading circuit does not read the data because the contents indicate the impossibility.
[0062]
  I.e.How wrongEven if it is output, the error flag output to the data read circuit isIf the data is incorrect, it indicates that the data cannot be read. If the data is normal, it indicates that the data can be read. Since this is linked to the data contents, the data reading circuit will not read the incorrect data. Can be prevented.
[0063]
  Further, although the output period of the data read clock signal in FIG. 7 has a certain time width in the explanation of the timing chart, in the actual system, the data read period for one sector time is so small that it can be ignored. The error flag that is output to the data readout circuit is virtually no matter what timing the sync timing signal is erroneously output.If the data is incorrect, it indicates that the data cannot be read. If the data is normal, it indicates that the data can be read.Therefore, the data reading circuit does not read erroneous data, and the system malfunction can be prevented.
[0064]
  In the third embodiment, an AND gate is used as a configuration example of the reset circuit. However, after m (m is a natural number equal to or less than n) data read clock signals are output, the sync timing signal of the next sector is output. Until the data is output, an up-side or down-side reset signal shown in FIG. 8 may be input as a reset signal of the mth storage element 131 from the LSB side of the read-side shift register. In short, when the data reading circuit reads data of a predetermined number of bits or more from the shift register, the content of the error flag storage register only needs to indicate that reading is impossible.
[0065]
【The invention's effect】
  As described above, according to the error flag generation circuit according to claims 1 to 3, the error flag determined by the data read circuit when the sync timing signal is erroneously output.Contents ofAlwayserrorSince the data read circuit does not read erroneous data because of the state, it is possible to prevent malfunction of the system.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of an error flag generation circuit according to a first embodiment of the present invention.
FIG. 2 is a timing chart during a read operation of the error flag generation circuit according to the first embodiment of the present invention.
FIG. 3 is a circuit diagram of a data storage register of the error flag generation circuit according to the first and second embodiments of the present invention.
FIG. 4 is a circuit diagram of an error flag generation circuit according to a second embodiment of the present invention.
FIG. 5 is a timing chart during a read operation of an error flag generation circuit according to a second embodiment of the present invention.
FIG. 6 is a circuit diagram of an error flag generation circuit according to a third embodiment of the present invention.
FIG. 7 shows a timing at the time of a read operation of the error flag generation circuit according to the third embodiment of the present invention.
FIG.
FIG. 8 is a circuit diagram of a reset circuit and a data storage register of an error flag generation circuit according to a third embodiment of the present invention.
FIG. 9 is a circuit diagram of a conventional error flag generation circuit.
FIG. 10 is a circuit diagram of a data storage register and an error flag storage register of a conventional error flag generation circuit.
FIG. 11 is a configuration diagram of sectors of ADIP data employed for address recording on a mini disc.
[Explanation of symbols]
11 Sink detection circuit
12 Error judgment circuit
13 Data storage register
13a Up side data storage register
13b down side data storage register
13c Up side data storage register
13d down side data storage register
131 Memory element
132 up side reset circuit
133 down side reset circuit
134 Selector
14 First error flag storage register
15 Second error flag storage register
16 Data readout circuit
17 Timing generation circuit
21 Error flag storage register
31 Reset circuit
50 Serial input data
51 Sync interpolation timing signal
52 Sync timing signal
53 Error flag(First error flag)
54 Error flag(Second error flag)
55 Read data
56A Read data
56B error flag(Third error flag)
57 Data read clock signal
58 Control signal
61 Error flag reset signal
71A Read enable signal
71B Read inhibit signal
101 Sink detection circuit
102 Error judgment circuit
103 Data storage register
104 Error flag storage register
105 Data readout circuit
106 Timing generation circuit
110 Serial input data
111 Sync interpolation timing signal
112 Sync timing signal
113 Error flag
114 Data read clock signal
115 Read clock signal
116 Read data
121 Up side data storage register
122 up side error flag storage register
123 down side data storage register
124 down side error flag storage register

Claims (3)

A sync detection circuit for generating a sync timing signal by detecting the sync bit of serial input data in which a sync bit for synchronization detection and a redundant bit for error detection are added to serial data;
An error determination circuit for performing error determination of serial input data composed of the serial data and the redundant bits;
A data storage register for storing the serial input data;
A first error flag storage register for storing a first error flag output by the error determination circuit;
A second error flag storage register for storing a second error flag output from the first error flag storage register;
When the sync timing signal is input, the third error flag output from the second error flag storage register is determined, and if the content of the third error flag is not in an error state , the first error flag is output . A data read circuit for generating a read clock signal;
When the first read clock signal is input, the by outputting the second read clock signal to the data storage register, via the second error flag storage register from the data storage register wherein A timing generation circuit for performing control to read the serial input data to the data read circuit ,
The contents of the second error flag, wherein the first error flag storage register is output immediately after the second error flag storage register storing the second error flag, the error condition by the timing generating circuit An error flag generation circuit. A sync detection circuit for generating a sync timing signal by detecting the sync bit of serial input data in which a sync bit for synchronization detection and a redundant bit for error detection are added to serial data;
An error determination circuit for performing error determination of serial input data composed of the serial data and the redundant bits;
A data storage register for storing the serial input data;
An error flag storage register for storing a first error flag output by the error determination circuit;
When the sync timing signal is input, the second error flag output from the error flag storage register is determined, and if the content of the second error flag is not in an error state , the first read clock signal A data readout circuit for generating
When the first read clock signal is input, the data read circuit outputs the second read clock signal to the data storage register from the data storage register via the error flag storage register. A timing generation circuit for performing control to read out the serial input data to
The contents of the second error flag, immediately after the serial input data is read, the error flag generating circuit, characterized in that it is in an error state by said data readout circuit, wherein the error flag storage register outputs. A sync detection circuit for generating a sync timing signal by detecting the sync bit of the serial input data and redundant bits for the sync bits and error detection for detecting synchronization in the serial data is being added,
An error determination circuit for performing error determination of serial input data composed of the serial data and the redundant bits;
A reset circuit for extracting the serial data from the serial input data;
A data storage register for storing the serial data output by the reset circuit;
An error flag storage register for storing a first error flag output by the error determination circuit;
When the sync timing signal is input, a second error flag output from the error flag storage register is determined, and if the content of the second error flag is not in an error state, a read clock signal is generated A data readout circuit;
Timing of reading the serial data from the data storage register to the data read circuit via the error flag storage register by outputting a read permission signal to the reset circuit when the read clock signal is input Generating circuit,
It said reset circuit is followed by the serial data read by the control signal which the timing generating circuit outputs, and outputs the data to the contents of the second error flag an error condition Error Flag generation circuit.

Images