SU1487103A1 - Dynamic memory with error correction - Google Patents

Description

The invention relates to digital computing, in particular to the memory2

instrumental devices made on semiconductor dynamic memory elements. The purpose of the invention is to simplify the device. The device comprises a storage unit 1, a trunk element 2, a correction unit 3, a data register 4, switches 5, 8, a counter 6, an address register 7, an address decoder 9, a control block 10. In the device, periodic control of information and correction of single errors, independent of the presence of the circulation signal, occurs, which significantly reduces the probability of unrecoverable double errors that can occur during long-term memory operation. 2 hp f-ly, 4 ill.

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1487103

The invention relates to digital computing, in particular to a storage device (memory), performed on semiconductor dynamic memory elements.

The aim of the invention is to simplify the device by reducing hardware costs without reducing its speed

FIG. 1 is a block diagram of a dynamic memory device with error correction; in fig. 2 shows a diagram of the correction unit; in fig. 3 - drive diagram; in fig. 4 is a diagram of the control unit.

The storage device contains a drive 1, which is connected to the outputs of the trunk element 2 and the inputs of the correction unit 3 by its bidirectional inputs, a data register 4 whose inputs are connected to the outputs of the second switch 5, a counter 6 and an address register 7 whose outputs are the first and second inputs switch 8, the first output of which is connected to the input of the decoder 9 address. The control inputs of the counter 7 and switch 8 are connected to the outputs of the control unit 10. The device is connected to external devices using the address input 11, the information input 12 of the device, the first information output 13 of the device, as well as the control inputs 14, 15 and 16 of the device, and the second information output 17 of the device connected to the output of the information register 4; The correction unit 3 comprises a syndrome calculating unit 18, its outputs connected to a decoding ROM 19, the outputs of which are connected to the inputs of the decoder 20, the outputs of which are connected to the first inputs of the adder 21 modulo two. The storage unit 1 contains the main storage 22 and the control storage 23, the outputs of which are connected to the three-state element 24 and And 25, the control inputs of which are connected to the output of the inverter 26. The control 10 includes the re. shifter 27, AND 28 element, two elements OR 29 and 30, KB trigger 31, two AND elements 32, 33.

The device works as follows.

The bus 15 to the second input of the control unit 10 receives the synchronization series. The memory access signal is fed through the bus 16 to the first input of the control unit 10 and coincides in time with the pulses of the synchronization series. The frequency of the sync series is three times the frequency of the circulation signals. When a circulation signal arrives on bus 16, a single level is set at the first output of register 27, and zero levels are set at the second and third. If the bus 14 at this time served a single

level (“Record” signal), the AND 28, 33 elements are opened, and single levels appear at the outputs of the OR elements 29 and 30, under the influence of which information is recorded in drive 1. If there is a zero level in the presence of a circulation signal on bus 14, then only element AND 33 opens and a single level appears at the output of element OR 30, under the influence of which information is read in the accumulator.

According to the second clock pulse, the unit level is rewritten to the second output of register 27 and through the element OR 30 is fed to the drive, where it causes reading of information. In this tact, regeneration takes place - reading and control of information. In case of detection of an error in this cycle, the control signal arriving at the 5th input is triggered by a short-circuit trigger 31.

The third sync pulse overwrites the unit level to the third output of register 27 if K5-flip-flop 31 is in the unit state, and unit levels appear at the outputs of the OR elements 29 and 30. The write to drive 1 is performed. The fourth sync pulse coinciding with the inversion signal sets the unit level to first exit register 27.

Thus, the time interval between the inversion signals of the register 27 is divided into three clock cycles. In the first cycle, if a reference signal is present, information is recorded or read, in the second, regeneration and reading of information for its control occurs, in the third cycle, the corrected information is written to the memory if an error was detected in the previous cycle.

The signal of the first cycle resets the short-circuit flip-flop 31, which fixes an error in the word read in the second cycle. In addition, the unit level of this signal connects the first switch 8 to the address memory buses, the decoder inputs 9, the outputs of the address register 7, and the information inputs 4 of the device to the information register 4 inputs; the zero level of this signal connects the counter outputs 6 to the address inputs of the memory, and the inputs of the information register 4 - the outputs of the block 3 correction. The leading edge of this signal is the addition of the unit to the contents of counter 6. With the unit level from the output of the element OR 29, the output of the trunk element 2 is brought to the active state, and the output of the element 24 with three states through the inverter 26 is switched to the high-impedance state. As a result, information from the outputs of the information register 4 enters the main drive and the correction unit 3. The zero output state of element 29 converts trunk element 2 into a high-impedance state5

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element, and the element 24 - in the active, and information from the main drive enters the block 3 correction.

The unit level at the output of the AND 32 element occurs in the third cycle when there is an error signal, which is generated in the second cycle in correction block 3 and stored in trigger 31, which allows recording the read and corrected information of the second cycle in information register 4. The zero level at the output of the element And 32 translates the information register 4 in the mode of transmission of information from the outputs of the second switch 5 without memorization.

When accessing the device by writing to the information input 12 of the device, the information to be written to the memory is fed from address input 1! device address register 7 receives the address code, the bus 16 to the input of the control unit 10 receives the access signal, and bus 14 - the write signal. Information for recording through the second switch 5, the information register 4 main element 2 is fed to the inputs of the main drive 22 and correction unit 3, which is transmitted to the first input of the syndrome calculating unit 18, and to the second input, which is intended to receive check bits, zero the level from the output of the And 25 element. In node 18 of the syndrogate's calculation, the control bits of the Hemmming code are formed, which allow detecting and correcting single errors. The control bits from the output of the syndrome computation node 18 are fed to the inputs of the control accumulator 23. A single signal from the first output of the control unit 10 connects through the first switch 8 to the address inputs of the accumulator 1 and the input of the decoder 9 the contents of the register 7 address. Under the influence of control signals from the second and third block outputs

10 control in the drive is recording information bits and control bits of the Heming code.

In the read cycle from the address input

11 receives the address code, from the bus 16 - the circulation signal, from the bus 14 - the read signal.

The work of the address part is similar to the write cycle. Under the influence of the control signal from the second output of the control unit 10 in the drive 1, information is read at the address adopted on the address register 7. Read bits from the main 22 and control 23 drives go to the inputs of the correction block 3, where the syndrome calculating node 18 forms the Hamming code syndrome, which is decoded in the decoding ROM 19. In the presence of a syndrome corresponding to a single error, the decoder 20 is input from the decoder ROM the code corresponding to the digit in which the error was found. From the output of the decoder 20, the decoded error position code goes to the first inputs of modulator 21 modulo two, the second inputs of which receive the read information, as a result of which the information bit in which the error is detected is inverted and the error is corrected. From the output of the adder 21 modulo two corrected information is supplied to the first information output 13 of the device. Writing or reading information occurs in the first cycle of the device.

In the second cycle, the zero-level control unit 10 at the first output connects through the first switch 8 to the address inputs of the drive 1 and the decoder 9 inputs the contents of counter 6, the signal from the second output of the control unit 10 reads from the drive 1 information and control bits to block 3 correction. In block 3 of the correction, as in the reading in the first cycle, the Hamming code syndrome is formed. decoding it and (in the case of a single error syndrome) issuing from the first output of the decoding ROM 19 an error signal that enters the control unit 10 and plays the short-trigger 31, and from the second outputs of the decoder ROM 19 the code number is supplied to the inputs of the decoder 20 discharge having an error. This code is decrypted in the decoder 20 and from the outputs of the decoder 20 enters the first inputs of the adder 21, where it is modulo two with the read information, thereby correcting a single error. From the outputs of the adder 21 modulo two, the corrected information goes through the second switch 5 to the input of the information register 4 In the third device operation cycle, if there is a logical unit at the output of the C Trigger 31, the output level of the element 32 produces a unit level that goes to the control input of the information register 4 and captures in it the information that has spread during the second cycle. The unit state of the element AND 32 causes the appearance of a cynical state at the output of the element OR 29, which causes the outputs of the trunk element 2 to switch to the active state, the outputs of the element 24 to the high-impedance state, the outputs of the element 25 and 25 to the zero state due to the corresponding connections of the control unit 10 control inputs of these elements. Corrected information from the outputs of the information register 4 through the main element 2 is fed to the inputs of the drive 1 and block 3 correction.

In block 3 correction information is supplied to the first inputs of the node 18 calculations

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syndrome, the second inputs of which arrive at the zero level from the outputs of the element And 25, as a result of which the output bits of the syndrome’s 18 calculations will form the control bits of the Hamming code, which will go to the inputs of the accumulator 1. Under the influence of the unit level, the output of the element OR 30 occurs in the accumulator overwriting the corrected information to the address where the error was detected in the previous clock cycle. The regeneration of information in the device is combined with the reading of information in the second cycle and occurs regardless of the presence of a circulation signal on the bus 16.

Thus, in the proposed device, periodic control of information and correction of single errors, independent of the presence of a circulation signal, occurs, which significantly reduces the likelihood of unrecoverable double errors that can occur during long-term memory operation.

Claims (3)

Claim 1. Dynamic memory device with error correction, containing a storage unit, correction unit, data register, counter, first switch, second switch, address decoder, control unit, address register, whose inputs are device address inputs, address register outputs are connected to the first information the inputs of the first switch, the second information inputs of which are connected to the outputs of the counter, the first outputs of the first switch are connected to the inputs of the address decoder, the outputs of which are connected to the inputs and samples of the storage unit, the address inputs of the storage unit are connected to the second outputs of the first switch, the outputs of the control bits of the storage unit are connected to the inputs of the control bits of the correction unit whose information inputs are information outputs of the device, the second output of the correction unit is connected handling, synchronization and recording of which are the corresponding inputs of the device, the first output of the control unit is connected to the control input of the first the switch and the clock input of the counter, the second and third outputs of the control unit are connected respectively to the enable input and the write input of the storage unit, characterized in that, in order to simplify the device, it contains a trunk element, the inputs of which are connected to the data register, bidirectional inputs the outputs of the storage unit are connected to the outputs of the trunk element and the information bits of the correction block, the outputs of the control bits of which are connected to the inputs of the control bits of the storage block, the information inputs of the data register are connected to the outputs of the second switch, the first information inputs of the second information the inputs of the second switch are the information inputs of the device, the third fourth, fifth outputs of the control unit soy ineny respectively to the control input of the main element, the input data register and a control input of the second switch. 2. Device by π. 1, characterized in that the correction unit contains the syndrome former, the first decoder, the second decoder, modulo-two adders, whose outputs are informational outputs of the correction unit, the first inputs of the syndrome-forming unit are connected to the first inputs of modulo-two adders correction, the second inputs of the syndrome shaper are the inputs of the control bits of the correction unit, the outputs of the syndrome shaper are connected to the inputs of the first decoder and are outputs ontrolnyh discharges correction block, the second inputs of modulo two adders are connected to outputs of the second decoder, the inputs of which are connected to the first output of the second decoder, the second decoder is an output of the first output signal error correction block. 3. Device by π. 1, characterized in that the storage unit contains the first drive, the second drive, the inverter, the group of elements AND, the three-state element whose information inputs are connected to the outputs of the first drive, the inputs of the sample, the address, the resolution n of the first and second drives are connected and respectively, the inputs of the sample, addresses, resolutions and records of the block of drives, the information inputs of the second drive are the inputs of the control bits of the block of drives, the outputs of the element with three states are connected to informational inputs-outputs of the storage unit, the outputs of the second storage unit are connected to the second inputs of the And elements, the outputs of which are the outputs of the control bits of the storage unit, the second inputs of the And elements are combined and connected to the control input of the three-state element and the output of the inverter, input which is under the keys to the entry of the drive block entry. 1487103 0 ™ 1 From]. Η 5.73 2 φα & 3 1487103 figl