JPS62183063A - Synchronizing circuit - Google Patents

Abstract

PURPOSE:To attain the quick and accurate detection of the head of data and the stable protection at the missing of the head data by providing a head flag generation circuit so as to change over the synchronizing signal detection algorithm of a PCM intermittent reproducing signal and the 2nd and succeeding algorithms. CONSTITUTION:In receiving a head synchronizing signal DSYNC of a reproducing signal from a synchronizing signal detection circuit 31, a flag processing circuit 35 outputs a control synchronizing signal BSYNC. The circuit 35 hits a protection counter 38 to cause it to output a window closing signal WD1 via a window count 36 in case all conditions of a parity check flag P, an address check flag ADPF and a demodulation error check EF or the like are satisfied thereby resetting the counter 38. The counter 38 is set by the discrimination that the synchronizing signal is reliable through the detection of the succeeding two consecutive signals BSYNCs. If the detection above is failed, no signal WD1 is outputted until the signal DSYNC is detected again. Thus, the synchronizing signal is detected accurately and the stable protection is attained even when the head data is missing.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a PCM signal reproducing device, and particularly to a digital signal processing circuit suitable for use in a synchronous circuit.

[Conventional technology]

The conventional device takes into consideration the point of more accurate protection with respect to methods such as replenishment against loss of synchronization signal in the middle of a continuous reproduction signal, as described in Japanese Patent Application Laid-Open No. 58-60409. However, when the playback signal is discontinuous and intermittent, such as in a playback device using a rotating head, there is a method for detecting a synchronization signal at the beginning, and for protecting or recovering synchronization when data at the beginning is continuously lost. No consideration was given to this.

[Problem that the invention seeks to solve]

The above conventional technology does not take into account the detection of a synchronization signal at the beginning of an intermittent playback signal or the protection and recovery method in the event that data is lost at the beginning, making it difficult to accurately and quickly detect a synchronization signal at the beginning. In addition, if the data at the beginning is continuously lost, stable protection operation becomes impossible, resulting in malfunction, or there is a delay in returning to normal operation, making it impossible to capture correct data. .

The purpose of the present invention is to accurately and quickly detect a synchronization signal at the beginning of an intermittent playback signal, to provide stable protection without malfunction even when the leading data is missing, and to realize a quick return to normal operation. An object of the present invention is to provide a synchronization signal detection and protection circuit to reproduce PCM signals with greater fidelity.

[Means for solving the problem] The above purpose is to provide a leading flag generation circuit that determines the state at the beginning, and to switch between the synchronization signal detection algorithm at the beginning and the second and subsequent detection algorithms, especially when the leading state is detected. When detecting a synchronization signal, check the parity code added during recording as a detection condition.

This is achieved by using error checking during demodulation and comparison results of block address values detected from reproduced signals as detection conditions.

[Effect]

Parity check is performed when detecting the first synchronization signal.

Processing is performed on the condition that the three factors of demodulation error check and detected address check are satisfied at the same time. Therefore, the synchronization signal detected first is accurate, and even when the leading data is missing, the return to normal operation is performed accurately and quickly, and the probability of malfunction occurring is extremely low.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained with reference to FIG. WJ1 and FIG. FIG. 1 is a circuit block diagram of a PC/M reproducing apparatus using a rotary head, and FIG. 2 is a recording signal format showing the structure of a data signal generated during recording. In FIG. 2, 2 is a recording tape, and 2A is a diagram showing the signal structure of one track recorded during the time (3) when the rotary head comes into contact with the tape. The configuration of this l track is such that the signal to be recorded is transferred to P as shown in (α).
CM area and subcode area (sus-1, 5UB-z)
and the signal ATF1 for tracking servo.
, ATF2. Furthermore, the PCM area consists of 128 blocks, and 5UB1 and 5UB2 each consist of 8 blocks. As shown in (A), one block consists of a synchronizing signal S1 word, an information code IDl word, a block address BA1 word, a parity code P1 word, and data W. -1'+a+ 32 words (36 words in total). Here, the ID code is an information code provided for reproducing the mode at the time of recording, such as the sampling frequency, number of quantization bits, and tape speed, at the time of reproduction. The block address BA is an address signal assigned to each block, and is '0 to 7F' in the PCM area.
, 80-87" in the 5UB1 area,' in the 5UB2 area
88 to 8F'', and the most significant bit is set to the PCM area when it is on, and the subcode area when it is set to '1''. Moreover, the parity code P is the above-mentioned ID.

This is a simple parity code generated by performing modulo 2 addition of each bit of two words of BA.

Data W. -wtn is composed of a PCM signal input during recording or an error correction code. The configuration and operation of this embodiment for reproducing signals recorded in this manner will be described below.

Fig. 1 shows a rotating cylinder with a magnetic head attached, 2
is a magnetic tape, 22 is a playback amplifier, 21 is a servo circuit for the rotation system, tape speed system, and tracking, 10 is a circuit that generates the timing necessary to operate each circuit of the playback system, and the device is an excitation device. be. The reproduced signal read from the magnetic tape is synchronized in word units by detection of the synchronizing signal and protection against loss in the synchronizing circuit 3, and demodulated by the demodulating circuit 4. A parity check circuit 5 checks the parity added during recording from this demodulated data, and an address latch circuit 6 and an ID code latch circuit 7 latch the block address and ID code. The reliability of the latched ID code is further checked by the ID code detection circuit 8, and the current reproduction mode, such as sampling frequency or tape speed, is determined and the necessary timing is changed. Further, the result of the parity check is used as a factor for evaluating the reliability of the detected synchronization signal and the block address, and is used for detection and protection of the synchronization signal, as well as one of the conditions for block address detection and protection in the address circuit 9. Further, the captured block address BA is compared in magnitude with a memory access address CA for error detection and correction processing, which will be described later, to prevent the corrected data from being rewritten in the memory due to erroneous address detection. In addition, if the beginning of data is lost due to dropout, etc., the data to be written to memory is set to reduce the probability of false detection and false correction in error detection and correction processing (P
R5ET output) The block address thus detected and protected by the address circuit 9 is generated by the reproduction address generation circuit 17 into an address to be written into the memory, and is written into the memory 12 (for example, RAM') together with the demodulated data via the interface 11.16. The data written in the memory is then read out by the correction address generation circuit 18, error detection and correction and interpolation are performed in the correction circuit 13, and the data is written into the memory again.
The corrected data is read out by 9 and converted into an analog signal by a D/A conversion circuit 14 and output.

An embodiment of the synchronous circuit according to the present invention will be explained with reference to FIG. In the figure, the same reference numerals as in FIG. 1 indicate the same functions and the same contents. The synchronization circuit is comprised of 31 to 39 in the figure, 31 is a synchronization signal detection circuit that detects a synchronization pattern from a reproduced signal, 35 is a synchronization signal detection circuit that generates and processes various flags for protection, and various counters 33. A flag processing circuit synchronizes and corrects 34, 36, and 38, 32 is a synchronization circuit for synchronizing the synchronization signal detected by the regenerated clock with the master clock MCK by the internal crystal, and 1 word, for example, 10 bits, is generated by the regenerated clock. 34 is a word counter that extracts and counts words from the reproduced signal; 36 is a word counter that extracts and counts each word from the reproduced signal;
A window counter for generating a synchronization signal detection window and various timing clocks, 37 a decoder circuit for generating the timing clock, and 38 a frequency divider for each block, for example, 360 bits, to protect the synchronization signal detection cycle. A counter 39 is a decoder circuit for generating the protected timing clock PCK.

In the figure, 41 is a conversion circuit that converts the reproduced serial signal into a parallel signal, I2 is a latch circuit that captures the reproduced signal in word units, 43 is a cephalothorax circuit, and 45 is a latch that latches demodulated data. A circuit 44 is a demodulation error detection circuit that detects signals other than predetermined data as errors during demodulation. By the synchronization signal detection circuit 31,
The synchronization signal DSYNC detected from the reproduced signal is subjected to a timing comparison with a detection window generated at a predetermined timing by the flag processing circuit 35, and the signal detected within the detection window is used as the BSYNC signal and operated by the reproduced clock. Bit counter 33 and word counter 34 are word synchronized. This B5YNC signal is synchronized with the reproduced clock, and a synchronization circuit 32 generates a signal C3YNC which is synchronized with a master clocker Af cK using an internal crystal. This C3YNC signal sets the window counter 36 and protection counter 38, which are operated by the master clock MCK, to predetermined values. (5ET0.SET,,SET.

The flag processing circuit also processes, for example, an error flag during demodulation (EF multiplied signal, a parity flag (P signal) which is the check result of the parity code added during recording,
Based on a determination signal such as an address flag (ADHF signal), which is a comparison result of whether the detected block address value is an appropriate value preceding the address to access the memory to perform the error correction processing shown in Figure 1. Determine whether the detected BSYNC signal is correct or due to erroneous detection, and only when it is determined that it is a correct synchronization signal, set the counters 36 and 38 to a predetermined value again (SET, signal) . In this way, the detected synchronization signal DS
The window counter 36 corrected based on YNC is decoded by the decoder circuit 37 to produce the ID code shown in FIG.
Latch clock IDCK of block address BADR,
ADRCK is generated, a parity check clock prcx is generated at a predetermined timing, and the aforementioned detection window opening signal WDo and closing signal TI'Dl are generated.
And if the DSYNC signal is not detected within the detection window, the NSYNC signal is decoded and generated. As shown in Fig. 2, when DSYNC is detected at a cycle consisting of 360 bits per block, this window counter is designed to divide the branch station by 360 or more, for example by a maximum of 370, and the detection window is ±3 bits. In order to detect DSYNC at the center during normal operation, the WD0 signal is generated by decoding the position 357 of the window counter, and the WDl is generated by decoding the position 363 of the window counter. Originally, B5YNC is detected at position 360, and C3YNC is delayed by one clock further in the synchronization circuit, so SET
, loads 2' with the signal and closes the detection window. Also, when ESYNC is not detected, the window counter does not receive the 5ETl signal and continues counting.
When reaching 64, the FD signal is generated and the detection window closes, and further when reaching e.g. 367,
The N5YNC signal is generated and the window counter is loaded with '8'' to keep the frequency divided by 360. Also, the protection counter is made to constantly maintain the frequency divided by 360, which is the length of one block, and the flag is set. Through processing, a reliable detected synchronization signal is determined and corrected (5ET0.
SET.

SE T'3). Furthermore, by decoding this protection counter, a clock PCK whose period and timing of one block are protected is generated.

Next, the flag processing circuit will be explained in detail.

FIG. 4 shows an embodiment of the flag processing circuit according to the present invention. In the figure, the same signal names as in FIG. 3 represent the same signals having the same functions. Further, 352 is the aforementioned detection window generation circuit;
357 is an AND gate that detects whether or not DSYNC exists within the detection window; 353 is a first head flag (abbreviated as F1 flag) generation circuit that identifies the beginning of reproduced data; and 354 is a second head flag. A generation circuit 355 (abbreviated as F2 flag) is a generation circuit 356 for a flag (abbreviated as A flag) that identifies the state in which BSYNC is detected.
is when ESYNC is not detected, i.e. N5YN
351 is a generation circuit for a flag (abbreviated as "t flag") for identifying when a C signal is detected.
How to set the window counter and protection counter depending on the status of the Ie flag and the P, EF, ADH7 lags and the presence or absence of the C5YNC, WDo, and WDl signals.
5ET0 to 5ET3) and sets or resets various flags in order to determine the processing method for synchronization signal detection protection in the next block. 1. An example of the processing algorithm of this control circuit is shown in the flowchart of FIG. First, the control circuit initializes each flag to its initial state, as shown at the input terminal 35D in FIG. do. For example, F.
Flag=ON, F, Flag=ON%A,)5g=OFF
,A,”:)'yg=OFF.

Detection window=ON. Furthermore, a conditional algorithm for detecting the first synchronization signal at the beginning using the FIl flag;
Switches the second and subsequent detection algorithms. In other words, when the first synchronization signal is detected, the protection counter should be set only once by the first BSYNC (5ET0).
Parity check (P flag), address check (
ADRF flag) and demodulation error check (EF), the detection window and Fl flag are turned OFF and the protection counter is set again. (SET
, ) The second and subsequent synchronization signal detection protection processes are as follows:
When BSYNC is detected twice in a row due to the synchronization flag, the protection counter is set as a sufficiently reliable synchronization signal (5ET1). Also, two consecutive B
If SYNC is not detected, the timing to open the detection window may be off from the predetermined timing when DSYNC should occur, so do not close the detection window and open the DS next time.
Leave the windows open until YNC occurs.

With the above processing, it is possible to accurately detect and protect the synchronization signal at the beginning of data, and to quickly pull in the synchronization signal and perform synchronization even if the beginning data is lost.

In order to explain this effect, specific operational examples of the synchronous circuit according to the present invention are shown in FIGS. 6 and 7. (1) in the diagram
is a signal representing the beginning of an intermittent reproduction signal, (2
) is an area signal indicating the data area in the reproduced signal (1), and S0 to S in (3) indicate the timing indicating the position of the synchronization signal that should originally exist. Also, the first
The same reference numerals and the same signal names shown in FIGS. 5 to 5 have the same functions and the same contents. Each of the flags (6) to (9) and the detection window are initially set by the falling point signal srp of the area signal, and the Ftl flag is turned OFF by DSYNC and Do for the first synchronization signal S0.
The window counter and protection counter are set (SET,
, 5ET0) Furthermore, the detection window and F, flag are set to 0 when the parity, address, and demodulation error checks are satisfied.
At the same time, the protection counter is set (SE
T,) will be done. Thereafter, the window counter is corrected (SET, ) by the DSYNC detected within the detection window, and counted up based on this. BSYNC towns that do not fall within the detection window are determined to be due to this detection, and no processing is performed. For example, DS for S
Even if YNC is missing and not detected, it is set so that the frequency division by 360, which is one block length, is maintained by generating NSYNC as described above. Since DSYNC is not detected twice in a row at the position indicated by T in (5), the detection window does not close until the next DSYNCD6 is detected. Furthermore, due to the detection of D6, the window counter is set (
5ET1), but the protection counter is DSY immediately after recovery.
DS is not set by NC and is detected by the next open detection window.
Set (SET, ) by YNCD. As a result, the protection counter data (PCK, P0 to P?) can maintain an accurate l block length cycle and generation timing.

FIG. 7 is a timing diagram showing the operation when the leading part of the reproduced signal is lost due to dropout or the like. fl
When a dropout like the one shown in + occurs, it is not only the loss of the synchronization signal, but also the DS YNC- ~ 几 due to false detection.
It also occurs frequently. The operation in such a case is to first detect DSYNCn after each flag is initially set by srp. Set the protection counter (SET
. ) At the same time, the F flag is turned OFF, and the setting of the protection counter for 1 to G is stopped. This will cause the protection counter to be set on false detection DSYNC (
This random generation of the timing signal PCK can be suppressed, and one PCK per block can be stably generated at a cycle of one block length. However, the protection counter 5ET
o is due to false detection DSYNCno, so
The timing of occurrence of p c x po, p,, p, is out of order.

This situation occurs because the first three blocks of data are missing as shown in the figure, and in this case, the data cannot be imported correctly, so the number of PCK occurrences corresponds to the number of blocks. If it is stable and stable, it will not cause any problems.

Assuming that the data is correctly reproduced starting from the 4th block and the detection synchronization signal is also detected correctly, the result is:
At T1, the parity, address, and demodulation error check flags work normally, and with these results, close the F1 flag and set the protection counter.
), the return to normal operation is quick, and at the same time, the reliability is very high because the three flags are checked. Therefore, it is possible to obtain the protection clock PCK that has returned to normal from T3 of the fourth block where normal data begins to be obtained.

FIG. 8 shows an embodiment of the flag processing circuit of the synchronous circuit according to the present invention. In the figure, the same signal names as in FIG. 4 are the same signals having the same functions as described above. Also, 3510. 35
11 is a latch circuit, 4400 is a shift register, and the others are gate circuits. Furthermore, the detection window generation circuit is 3521
~3523, and the F1 flag generation circuit is 3561
, 3562, F, flag generation circuit is 354135
42, A1 flag generation circuit is 3551. 3552
．． The flag generation circuit is 3561. 3562. Control circuits are 3510-3519 and 4400,
4401, 5000. Composed of 3571
is a circuit corresponding to the gate circuit 357 in FIG. Here, various flag generation circuits including the detection window generation circuit are NAN
This is realized by a set/reset flip-flop circuit using a D gate, and latch circuits 3510 and 3511 are circuits for processing each flag and controlling the timing of the SET signal. Furthermore, games 1-3512 to 3518 are logic circuits for performing the condition determination process shown in FIG.
The parity, address, and demodulation error flags are processed by a latch circuit 4400 and gates 4401 and 5000, and the output of the gate 5000 becomes "H" level when all three flags satisfy the conditions. Also, input AC5
teeth.

By inputting an H" level signal when requesting special playback such as access, gates 3523 and 351
9 is a control signal for turning on the entire detection window and switching the processing algorithm of the synchronous circuit so that only the processing at the beginning shown in FIG. 5 is executed.

〔Effect of the invention〕

According to the present invention, the synchronization signal detection protection operation can be performed accurately at the beginning of data, and even if the data at the beginning is lost, the synchronization signal can be pulled in accurately and quickly without causing malfunction. Since normal operation can be restored, more faithful PCM signals can be reproduced.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram showing an embodiment according to the present invention;
FIG. 2 is a data format diagram of a recording signal, and FIG. 3 is a circuit block diagram showing an embodiment of a synchronous circuit according to the present invention.
FIG. 4 is a circuit block diagram showing an embodiment of the flag processing circuit of the synchronous circuit according to the present invention, FIG. 5 is a flowchart diagram showing an embodiment of the processing algorithm of the flag processing circuit according to the present invention, and FIGS. FIG. 7 is a timing diagram showing the operation of the synchronous circuit according to the present invention, and FIG. 8 is a circuit diagram showing an embodiment of the flag processing circuit according to the present invention. ■...Demodulation error detection circuit 31...Synchronization signal detection circuit 32...Synchronization circuit A...Bit counter A...Word counter 36...Window counter blade...Protection counter 37, 39 ... Decoder circuit 35 ... Flag processing circuit 352 ...
・Detection window generation circuit 353...F, flag generation circuit 3
54...F, flag generation circuit 355...A, flag generation circuit 356...Flag generation circuit 351...
Control circuit agent Patent attorney Masaru Ogawa 3 2 mouths zA (α) Trazuku 7 years old - Maaμ (b) Fu”Dtsufufu mat 1 4 mouths

Claims (1)

[Claims] 1. Divide data into blocks, and send a block synchronization signal and a block address code for each block;
An ID code for control information, a block address code, and a parity code generated for checking the ID code are added, and when reproducing data on a recording medium recorded in units of multiple blocks, the synchronization signal is extracted from the reproduction signal. Detects and synchronizes the reproduced signal in word units consisting of a predetermined plurality of bits to capture data in word units, and generates a timing signal to capture the block address and ID code and a timing signal to check the parity code. A detection protection circuit for a synchronization signal that detects the synchronization signal, a protection signal generation circuit that generates the protected timing signal even when the synchronization signal cannot be detected, and a protection signal generation circuit that generates the protected timing signal even when the synchronization signal cannot be detected; Includes a detection window generation circuit that opens and closes near the timing, a head flag generation circuit that determines the state in which a synchronization signal is detected first in a predetermined area where playback data is to be input, and an output of the head flag circuit. A synchronous circuit comprising: a flag processing circuit that receives a plurality of flag signals as input; and the flag processing circuit switches between a leading synchronous signal detection algorithm and a synchronous signal detection/protection process based on the output of the leading flag circuit. . 2. Divide the data into blocks, and send a block synchronization signal and block address code to each block.
An ID code for control information, a block address code, and a parity code generated for checking the ID code are added, and the synchronization signal is detected from the playback signal when reproducing data recorded in units of multiple blocks. A synchronization signal that synchronizes signals in word units consisting of a predetermined plurality of bits to capture data in the word units, and generates a timing signal to capture the block address and ID code and a timing signal to check the parity code. The detection/protection circuit includes a circuit that detects the synchronization signal, a protection signal generation circuit that generates the protected timing signal even when the synchronization signal cannot be detected, and a vicinity of a predetermined timing at which the synchronization signal is to be detected. A detection window generation circuit that opens and closes with a detection window generation circuit, a parity check circuit that checks the parity, and a flag processing circuit that receives as input a plurality of flag signals including the output of the parity check circuit, and the flag processing circuit checks the parity. A synchronous circuit characterized in that an output signal of the circuit is used as a detection condition for the synchronous signal, and synchronization or protection processing is performed according to a result of condition determination. 3. In claim 1 or 2, the flag processing circuit opens the detection window before the timing at which the first synchronization signal is to be detected, and when the first synchronization signal is detected, the detected synchronization signal is detected. closing the detection window when the signal and the output signal of the parity check circuit reach a predetermined result, and synchronizing the protection signal generation circuit;
When detecting the second and subsequent synchronization signals, the protection signal generation circuit is synchronized when a synchronization signal is detected in multiple consecutive blocks, and when the synchronization signal is not detected in multiple consecutive blocks, the detection window is A synchronous circuit characterized in that it is controlled not to close until the next synchronous signal is detected. 4. Divide the data into blocks, and send a block synchronization signal and block address code to each block.
An ID code for control information, a block address code, and a parity code generated for checking the ID code are added, and the synchronization signal is detected from the playback signal when reproducing data recorded in units of multiple blocks. A synchronization signal that synchronizes signals in word units consisting of a predetermined plurality of bits to capture data in the word units, and generates a timing signal to capture the block address and ID code and a timing signal to check the parity code. The detection/protection circuit includes a circuit that detects the synchronization signal, a protection signal generation circuit that generates the protected timing signal even when the synchronization signal cannot be detected, and a vicinity of a predetermined timing at which the synchronization signal is to be detected. When demodulating the detection window generation circuit and the playback signal,
A demodulation error detection circuit that checks errors in an input reproduced signal and a flag processing circuit that receives a plurality of flag signals including the output of the demodulation error detection circuit are provided, and the flag processing circuit is connected to the demodulation error detection circuit. A synchronization circuit characterized in that the output signal of is used as a detection condition for the synchronization signal, and synchronization or protection processing is performed depending on the result of condition determination. 5. In claim 1 or 4, the flag processing circuit opens the detection window before the timing at which the first synchronization signal is to be detected, and when the first synchronization signal is detected, the flag processing circuit opens the detection window before the timing when the first synchronization signal is to be detected. and when the output signal of the demodulation error detection circuit reaches a predetermined result, the detection window is closed and the protection signal generation circuit is synchronized, and the second
When detecting a synchronization signal after the number, the protection signal generation circuit is synchronized when a synchronization signal is detected in multiple blocks in a row, and when a synchronization signal is not detected in multiple blocks in a row, the detection window is synchronized to the next one. A synchronous circuit that is controlled so as not to close until a signal is detected. 6. Divide the data into blocks, and send a block synchronization signal and block address code to each block.
An ID code for control information, a block address code, and a parity code generated for checking the ID code are added, and the synchronization signal is detected from the playback signal when reproducing data recorded in units of multiple blocks. A synchronization signal that synchronizes signals in word units consisting of a predetermined plurality of bits to capture data in the word units, and generates a timing signal to capture the block address and ID code and a timing signal to check the parity code. The detection/protection circuit includes a circuit that detects the synchronization signal, a protection signal generation circuit that generates the protected timing signal even when the synchronization signal cannot be detected, and a vicinity of a predetermined timing at which the synchronization signal is to be detected. a detection window generation circuit that opens and closes with A flag processing circuit is provided that receives a plurality of flag signals including the output, and the flag processing circuit uses the output signal of the address comparison circuit as a detection condition for the synchronization signal and performs synchronization or protection processing according to the result of condition determination. A synchronous circuit characterized by: 7. In claim 1 or 6, the flag processing circuit opens the detection window before the timing at which the first synchronization signal is to be detected, and when the first synchronization signal is detected, the detected synchronization signal is detected. When the signal and the output signal of the address comparison circuit reach a predetermined result, the detection window is closed and the protection signal generation circuit is synchronized, and the second
When detecting a synchronization signal after the first block, when a synchronization signal is detected in multiple blocks in a row, the protection signal generation circuit is synchronized, and when a synchronization signal is not detected in multiple blocks in a row, the detection window is set to the next one. A synchronous circuit characterized in that it is controlled not to close until a synchronous signal is detected.