JPH0258709B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal recording and reproducing device, which prevents frame synchronization signal detection errors and false detections caused by dropouts and the like when reproducing a digitally recorded recording medium, and prevents missing data. The aim is to minimize the

FIG. 1 is an example of a generally proposed recording format. The digital signal to be recorded is divided into a fixed number of parts, and a frame synchronization signal (SYNC
The frame is constructed by adding a CRC (cyclic code) to detect errors in the data portion (DATA in the figure) and the data portion (DATA in the figure).

Figure 2 is a configuration diagram of a conventional frame synchronization signal separation circuit that detects a frame synchronization signal from a digital signal string reproduced from a recording medium according to the format shown in Figure 1, and Figures 3A to 3E are timing diagrams of signals in each part of the circuit. It's a chat.

In FIG. 2, a reproduced digital signal is input to terminal 1, and a clock signal extracted from the digital signal is input to terminal 2.
3 is a shift register, and the input serial digital signal is read in synchronization with a clock signal, returned in parallel, and appears at the output of the shift register 3. Reference numeral 4 denotes a frame synchronization signal detection circuit composed of a digital comparator or ROM, etc., which detects the pattern of the frame synchronization signal in the reproduced digital data to obtain an output signal (H level in the figure). 5 is the first counter circuit;
Appears at the output terminal 14 of the 1AND gate circuit 6
After being reset by the SYNC signal and counting a preset number of clock signals, an H level is obtained at the output and applied to the input of the first AND gate circuit 6.

In other words, since there is a possibility that the same pattern as the frame synchronization signal pattern is detected in the data part or the CRC part, focusing on the regularity of the frame synchronization signal, once the SYNC signal is detected, the first counter Reset circuit 5 to start counting the clock and read the data or CRC.
Even if the same pattern as the frame synchronization signal is detected in the section, the first AND gate circuit 6 is closed until the first counter circuit 5 counts a certain number (K bits in FIG. 3) of clock signals.
The configuration is designed to prevent erroneous detection of the SYNC signal.

Now, consider a case where, in the conventional circuit configuration, a dropout or the like occurs in the SYNC signal portion and a normal SYNC signal is not reproduced. In FIG. 4, if the Nth frame SYNC signal is not normally reproduced, the AND gate signal D is not reset and remains at H in the Nth frame section. If in the data of the Nth frame or
If a pattern similar to the SYNC signal is detected in the CRC part, that part is determined to be the SYNC signal, and the AND gate signal D is reset.
The SYNC signal is not detected after the frame, and it usually takes several frames to return to the so-called normal synchronization pull-in state. If the SYNC signal is not detected over several frames after the Nth frame, it will be difficult to properly process the data during that time, such as controlling writing to the memory for absorbing wow and flutter, resulting in serious data loss. There was a drawback.

The present invention was provided for the purpose of solving such conventional problems.

The invention will now be described in detail with reference to illustrated embodiments. FIG. 5 is a block diagram showing the first embodiment of the present invention, and FIG. 6 shows its time chart.

The operation will be explained below with reference to FIG.
6 is the same as the operation of each part in FIG. 2, so a description thereof will be omitted.

The SYNC signal output from the first AND gate circuit 6 passes through the first OR gate circuit 7 to the output terminal 8.
is output to. 9 is a second counter circuit which, after counting the clock signal by the number of bits composing the frame (M bits in the figure), performs the first OR on the output signal.
The signal is configured to be output to the gate circuit 7.

Further, the output of the first OR gate circuit 7 is applied to the reset inputs of the first and second counter circuits 5 and 9. Normally, when a correct SYNC signal is detected, the output of the first AND gate circuit 6 passes through the first OR gate circuit 7 and is output to the output terminal 8, and the second counter circuit 9 is always reset by the SYNC signal. is used to count the clock signals. When the second counter circuit 9 has a clock-synchronous reset terminal, an output signal can be obtained at the same timing as the SYNC signal serving as the reset signal.

Furthermore, if the second counter circuit 9 has a reset terminal that is asynchronous to the clock, it will be reset at the moment the counter output is obtained, so it will not function normally.
If the SYNC signal is being output, the output of the second counter circuit 9 cannot be obtained, but in either case, a normal SYNC signal can be obtained from the output terminal 8.

Now, considering the case where a normal SYNC signal is not detected due to dropout or the like, the second counter circuit 9 outputs an output signal to the first OR gate circuit 7 at a frame position where a normal SYNC signal is obtained, and the output signal is is obtained from the output terminal 8 as a pseudo SYNC signal instead of a normal SYNC signal.

Furthermore, since the second counter circuit 9 is configured to be reset again by its own output signal, even if the SYNC signal fails to be detected continuously, it is possible to continuously obtain a pseudo SYNC signal. can.

Furthermore, the first counter circuit 5 that generates the gate signal for detecting the original correct SYNC signal is connected to the second counter circuit 5.
Like the counter circuit 9, it is reset by the signal at the output terminal 8, so even if the SYNC signal fails to be detected, it is forcibly reset by the pseudo SYNC signal, the gate signal is closed, and the data and CRC are reset. Erroneous SYNC signal detection due to the same pattern as the SYNC signal inside can be prevented.

FIG. 7 is a block diagram showing a second embodiment of the present invention, and FIG. 8 shows a time chart of each part thereof.
Note that 1 to 9 in FIG. 7 are the same as described above, so their explanation will be omitted.

10 is a pulse generation circuit composed of a monostable multivibrator, a counter, a shift register, etc.
Using the SYNC signal output as a trigger input, a pulse signal with a preset constant width is obtained at its output. The output of the pulse generation circuit 10 is sent to the second OR gate circuit 11
This signal becomes a reset signal for the first and second counter circuits 5 and 9. In this configuration, normal SYNC
When the signal is obtained as the output of the first AND gate circuit 6, the output of the pulse generation circuit 10 becomes the reset signal for the first and second counter circuits 5 and 9, and when a normal SYNC signal is not obtained, ,
At the same time the output of the second counter circuit 9 becomes a pseudo SYNC signal, the output of the first and second counter circuits 5, 9
It becomes a reset signal.

However, in this case, the position where the pseudo SYNC signal, that is, the output signal of the second counter circuit 9 is output, is slightly wider than the position where the normal SYNC signal is expected to be output by the preset output pulse width of the pulse generation circuit 10. Naturally, the reset of the first counter circuit 5 is delayed by that period, and as a result, the period during which the first AND gate circuit 6 is open can be extended.

According to this method, from the time when a normal SYNC signal becomes undetected until the pseudo SYNC signal is generated,
By providing a certain delay time,
Even if there is some discontinuity in the SYNC signal, the SYNC signal can be reliably detected. This means that, for example, when performing electronic editing in which new data is recorded in consecutive frames on top of an already recorded tape, even if there is some discontinuity in the frames before and after editing, According to this method, it is possible to
SYNC signal can be detected.

FIG. 9 shows a third embodiment of the present invention, and FIG. 10 shows a time chart of each part thereof. In addition, 1~
The operations up to step 9 are the same as described above, and will therefore be omitted.

Reference numeral 12 denotes a second AND gate circuit, which gates the output of the second counter circuit 9 using the output of the start/stop detection circuit 13. data start
For example, the stop detection circuit 13 opens the second AND gate circuit 12 when it determines that a preset number of normal SYNC signals are consecutively detected from the reproduced data, and conversely, the stop detection circuit 13 opens the second AND gate circuit 12 when a preset number of normal SYNC signals are detected consecutively from the reproduced data. For example, it is configured by a counter or the like so as to obtain a control output that closes the second AND gate circuit 12 upon determining that a set number of objects have not been detected.

That is, according to the configurations shown in FIGS. 5 and 7, even if no SYNC signal is detected from the reproduced data, a pseudo SYNC signal is obtained by the counting operation of the second counter circuit 9, and the pseudo SYNC signal is obtained by the counting operation of the second counter circuit 9.
The first counter circuit 5 is reset by the signal,
The first AND gate circuit 6 is designed to be open only for a certain period of time.

In this case, the periodicity of the data or SYNC signal is significantly discontinuous before and after the connection point, such as when transitioning from an unrecorded part of the tape to a recorded part, or for example at a hand stamped editing connection point in the middle of a recorded part. Since the detection period of the SYNC signal is short at the location where , it is conceivable that so-called period pull-in may take time or become difficult.

However, in this case, by providing the data start/stop detection circuit 13, normal
The second counter circuit 9 generates a pseudo SYNC signal only when SYNC signal detection is performed continuously. As a result, the time required to start data or to pull in synchronization at a discontinuous point is the same as the conventional circuit system, and if a normal SYNC signal is not detected, a pseudo SYNC signal can be generated. This makes it possible to keep the data error interval to a minimum.

As described in detail in the embodiments above, according to the present invention, when reproducing a digitally recorded recording medium, continuous failure to detect a frame synchronization signal (SYNC signal) and false detection due to dropout, editing, etc. can be prevented. As a result, it is possible to minimize data missing sections due to dropouts, which is extremely valuable.

[Brief explanation of the drawing]

Figure 1 is a diagram showing an example of a recording format, Figure 2 is a configuration diagram of a conventional frame synchronization separation circuit, Figure 3 is its timing chart, and Figure 4 is a case in which dropout occurs in a conventional frame synchronization separation circuit. 5 is a block diagram showing the first embodiment of the present invention, FIG. 6 is a timing chart thereof, FIG. 7 is a block diagram showing the second embodiment of the present invention, and FIG. 8 is a timing chart thereof. 9th
The figure is a configuration diagram showing the third embodiment, and FIG. 10 is a timing chart thereof. 3...Shift register, 4...Frame synchronization signal detection circuit, 5...First counter circuit, 6...First counter circuit
1AND gate circuit, 7...1st OR gate circuit, 9
...Second counter circuit, 10...Pulse generation circuit, 11...Second OR gate circuit, 12...No.
2AND gate circuit, 13...Data start
Stop detection circuit.

Claims (1)

[Scope of Claims] 1. A frame synchronization signal detection circuit that divides a digital signal sequence into a fixed number of frames, records them with a frame synchronization signal added thereto, and detects the pattern of the frame synchronization signal during playback. A frame synchronization signal is extracted from the reproduced digital signal by a frame synchronization separation circuit comprising a frame synchronization signal detection protection circuit that inhibits output from the frame synchronization signal detection circuit for a certain period of time to prevent false detection. In the digital signal recording and reproducing apparatus configured, there is provided a counter circuit for obtaining an output signal by counting the clock signal extracted from the reproduced digital signal by the number of bits constituting the frame, and separating the output signal of the counter circuit and the frame synchronization. a first OR gate circuit which receives an output signal from the circuit as an input signal, and uses the output signal of the first OR gate circuit as a reset signal for the frame synchronization signal detection protection circuit and the counter circuit. A digital signal recording and reproducing device comprising: a circuit; and a counter circuit. 2. A frame synchronization signal detection circuit that divides a digital signal sequence into a fixed number of frames, records them with a frame synchronization signal added thereto, and detects the pattern of the frame synchronization signal during playback; and the frame synchronization signal detection circuit. A digital signal recording and reproducing device configured to extract a frame synchronization signal from a reproduced digital signal using a frame synchronization separation circuit comprising a frame synchronization signal detection protection circuit that prevents false detection by inhibiting output from the digital signal for a certain period of time. In the apparatus, a counter circuit obtains an output signal by counting the clock signal extracted from the reproduced digital signal by the number of bits constituting the frame, and an output signal of the counter circuit and an output signal from the frame synchronization separation circuit. a first OR gate circuit that receives as an input signal, a pulse generation circuit that uses the output signal from the frame synchronization separation circuit as a trigger to obtain an output signal with a pulse width of a fixed time, and an output signal of the pulse generation circuit. and a second OR gate circuit which receives as input the output signal of the first OR gate circuit, and uses the output signal of the second OR gate circuit as a reset signal for the frame synchronization signal detection protection circuit and the counter circuit. A digital signal recording and reproducing device comprising a signal detection protection circuit and the counter circuit. 3. A frame synchronization signal detection circuit that divides a digital signal sequence into a fixed number of frames, records them with a frame synchronization signal added thereto, and detects the pattern of the frame synchronization signal during playback; and the frame synchronization signal detection circuit. A digital signal recording and reproducing device configured to extract a frame synchronization signal from a reproduced digital signal using a frame synchronization separation circuit comprising a frame synchronization signal detection protection circuit that prevents false detection by inhibiting output from the digital signal for a certain period of time. The apparatus includes a counter circuit which obtains an output signal by counting the clock signal extracted from the reproduced digital signal by the number of bits constituting the frame, and a counter circuit which obtains an output signal by counting the clock signal extracted from the reproduced digital signal by the number of bits constituting the frame; 1OR gate circuit, the output signal of the first OR gate circuit is applied to the frame synchronization signal detection protection circuit and the counter circuit as a reset signal for the frame synchronization signal detection protection circuit and the counter circuit, and the output signal of the first OR gate circuit is applied to the frame synchronization signal detection protection circuit and the counter circuit. A data controller configured to obtain a control output by determining whether or not a preset number of output signals of the separation circuit are continuously detected.
comprising a start/stop discrimination circuit, and an AND gate circuit whose input signals are a control output signal of the discrimination circuit and an output signal of the counter circuit;
A digital signal recording and reproducing device characterized in that the output of the gate circuit is inputted as the other input signal of the first OR gate circuit. 4. A frame synchronization signal detection circuit that divides a digital signal sequence into a fixed number of frames, records them with a frame synchronization signal added thereto, and detects the pattern of the frame synchronization signal during playback; and the frame synchronization signal detection circuit. A digital signal recording and reproducing device configured to extract a frame synchronization signal from a reproduced digital signal using a frame synchronization separation circuit comprising a frame synchronization signal detection protection circuit that prevents false detection by inhibiting output from the digital signal for a certain period of time. The apparatus includes a counter circuit which obtains an output signal by counting the clock signal extracted from the reproduced digital signal by the number of bits constituting the frame, and a counter circuit which obtains an output signal by counting the clock signal extracted from the reproduced digital signal by the number of bits constituting the frame; a 1OR gate circuit, a pulse generation circuit configured to obtain an output signal of a constant time pulse width by obtaining the output signal from the frame synchronization separation circuit as a trigger, and an output signal of the pulse generation circuit and the first OR gate circuit. The output signal of the second OR gate circuit which inputs the output signal of a data start/stop discrimination circuit configured to obtain a control output by determining whether or not a predetermined number of output signals of the separation circuit have been continuously detected; a control output signal of the discrimination circuit; Comprising an AND gate circuit whose input signal is the output signal of the counter circuit,
A digital signal recording and reproducing apparatus characterized in that the output of the AND gate circuit is inputted as the other input signal of the first OR gate circuit.