JPS628859B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a data reproducing circuit, and an object of the present invention is to provide a data reproducing circuit that detects signal loss, invalidates a series of data, and outputs only correct data to an external circuit. shall be.

The present applicant has developed an electrode function in which the main information signal and the reference signal for tracking control to accurately trace the reproducing needle to the information signal bits are recorded as changes in the geometric shape, without first forming a needle guide groove. The main information signal and tracking control reference signal are read and reproduced as changes in capacitance by relative sliding scanning between a disk-shaped information recording medium (hereinafter referred to as disk) and a reproduction needle having an electrode function. proposed a playback device.
In addition, in the above-mentioned disk, the video signal is recorded as the main information signal in 4 fields per revolution on the spiral main track, and the main information signal is recorded at, for example, 17H from the fall of the vertical synchronization signal during the vertical retrace period. The chapter data representing the number, and the time data representing the recording position (address) of the main information signal at the 18th H are data of 1 and 0 as shown in Figure 1A, respectively, and the biphasic code (hereinafter referred to as FM code) and recorded.

FIG. 2 shows an example of a block system diagram of a data reproducing circuit of an information recording medium reproducing apparatus previously proposed by the present applicant. The FM code recorded on the disk as shown in FIG. 1B is converted into an electrical signal by a reproducing needle, and further demodulated as a video signal (not shown). The PCM signal (FM code) multiplexed in a specific horizontal scanning period within the vertical retrace period of the demodulated video signal passes through an appropriate data extraction circuit (not shown) and is converted into a digital signal as shown in FIG. 1B. It becomes a series signal and enters the input terminal 1 as shown in FIG. In the figure, the FM code b is supplied to the clock regeneration circuit 2 to reproduce the clock signal c synchronized with the data cycle as shown in FIG. A data signal d as shown in FIG. 1D is obtained. The data signal d is sent to the memory 5, such as a shift register, using the clock timing of the clock signal c taken out from the clock regeneration circuit 2 via the clock switching circuit 4, and is stored in an NRZ as shown in FIG. 1E.
The signal is taken in as a signal and taken out to an external circuit from the terminal 10 as necessary.

The data string shown in FIG. 1A includes, for example, a 1H cycle framing code to delimit data blocks, and when the clock regeneration circuit 2 and data regeneration circuit 3 operate correctly, the PCM signal input to terminal 1 is is correctly reproduced from the disc, the framing code detection circuit 6 detects the framing code, and a detection signal is taken out from the framing code detection circuit 6 to set the flip-flop 7. flipflop 7
By setting , a ready signal for informing an external circuit (not shown) that the data has been correctly demodulated and entered into the memory 5 is taken out from the output terminal 8, while the clock switching circuit 4 is connected to the clock regeneration circuit 2 side. The terminal is switched from to the terminal 9 side. The external circuit is supplied with a read clock from terminal 9 in response to a ready signal, and reads out the data stored in memory 5 from terminal 10. When the external circuit finishes taking in the data in the memory 5, it applies a reset signal to the terminal 11 and resets the flip-flop 7.

However, according to this circuit, if the playback signal is lost due to a dropout or the like during disk playback, if clock playback continues,
There is a problem that data may be erroneously reproduced or a different framing code may be extracted by the framing code detection circuit 6. This cannot be completely removed by a framing code check or parity check.

The present invention solves the above problems, and one embodiment thereof will be described with reference to FIG. 3 and the following figures.

FIG. 3 shows a block system diagram when an embodiment of the data reproducing circuit according to the present invention is applied to an information recording medium reproducing apparatus. In the figure, the same parts as in FIG. 2 are given the same numbers. In the figure, the pulse cycle detection circuit 12 is set with a pulse cycle T _L that is larger than the data cycle T of the FM code b shown in FIG. 1B. First, the normal condition as shown by the solid line in Figure 1B
When the FM code b is received and the regenerated clock is being regenerated at a constant period T, nothing is taken out from the detection circuit 12, and the operation is the same as the circuit shown in the second diagram.

If a dropout b' occurs in the signal b as shown by the broken line in FIG. I end up. The L level period of the clock C including this period is longer than the data period T. This L
The level period is detected by the detection circuit 12, and a horizontal scanning period detection signal including this data period is outputted, which passes through the OR circuit 13 to reset the flip-flop 7.

Therefore, the missing data due to dropout etc.
If a PCM signal comes in and incorrect data is played,
Furthermore, even if an incorrect framing code is detected as a result, the ready signal is not taken out from the flip-flop 7, and the demodulated data until the next correct framing code is detected after correct data is received is invalidated. be done. That is, since the framing code exists in 1H period, for example, if a dropout occurs in the signal of the 17th horizontal scanning period, only the 17th demodulated data is invalidated.

In FIG. 3, the pulse period detection circuit 12, OR circuit 13, and flip-flop 7 are actually retriggerable monostable multivibrator 1 as shown in FIG.
4. It is composed of D-type flip-flops 15 and 16, and the pulse period of the retriggerable monostable multivibrator 14 is set to the above-mentioned T _L. When a dropout or the like occurs, the Q of the flip-flop 15 is set by the output ₂ from the multivibrator 14, so that the flip-flop 16 receives the framing code detection signal from the C terminal after the flip-flop 15 is set. Also, Q output is not taken out. In addition,
The flip-flop 15 is reset at regular intervals by a horizontal synchronizing signal.

In order to prevent the ready signal from being taken out when a missing PCM signal is received, in addition to not setting the flip-flop 7 even if the framing code detection signal is taken out as in this embodiment, the framing A method of providing a gate circuit between the code detection circuit 6 and the flip-flop 7 to prevent the gate circuit from operating when incorrect data is received, a method of preventing the detection signal from being taken out from the framing detection circuit, memory 5
One possible method is to clear the contents themselves.

The above explanation uses a disk example, but VTR
It operates in exactly the same way even if the reproduced signal is as follows.
Also, PCM signals multiplexed with television signals or PCM recorded on audio magnetic tape, etc.
It is clear from the explanation in the text that a signal may also be used.

As mentioned above, the data reproducing circuit according to the present invention has the following features:
Since a means is provided to detect a clock drop and invalidate a series of demodulated data corresponding to the digital time-series signal that is missing due to this detection, even if erroneous data is reproduced due to a dropout, parity check or It has the advantage of being able to check for erroneous reproduction of data more easily and more reliably than by means such as thumb checking of data.

[Brief explanation of the drawing]

1A to 1F are signal waveform diagrams for explaining the operation of the circuit of the present invention, FIG. 2 is a block system diagram of an example of an information recording medium reproducing device previously proposed by the applicant, and FIG. 3 is a diagram of the circuit of the present invention. FIG. 4 is a block system diagram of one embodiment, and is a specific circuit diagram of a part of the circuit shown in FIG. 1...Digital time series signal input terminal, 2...Clock regeneration circuit, 3...Data regeneration circuit, 5...
Memory, 6...Framing code detection circuit, 7
... Flip-flop, 8 ... Ready signal output terminal, 10 ... Data output terminal, 12 ... Pulse period detection circuit, 13 ... OR circuit, 14 ... Retriggerable monostable multivibrator, 15, 16 ...
...D-type flip-flop.

Claims (1)

[Claims] 1. When obtaining demodulated data by reproducing a clock having a period corresponding to the bit period of the signal from a digital time series signal, means for detecting a framing code included in the signal; In a data reproducing circuit having a means for notifying the outside that the clock has been demodulated, a means for detecting the clock dropout, and a series of demodulated data corresponding to the digital time series signal in which the clock dropout is caused by detecting the clock dropout. What is claimed is: 1. A data reproducing circuit characterized in that the data reproducing circuit is provided with means for 2. The digital time-series signal is a signal that is multiplexed into one or more predetermined horizontal scanning periods within the vertical retrace period of the television signal, and the period to be invalidated includes the missing signal. 2. The data reproducing circuit according to claim 1, wherein the period is a horizontal scanning period.