JP2702939B2 - Digital signal reproduction device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial applications]   The present invention relates to a digital signal reproducing apparatus, and more particularly to a digital signal reproducing apparatus.
Digital data suitable for a device that performs double error correction in units of time
A signal reproducing circuit. [Conventional technology]   As a conventional digital playback device, for example, DAT
(Digital Audio Tape Recorder)
Section 63, "Latest AV Equipment and Digital Technology" (1986)
1 block at 128 blocks as discussed in Section 79.
C that constitutes a track and is completed in units of one track_Twoseries
And C completed in 2 blocks₁A sign with a double series
And generate one frame with two tracks
And interleave (data
And recording. Added to each block during playback
Correctly detects the block address
Generates an address to be written to RAM and stores data for two tracks.
Data, and C for each track₁Sign by (C₁Mark
) To detect errors and correct up to two symbols.
And C₁C for uncorrectable data with code₁correction
Based on the time information, C_TwoSequence code (C_Two6)
Make corrections up to the symbol. Above C_TwoUncorrectable code
For, keep the previous value or
Interpolate using the average, solve the interleave and output
I do. [Problems to be solved by the invention]   In the above conventional technology, the fold scratch on the tape and the running
Several blocks in the same track due to instantaneous disturbance to the
If you have a truck jump for a while,
Within this few blocks, C completed in two blocks₁Sign
No more errors can be detected and this C₁Based on sign information
And C_TwoCorrection may cause erroneous correction
is there. Furthermore, interleaving completed in two tracks
Will also be incorrect, so if you output as it is,
A sequence of data from different samples in columns (inter
Leave deviation), completely different from the pre-recorded signal
There was a problem of becoming a signal.   An object of the present invention is to detect the above-mentioned track jump, and_Two
Prevents erroneous correction due to codes and interleave misalignment
Another object of the present invention is to provide a digital signal processing circuit for stopping the operation. [Means for solving the problem]   The purpose of the above is to track or complete the code.
The frame to be played is frame-by-frame
Match of frame address or block address or
By checking continuity, each block can be traced.
The jump jump is detected and the C of the block is detected.₁Sign intentionally
Misleading or track jump detected
C in truck_TwoCorrection C₁Without using information at the time of correction, C_Two
Switch to processing that performs correction only based on code unique information
Is achieved by [Action]   Frame address in the above track jump detection
Or the check of the block address is added to the recorded data.
Of sync signal, parity bit and block address
Characteristics, etc., according to these conditions during playback.
Controls the start timing of the jump detection.
Dropout or Lander detection
There are few false detections of track jumps due to
Even if there is a slight false detection of rack jump, C_TwoCorrected words
Is reduced and only interpolation data is increased.
There are no malfunctions. 〔Example〕   Hereinafter, an embodiment of the present invention will be described with reference to FIG. No.
FIG. 1 shows a digital signal reproducing device represented by DAT, for example.
The configuration of a digital signal processing circuit using the present invention
It is a block diagram shown. In the figure, 1 is a demodulation circuit, 2 is a synchronization signal.
Detection protection circuit, 3 is parity check circuit, 4 is block address
5 is a track jump detection circuit, 6 is RAM
(Random access memory), 7 is data with memory 6
8 is a circuit for controlling data input / output,
Circuit for switching the address to be read / written, 10 is incorrect
Circuit for detecting and correcting errors.
Read / write data in memory 6 to perform
An address generation circuit, 12 stores the data after error correction
The circuit that generates the address to be read from memory 6 is incorrect.
Circuit for interpolating uncorrectable data in the correction circuit 10, and 14 for each
Generates the timing signals required to operate the circuit
Circuit.   First, the input terminals A and B are connected to the waveform-equalized playback data
And the playback clock extracted from the playback signal is input,
A predetermined synchronization signal from the reproduced data is
Signal is detected, thereby synchronizing and correcting the timing circuit 14.
And a predetermined bit unit constituting each symbol
And the demodulation circuit 1 digitally converts each symbol.
The data is demodulated to the original binary data. Demodulated data
The data is input to the RAM 6 via the data control circuit 7, and
In addition, a block added at the time of recording by the address detection circuit 4 is used.
Address signal is detected and protected.
Generates RAM address and completes interleaving
Write all data for the frame to be written to RAM. Hereafter, RAM
The data stored in 6 is corrected by the correction address generation circuit 11
When reading predetermined data and recording with the error detection and correction circuit 10.
, C encoded in a double sequence₁Sign, C_TwoCodes are sequentially restored
And performs error detection and correction. In addition, read
In the order in which the interleave is solved by the address generation circuit 12.
Read the corrected data from M6.   However, based on the information at the time of correction,
In addition, the interpolation circuit 13 stores the previous value with correct data before and after.
Or output from the output terminal C after average value interpolation.
In the case of DAT, the signal output from output terminal C is
Analogue audio signal is obtained by A-conversion.
You.   DAT error correction code is C₁, C_TwoBoth Reed Solomon Marks
No. is used and C₁28 completes a series in 2 blocks
Nvol audio data and 4 symbol C₁Inspection thin
This is a code with a code length of 32, consisting of a total of 32 symbols of VOL. C_Two
A series is an audio stream that is completed every 4 blocks and is completed in units of tracks.
26 data symbols and C_Two6 inspection symbols
Consists of a total of 32 symbols. Therefore, lead solo
The minimum distance between codes of the Mon code is C₁Is 5, C_TwoBecomes 7 and C₁Mark
Error correction for any two symbols whose error location is unknown
Can be. If the position of the error is known, 4 symbols
Can be corrected with an error in the file, and a quadruple erasure
There is positive. C_TwoEach code has 3 symbol error correction and 6 symbols
Volley Regia corrections can be made. So C₁Up to double code
Error correction is performed, and the error location
Set the lugs and C_TwoWhen decoding the code, C₁Set at correction
Erase correction is performed using the flag thus set.   In such a correction method, for example,
Block of reproduction signal is different due to
When a jumping phenomenon occurs in the frame
Also, due to the above correction code configuration, a signal of at least 2 blocks is reproduced.
Preferably C₁Code errors are detected and corrected.
Maybe this different frame block C₁Correction information
Based on C_TwoError correction is performed by the code, and C_TwoMark
It may cause erroneous correction at the time of issue. In addition,
A few blocks of data on trunk jumps without getting up
However, predetermined processing is performed as data in the same frame.
Output, the interleave rules are disturbed
When playing, C_TwoRegular in sample order by series
Two consecutive abnormal data will be generated.   Therefore, in the present invention, such a track jump is used.
For detection, the track jump detection circuit 5 of FIG.
Detects the frame address from the playback data, and
Check the frame address for each block, or
Blocks detected and protected by the address detection circuit 4 for each block
Paris added when checking and recording address continuity
According to various conditions including the output of the test symbol inspection circuit 5
To determine if a track jump has occurred and
When the jump jump is detected, the error correction circuit 10_TwoRevision
C on the hour₁Erasure correction using information at the time of correction
C by controlling to be prohibited_TwoMiscorrection caused by
Can be prevented.   FIG. 2 is a circuit block diagram showing another embodiment of the present invention.
FIG. 1 has the same reference numerals as in FIG.
Circuit.   Here, the write data control circuit 9 operates as a tracker.
Track detection by the pump detection circuit 5 in block units.
When abnormal playback such as a loop is detected, the playback data
Prohibit write processing or disable data control circuit 7
Control the C of the reproduction data of each abnormal block.₁Inspection symbol
At least correction, such as converting
Sometimes C₁Data so that it can always be determined as an error by the code
To process. As a result, abnormal output data
Interleave by mixing with the correct data_Two
C at correction₁Error detection using code
No correction is required, and the data in the abnormal block
Be replaced with interpolation data generated from the correct data.
And the interleave shift and C_TwoDifference due to erroneous correction
Generation of normal data can be prevented.   FIG. 3 is a circuit block diagram showing another embodiment of the present invention.
1 and 2 have the same functions.
The same circuit.   In this embodiment, the track jump detecting circuit 5
Write to RAM according to reliability of track jump discrimination
Data processing or C_TwoWhether to prohibit erasure correction
Select It converts or writes data to RAM
Is deliberately C₁Make an error
Then, when the number of erroneous detections of the track jump increases, two blocks
All data is destroyed in units and the error rate worsens.
In cases where correction is possible, the
Loss of the fidelity of the playback data so that
The reliability of the track jump discrimination is high because
Perform under the following conditions.   In this case, the detection of the track jump may be reversed.
Conditions that can be easily detected
In C_TwoProhibit erasure correction. False detection in this case
C occurs even if₁According to the correction information, C_TwoThe code is 6
If the erasure correction up to the symbol is possible, C₁correction
Without information, C_TwoOnly syndrome check by sign
Correction capability by only performing up to two symbol corrections
Is lower, but for uncorrectable words,
Interpolation is performed using data that is not
Don't give, wrong C₁C with correction information_TwoCompletely prevent mistakes
There is an effect that can be stopped.   FIG. 4 is a timing chart showing the operation of the embodiment according to the present invention.
Will be described.   FIG. 4A shows the timing generation circuit 14 shown in FIGS.
This is a cylinder servo reference signal to be generated. For DAT
Has a normal cylinder rotation speed of 2000rpm during regeneration.
Therefore, one cycle is 30 msec. This reference signal allows
Speed and head mounted on cylinder
The phase relationship between the two heads is maintained at a constant
In this case, the reproduced signal is obtained at the timing of every 90 ° shown in FIG.
You. In DAT format, the center of the playback signal 90 ゜
-Dio PCM data, subcode data at both ends (Fig.
Medium.S) between the subcode area and the PCM area
Pilot signals and the like for tracking are arranged.
FIG. J shows an example of the timing of the RAM processing.
Therefore, the data writing involves the reproduction signal B
At the timing of transfer to RAM, for example, RAM slot (1)
In addition, the sampling frequency channel is used in RAM.
It is necessary to read the corrected PCM data at several times the cycle
Therefore, by processing this in the RAM slot (2),
Write and read timings do not overlap
To In addition, the correction process uses the same slot as reading.
Performed in (2), and
Process so that it can be completed within one track. RAM capacity
If it is large, the correction process can be delayed by one track.
Both are possible. Complete the correction process in the same track
In order to C₁As can be seen from the correction processing start timing
Correction processing is started before PCM data is collected for one track.
It is.   Therefore, the PCM portion in the reproduced signal is shown in FIG.
In the data write area and for data write
Block address detected at₁For the correction address
Must precede. Figure C is a block diagram.
PCM area gate signal to protect address detection
And the block address detected by the predetermined condition judgment
And count up when conditions are not met.
Counter. Figure D shows this load signal.
You. Outside the PCM area, block address detection processing
Not be performed and within the PCM area signal and
Certain conditions are satisfied first. That is, the positive
Until C in the figure when a new top block is detected, RAM
Initialize the data to be written to. (G area in the figure
Area)   Conditions for detecting a block address include, for example, synchronous
Detection of signal, parity check, detection block
Continuity of address, detection block address C₁Correction address
For example, address precedence. Here in Figure B
As shown, the beginning a of the track is missing due to dropout.
Then, it is assumed that the area indicated by b in the figure has a track jump.
And the load signal D in the PCM area C
It is generated for the first time at c in FIG. Also a few bro
Even if track jump b occurs over
It cannot be detected under the condition, and the load condition is
The case where it is satisfied can occur sufficiently. Therefore, if the above conditions are met
At the same time, the frame address is detected and
Inspection of match in units of tracks, or tracking as shown in f in the figure
If the jump load condition is satisfied,
Detect non-continuity of protected block address
Detection of track jumps on a block-by-block basis
The signal G is output. However, as shown in Figure F, the PCM area
From e in the figure where the load condition is satisfied for the first time in A
By detecting a track jump, the leading drop is detected.
The abnormalities that occur at the tip-out a
Prevent erroneous detection. This detection area signal F
For example, a data write area generated for each track,
That is, the PCM area signal C is set at the beginning of the track.
Gate at the first load condition C
(Fig. E), and from the moment the flag is closed (d), the PC
Operates the track jump detection circuit only in the M area
Can increase reliability.
You.   The area of the signal F until the head of the track is detected correctly.
Area is the same area as g in the figure, RAM initialization processing
, And the detection data is not written to the RAM. Also,
Block where the rack jump detection signal is output (in the figure,
h) means that data writing to RAM is prohibited or less
And C₁C so that it can be determined as an error at the time of correction.₁Inspection symbol
By converting the data of_TwoMiscorrection and in
Prevents turbulence and prevents abnormal data from being output
I do. Here, when a track jump is detected, C₁Inspection symbol
Convert the data of₁Be sure to make an error when correcting
The reason is that when the track jump is a false detection
Is C₁C in the syndrome check performed at the time of correction₁At the time of correction
Data that was determined to be incorrect
When the error correction effect increases by being able to reproduce
And, of course, all the data in the block.
Data conversion or C₁For data conversion other than inspection symbols
C₁Even if it is determined to be an error at the time of correction, C_TwoMistake
Correction and interleave shift effects can be obtained in the same way.
Can be.   Also, the track jump detection signal G is one track.
Is output even once within_TwoCorrection processing timing
Signal H that completely covers_TwoCorrection processing method
, C₁Only erasure correction using information at the time of correction
By prohibiting, C_TwoCan prevent erroneous corrections.
Wear. This C_TwoCorrection control is detected by the track jump
Data of the track_TwoThailand just before correction
State is decided by_TwoSet after correction is completed
The track completion processing shown in FIG.
In the case of, set at the beginning of each track, and within the PCM area
Detects track jump and sets C_TwoTurn off correction algorithm
You can change it.   One embodiment of the track jump detection processing according to the present invention
Will be described with reference to the flowchart of FIG. This embodiment
Then, as shown in FIG. 4, the same track as the reproduced signal is used.
Shows the timing when the correction process is completed within
You. That is, in the figure, the head of the track is determined by branches a and c.
Otherwise, the detection circuit is initially set outside the PCM area (b).   This means that the PCM area signal follows the playback signal,
Furthermore, the fact that the phase of the rotating cylinder may be disturbed
Considering the PCM area signal does not match the predetermined RAM processing timing
Error, a track jump error is detected,
Prevents malfunction due to timing error of Lugo Lims change
To do that. After the initial setting of the detection circuit,
When the block address detected by branch d is an even number
Control to operate this track jump detection process.
You. In this embodiment, this is the frame address check.
Mainly for detecting traffic jumps
In the case of DAT, the frame address is only in even blocks.
This is because it is not recorded.   In branch e, the track jump detection operation is started.
The process is switched depending on whether it is after. That is, the first detection circuit
According to the period set (b), the detection area is turned off,
At the beginning due to branch e, when condition 1 is satisfied
For the first time (branch f), the track jump detection operation is started.
(Detection area open g), and register 1,
2. Latch the detected frame address. register
1 is the frame address signal of the block that satisfies condition 1.
The issue is only latched once at the beginning of the track,
Hereinafter, comparison with the sequentially detected frame address signal will be described.
Condition 1 must include the correct frame address.
Conditions must be selected to ensure that
No. In other words, under extreme conditions, track jump
Start operation is delayed, during which a track jump occurs
The problem comes out when the detection leak occurs when it is born
That's why. Therefore, condition 1 includes the PCM area described above.
If the load condition of the counter that generates the signal is the same,
Until the head load condition is satisfied, block address detection
RAM initialization operation is performed in the output protection circuit.
Before the start of the track jump detection
Playback data is not written on RAM even if a jump occurs.
Therefore, it is not possible to cause abnormalities in playback processing and output signals.
Absent. At the beginning, if condition 1 is satisfied,
In both cases, the same frame address is latched and the branch h
Therefore, actually, from the next detected frame address
The operation for detecting a transistor jump starts. Enter detection operation
The frame addresses detected from the second time onward are
The latch that latches to register 2
Address, and if they match, the
Judging that normal regeneration is in progress, and if they do not match,
By determining the case 2 and the condition 3, the drop-out
Frame address mismatch due to error or random error
Is identified. That is, conditions 2 and 3 are simple
Frame drop due to dropout or random error
If the dresses do not match, you are very likely to be satisfied
By selecting the condition that disappears, conditions 2 and 3 are satisfied.
And if the frame addresses do not match
It is determined that a jump has occurred.   Here, a track jump is detected according to the condition 2.
If the detected block data is C₁By sign
It is highly probable that no error is detected.
When writing, at least C as described above₁Errors at the time of correction
C so that it can be detected₁Data conversion of inspection symbol or
Data writing is prohibited.   Furthermore, according to condition 3, even once in the track
If a track jump is detected, the track
C_TwoCorrection processing, C₁C using information at the time of correction_TwoIle
By prohibiting only erasure corrections,
Error correction is prevented. In this case, C_TwoUp to 6 layers in code
Up to two symbols can be erased.
Error correction, and the correction capability is reduced.
Erroneous correction only when interpolation data increases in the output signal in frame units
It can prevent the occurrence of abnormal signals due to positive and audio
In the case of a signal, there is no problem in hearing.   As specific elements of the conditions 1, 2, and 3 in the present embodiment,
For example, by combining the following conditions
it can. (1) Synchronization signal detection result, (2) Paritiche
Check result, (3) Reproduction, continuation of block address signal
, (4) Playback, block address C₁Correction address
Precedence, etc. Here, the structure of the above conditions 1, 2, and 3
An embodiment will be described. First, condition 1 is the PCM area cow
As mentioned earlier, it is effective to use the same load conditions as
However, the reference frame address in this load condition is
(1) to above to reduce false detections due to latching
All the condition configurations of (4) are satisfied. Conditions 2 and 3 are
It is involved in the detection of Tsukuji Jump.
Intentionally C by conversion of RMA write data₁Mistake
Therefore, if there are many false detections in condition 2, an error
There is a problem that the card becomes worse. Because of this, even a little detection
A condition configuration that minimizes false detections is appropriate.
For example, the load condition is the same as condition 1
A configuration including all (1) to (4) is adopted. Or,
Protective cow counts and loads condition by unit
The frame address for every frame
Frame address based on the detected and protected frame address.
An address signal. Or detection protected frames
Address and frame address input at input terminal 38
By using the result of matching with the condition added to the load condition
The reliability of the reference frame address signal increases,
Improved reliability and effectiveness of track jump detection
You. In condition 3, the omission is detected in the flow up to the processing j in FIG.
To protect against track jumps
C due to false detection of condition 3_TwoEven if the correction capability decreases, the output
-The audio signal has very little effect on hearing. According to
And make it a condition that does not omit detection rather than false detection
It is more effective to give priority to (1) and (2) above.
Or only the parity check of (2)
Is suitable.   5. The track jump detecting process according to the present invention shown in FIG.
An embodiment of a track jump detection circuit for realizing
This will be described with reference to FIG. In the figure, 20 and 21 are registers, and 22 is
The match check circuit for the frame address, and 23 and 25 are the reset
Top flip-flop circuit, 24 and 26 are D flip-flops
Circuit, 27 to 32 are AND gate circuits, 33 to 42 are input terminals, 43, 44
Is an output terminal. Registers 20 and 21 are the frames described above.
This is a circuit for latching addresses.
Latches the reference frame address signal only once at the beginning.
The latch clock to the frame address
Slack clock 1 and frame address are recorded
Block address to detect only the block
▼ Signal, condition 1 and track jump detection error
Reset flip-flop circuit 23 for generating rear
Is input to the gate 28 by taking a conditional product.   Set-up reset that constitutes the detection area generation circuit
The tip flop 23 is set at the beginning of the track,
A reference frame address signal is latched on the register 20.
And the detection area is opened. Detection
Register 20 is reset while the rear is not open
The signal is registered in the register 21 every two blocks.
Touched, no match result with registers 20, 21
As a result, false detection of track jumps is likely to be induced.
However, to prevent this, the output of the track jump detection signal is
Near the step, outside the PCM area or outside the detection area, D-
The flip-flop circuits 24 and 26 are reset. flame
The address mismatch signal is further provided by gates 31 and 32.
It is determined by conditions 2 and 3 and the frame address matches.
The signal satisfying the condition 3 is a D-flip-flop.
Latched into circuit 24 and reset at the beginning of the track
Flit once in the track by the reset circuit 25
If the above situation occurs on the flop 24, C_TwoCorrection Thailand
Timing to cover the_TwoCorrection processing conversion
A control signal (FIG. 4H) is output from an output terminal 44.   Also, the frame addresses do not match and the condition 2 is satisfied
If this is done, this should be done just before the PCM data area in the block.
The clock 2 at the timing of
From the input terminal 42.₁It is the area of the inspection symbol
A code for identifying the area for the last 8 symbols of the odd block.
Control signal is input and the gate 27
Block C where jump was detected₁Only inspection symbols
The output signal is output from the output terminal 43. This
RAM write data, for example, by copying all bits "1" etc.
By converting the code, C₁At the time of correction
It is always wrong. This allows the truck jump
C_TwoMiscorrection and interleave misalignment
Abnormal output can be prevented.   Another embodiment of the track jump detection processing according to the present invention
An example will be described with reference to the flowchart of FIG. This implementation
In the example, if a track jump occurs, a few blocks
The above-mentioned load condition is satisfied between
The continuity of the block address that is detected and protected is lost.
That the main condition is that
This is an embodiment for detecting a jump. A to cd and l
Have the same contents as the functions and processes shown in FIG. Also,
In the figure, e to g determine the detection area of the track jump.
For the same reason as described in FIG.
Therefore, the condition 4 is suitable to be the same as the load condition.
I have. After the track jump detection operation is started,
At the branch h, it was detected and protected by the address detection circuit.
Check the continuity of block addresses. Here tiger
Tsukuji Jump occurs over several blocks and these
If the load condition is satisfied in the block, the block address
Detect and protect the counter with different frame blocks
The address will be loaded and the track jump
The probability that the block address is continuous before and after
Of the 7 bits in the dress, the number of bits to check is large
It gets smaller. Therefore, detection protected blocks
If address discontinuities are detected,
It can be determined that Tsukuji Jump has occurred, in which case the same
Like, C in the correction circuit_TwoProhibit erasure correction processing
You. However, even if a track jump occurs, there is little false detection.
May not be established under severe road conditions,
Check addresses are protected by simple count-up.
Write different blocks of data to RAM for several blocks.
It will be crowded. In this case, C_TwoErroneous correction is likely to occur
You. That is, the detection of the track jump is missing. But
The discontinuity of the detected block address is detected at branch h.
Is not detected, it is detected by branch i and j more than false detection.
Select in consideration of conditions with little leakage. For example, condition 5
Uses the parity check result to establish the parity condition
And a reproduction block address and a detection block at branch j.
If no address match can be detected,
It is judged that it is a pump. The parity check condition of branch i is satisfied
If not, the load condition is satisfied by dropout
Block address is considered protected
A branch block j indicates a reproduction block address and a detection block.
If an address match is detected, the load condition is satisfied
This is a normal playback status path without error.   FIG. 7 shows a track jump detecting process according to the present invention.
One embodiment of a track jump detection circuit that realizes
This will be described with reference to FIG.   In the figure, 50 to 57 are input terminals, 58 is track jump detection
Output terminal of the error correction processing switching control signal at the time, FIG.
To 3 which constitute the address detection circuit 4 shown in FIG.
Protection address counter, 60 is a latch circuit, 61 is a detection block
Address continuity detection circuit, 62 is a playback block address
Circuit and the detection block address match detection circuit, 63
Set flip-flop that constitutes the area generation circuit
Circuit, 64 and 65 are AND gates, 66 is OR gate, 67 is D-channel
A flip-flop circuit, 68 is a reset flip-flop
It is a top circuit. The address counter 59 displays the reproduced block.
Input the block address signal, and when playing back this block,
If the load condition described above is satisfied, it is loaded and
If not, simply count up by clock.
To protect the block address. Therefore,
Normal playback status even if there is a tap-out or random error
Detection block, which is the output of the address counter 59
In most cases, the dress signal will be continuous.
You. However, if a track jump occurs,
The load condition is easily established for the block, and as a result
Block address to be loaded is likely to break continuity
Will be very high. Therefore, the detection block address is
Delayed by one block in the latch circuit 60 and added to the latch circuit 60
Of the detection block address with the output of the counter 59
Continuity is detected by the continuity detection circuit 61, and discontinuity is detected by one track.
If even one block is detected in the
To the D-flip-flop circuit 67,
By setting the flip-flop circuit 68, C_TwoRevision
Generate a normal processing switching signal. Also, detection block address
Missed track jumps in the continuity check
In consideration of the
The output signal, that is, the reproduction block address and the detection block
The match with the address is checked by the match detection circuit 62,
Case 5, that is, the parity check is established, and
Only when the raw block addresses do not match is gate 65
Detected and judged as track jump.   Detection area generation circuit and control signal generation for error correction processing
Set flip-flops 63 and 63
And 68, the error correction processing is performed in the same track as the reproduced signal.
If it is completed, start signal of the track from input terminal 50
The initial setting is performed by inputting
4 (for example, the same as the load condition)
Open the rear and check out of the PCM area or
Outside the exit area, to prevent false detection of track jumps,
D-free, which is a latch circuit for the track jump detection signal.
Reset the top flop 67. 〔The invention's effect〕   According to the present invention, scratches on the recording medium,
Different frames that cannot occur with normal playback due to disturbances, etc.
Cross playback and track jump playback
On a track-by-track basis or on a track-by-track basis where the correction process is completed.
Can be output, and using this detection signal,
Control of writing data to memory only or C_TwoCorrection processing
By prohibiting only erasure correction,
Data C₁Errors can always be detected or corrected at the time of correction
C₁C using the information at the time of correction_TwoMaking erasure corrections
Because there is no_TwoMiscorrection or interleave misalignment
This has the effect of preventing output of abnormal data.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1, 2 and 3 are block diagrams of a digital signal reproducing circuit according to an embodiment of the present invention, and FIG. 4 is a circuit diagram of the circuit shown in FIGS. 1 to 3. FIG. 5 is an operation timing chart, FIG. 5 is a flowchart showing one embodiment of the track jump detection processing of the present invention, FIG. 6 is a track jump detection circuit diagram of one embodiment for realizing the track jump detection processing of FIG. FIG. 7 is a flowchart showing another embodiment of the track jump detecting process according to the present invention, and FIG. 8 is a track jump detecting circuit diagram of an embodiment for realizing the track jump detecting process of FIG. 3 ... Parity check circuit 4 ... Block address detection and protection circuit 5 ... Track jump detection circuit 6 ... RAM, 7 ... Data control circuit 8 ... RAM address control circuit 9 ... Write data control circuit 10 ... Error Detection and correction circuit 22 ... Frame address matching circuit 61 ... Detection block address continuity detection circuit 62 ... Reproduction / detection block address matching circuit 23, 63 ... Track jump detection area generation circuit

   ────────────────────────────────────────────────── ─── Continuation of front page    (72) Inventor Yuji Hatanaka               292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa               Hitachi, Ltd. (72) Inventor Shunichirou Sakamoto               25-1, Nishimachi, Yamada, Kawagoe-shi, Saitama               Onia Corporation Kawagoe Factory (72) Inventor Ichiro Miyake               Pie, 4-2610 Hanazono, Tokorozawa-shi, Saitama               Onia Corporation Tokorozawa Plant (72) Inventor Shinichi Wakumura               Pie, 4-2610 Hanazono, Tokorozawa-shi, Saitama               Onia Corporation Tokorozawa Plant                (56) References JP-A-62-208472 (JP, A)                 JP-A-60-136961 (JP, A)                 JP-A-61-145705 (JP, A)                 JP-A-59-1440738 (JP, A)                 JP-A-57-46585 (JP, A)                 JP-A-62-16277 (JP, A)

Claims (1)

(57) [Claims] The first error correction code and the second
The digital data and the error correction code are divided into predetermined bits to form blocks, and a synchronization signal, a block address and a track identification address are added to each block, and a track is formed by a plurality of blocks. An apparatus for reproducing a digital signal that has been constructed and recorded, stores reproduced digital data in a storage circuit using a reproduced block address, and performs digital signal sequential correction processing using the first and second error correction codes. In the reproducing apparatus, a first storage circuit that stores a reference value of the track identification address in the track, and a second storage circuit that sequentially stores the value of the track identification address detected in the track The value of the track identification address stored in the first storage circuit and the value of the track identification address stored in the second storage circuit; A check circuit for checking the identity of the value of the stored track identification address; and the storage circuit such that when an error is detected in the check circuit, an error is detected with at least a first error correction code. And a control circuit for prohibiting data writing to the data or converting the data to be written. 2. The first storage circuit stores the value of the track identification address first correctly detected in the track, and the second storage circuit stores the value of the second correctly detected track in the track. 2. The digital signal reproducing apparatus according to claim 1, wherein track identification addresses are sequentially stored. 3. In the inspection circuit, when an abnormality is detected,
3. The digital signal reproducing apparatus according to claim 1, wherein a correction process using the error correction code is switched. 4. 2. The method according to claim 1, wherein, when an abnormality is detected in the check circuit, the correction processing by the second error correction code is switched so as to be performed without using error detection information by the first error correction code. 4. A digital signal reproducing apparatus according to claim 3, wherein: