JPH073499Y2 - DAT - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a DAT, and more particularly to a DAT that detects a sampling frequency during digital input.

[Conventional technology]

In DAT, in addition to the standard 48 kHz, recording and playback can be performed on tape at sampling frequencies of 32 kHz and 44.1 kHz.

Therefore, the sampling frequency can be written in the subcode recording area of the tape, and the recording / recording
The sampling frequency during playback is displayed.

By the way, when recording from a digital input, detect which sampling frequency the input is using,
It must be recorded or displayed in the subcode recording area of the tape.

At this time, conventionally, the sampling frequency of the sub-code included in the digital input is read, or 3
For example, three types of clocks corresponding to one sampling frequency are generated, one of them is sequentially selected, and the sampling frequency is determined by comparing the frequency with the clock component of the digital input.

[Problems to be solved by the device]

However, in the above-mentioned conventional technique, when detecting the sampling frequency from the subcode of the former digital input,
The sampling frequency of the subcode sent by digital input is not always correct, and if it is incorrect, incorrect data will be recorded on the tape or displayed.

Also, when the sampling frequency is detected by the latter frequency scan, it takes time to detect it.Therefore, if the sampling frequency changes during digital input, the sub frequency will be delayed considerably from the sampling frequency change point of the PCM audio signal recorded on the tape. Since the sampling frequency data of the code changes or the display changes, there is a drawback that the user cannot accurately recognize the change point.

The present invention has been made in view of the drawbacks of the prior art, and an object thereof is to provide a DAT capable of detecting sampling frequency at the time of digital input while achieving both quickness and reliability.

[Means for Solving the Problems]

In the DAT according to the present invention, digital sampling data, a clock, and a subcode are extracted from a digital input while synchronizing with each other, and a digital input means for outputting an asynchronous detection signal in the case of an asynchronous state, and a clock having a different predetermined sampling frequency. A plurality of clock generating means, a selecting means for selectively selecting and outputting one clock from the clocks generated by the respective clock generating means, an output clock of the selecting means and a digital input means extracted. Frequency comparison means for performing frequency comparison with a clock and outputting a match signal when they match, and switching control for performing switching control of the selection means until the match signal is output when this frequency comparison means does not output a match signal Means and the digital input means stop outputting the asynchronous detection signal, the frequency ratio And the sampling frequency data output means for outputting the sampling frequency data relating to the selected position of the selection means when the means is outputting a coincidence signal,
The sampling frequency data output means is configured to temporarily output the sampling frequency data included in the subcode extracted by the digital input means immediately after the digital input means stops outputting the asynchronous detection signal. Is characterized by.

Further, in another DAT according to the present invention, a digital input means for extracting digital sampling data, a clock, and a subcode while synchronizing with a digital input, and outputting an asynchronous detection signal at the time of non-synchronization, and different predetermined input signals. A plurality of clock generating means for generating a clock having a sampling frequency, a selecting means for selectively selecting and outputting one clock from the clocks generated by the respective clock generating means, an output clock of the selecting means, and a digital input. Frequency comparison with the clock extracted by the means, and outputs a coincidence signal when they coincide, and when the frequency comparison means does not output the coincidence signal, switching control of the selection means until the coincidence signal is output Of the selection control means when the frequency comparison means outputs the coincidence signal. And the sampling frequency data output means for outputting the sampling frequency data of the position,
And the switching control means switches the selection means to a position indicated by the sampling frequency data included in the subcode extracted by the digital input means immediately after the digital input means stops outputting the asynchronous detection signal. Is characterized by.

〔Example〕

 One embodiment of this invention will be described with reference to FIG.

FIG. 1 is a block diagram showing a DAT according to the present invention.

Digital I / O with PLL sync circuit at digital input / output terminal D
When 10 is connected and set to the digital input mode, audio sample data, a subcode and a clock are extracted from the digital input based on a predetermined format from the outside, and PLL unlock detection is performed.

The signal processing circuit 12 is connected to one output side of the digital I / O 10, and the audio sample data extracted by the digital I / O 10 and the clock are output.

The signal processing circuit 12 takes in audio sample data based on the clock.

On the other hand, a microcomputer that controls the overall DAT 1
4, the other output side of the digital I / O10, the signal processing circuit 12,
Operation unit 16, display unit 18, tape running / mechanical unit (not shown)
Etc. are connected, and based on a predetermined program stored in the ROM, in accordance with the user's operation of the REC key or the like on the operation unit 16, REC control for each unit of the device, identification of sampling frequency at the time of digital input, and sub frequency including sampling frequency Performs code recording / display control, etc.

The microcomputer 14 inputs a sub code and a PLL unlock detection signal (asynchronous detection signal) from the digital I / O 10 in order to identify the sampling frequency at the time of digital input.

A selector circuit 20 is connected to one of the control output sides of the microcomputer 14.

This selector circuit 20 has three input terminals, and the clocks of 32kHz, 44.1kHz and 48kHz generated inside the DAT are input to each of them, and one of them is controlled according to the switching control of the microcomputer 14. Output.

The output side of the selector circuit 20 is connected to the input side of the frequency comparison circuit 22.

The clock output side of the digital I / O 10 is also connected to the input side of the frequency comparison circuit 22.

The frequency comparison circuit 22 compares the frequencies of the two input clocks and outputs a determination signal indicating whether or not they match to the microcomputer 14.

The microcomputer 14 also uses the discrimination signal of the frequency comparison circuit 22 to identify the sampling frequency.

Then, the subcode including the identified sampling frequency (Fs) data is output to the signal processing circuit 12 and recorded on the tape, and also output to the display unit 18 to display the sampling frequency.

The signal processing circuit 12 performs a predetermined signal conversion process based on the audio sample data input from the digital I / O 10 and the subcode input from the microcomputer 14 to create a recording signal, and outputs the recording signal to the head side.

Next, the operation of the above embodiment will be described with reference to the flowchart of FIG.

FIG. 2 shows the sampling frequency identification / output processing at the time of digital input.

First, the user specifies the digital input mode by key operation and then RE
When the C key is turned on, the microcomputer 14 sets the digital I / O 10 in the input mode and the signal processing circuit 1
2. Start the REC operation by controlling the tape drive and mechanical parts.

When the device on the source side is not operated yet, there is no signal input to the digital input / output terminal D, and the digital I / O 10 outputs the unlock signal to the microcomputer 14.

At this time, the microcomputer 14 does not output the sampling frequency data to the signal processing circuit 12 and output it to the display unit 18 (step 40).

After that, when the device on the source side is activated and put into the PLAY state, and digital input is made to the digital input / output terminal D, the PLL of the digital I / O 10 is synchronized and the audio sample data, subcode, and clock included in the input signal. Is extracted and output.

Also, the unlock signal output is stopped.

The microcomputer 14 is urged to stop the unlock signal, inputs the sub code from the digital I / O 10, and outputs 32 kHz, 4
Fs related to either 4.1kHz or 48kHz sampling frequency
If there is data, the subcode including this Fs data is immediately output to the signal processing circuit 12 and also output to the display unit 18 for frequency display (NO in step 40, 42
~ 46).

The signal processing circuit 12 creates a recording signal based on the audio sample data input from the digital I / O 10 and the subcode input from the microcomputer 14, and outputs the recording signal to the head side to record it on the tape.

As a result, the sampling frequency is recorded on the tape immediately after unlocking the digital I / O 10 and is also displayed.

After the output processing in step 46, the microcomputer 14 controls the switching of the selector circuit 20 according to the Fs data input from the digital I / O 10 (step 48).

For example, when Fs input from the digital I / O 10 is 44.1 kHz, the input position of the selector circuit 20 is set to a 44.1 kHz clock.

Then, the discrimination signal input from the frequency comparison circuit 22 is checked (step 50).

If the audio input data of the digital input is sampled at 44.1kHz, the clock extracted by the digital I / O 10 will also be 44.1kHz, so the output of the frequency comparison circuit 22 will show a match. At this time, the microcomputer 14 outputs a subcode including Fs data of 44.1 kHz corresponding to the current position of the selector circuit 20 to the signal processing circuit 12 and the display unit 18 (step 52).

This allows the actual sampling frequency of the digital input to be accurately recorded and displayed.

Thereafter, as long as the unlock signal is not input from the digital I / O 10 and the frequency comparison circuit 22 continues to output the determination signal indicating the coincidence, recording / display is continued at the sampling frequency related to the current position of the selector circuit 20. (Repeat steps 54, 50 and 52).

In this state, the sampling frequency of the digital input is
When the frequency changes to 32 kHz, the PLL lock of the digital I / O 10 is released and the unlock signal is input to the microcomputer 14.

Then, the microcomputer 14 determines YES in step 54 and returns to the first step 40.

As long as the unlocked state continues, the microcomputer 14 stops outputting the Fs data to the signal processing circuit 12 and the display unit 18.

Then, when the PLL of the digital I / O 10 finishes following the sampling frequency change and the unlock signal output is stopped, the microcomputer 14 inputs the subcode read by the digital I / O 10 (steps 40 and 42).

If there is sampling frequency data Fs in the subcode,
Immediately output to the signal processing circuit 12 and the display unit 18 (step
44, 46).

As a result, new Fs data is recorded and displayed immediately after the change of the sampling frequency of the digital input, and the user can know the change of the sampling frequency with almost no time delay.

After the processing of step 46, the microcomputer 14 controls the switching of the selector circuit 20 based on the Fs data inputted previously (step 48).

For example, when the Fs data input from the digital I / O 10 is 32kHz, the clock input position is 32kHz.

Then, the discrimination signal from the frequency comparison circuit 22 is checked (step 50).

Here, if the actual sampling frequency of the digital input and the Fs data input from the digital I / O 10 are different, the frequency comparison circuit 22 outputs a discriminating signal indicating inconsistency.

At this time, the microcomputer 14 temporarily stops the output of Fs data to the signal processing circuit 12, switches the selector circuit 20 to the clock input position of 44.1 kHz, and checks the discrimination signal again (steps 56 and 50).

If the discriminating signal again shows disagreement, the selector circuit 20 is switched again without outputting the Fs data and the frequency is 48 kHz.
Then, the discrimination signal of the frequency comparison circuit 22 is checked (steps 56 and 50).

When the actual sampling frequency of the digital input was 48 kHz, it is judged as YES in this step 50, and here the Fs data (= 48 kHz) related to the current position for the first time.
Is output to the signal processing circuit 12 and the display unit 18 to be recorded on a tape and displayed (step 52).

As a result, accurate recording and display after changing the sampling frequency is performed.

After that, as long as the unlock signal is not input and the determination signal indicating the coincidence is input from the frequency comparison circuit 22, the output of the Fs data related to the current position is continued.

If, for some reason, the discrimination signal does not match without the unlock signal being input, the microcomputer 14 stops outputting the Fs data and detects the accurate sampling frequency. To switch to the 32 kHz clock input position and determine whether or not the determination signals indicate a match (NO in step 50,
56, 50).

If they still do not match, switch the selector circuit 20 again.
At the position of 44.1kHz, check the discrimination signal (steps 56, 50) Here, if the discrimination signal indicating coincidence is input from the frequency comparison circuit 22, the microcomputer 14 determines that 44.1kHz is the accurate sampling frequency. Fs related to this frequency
The data is output to the signal processing circuit 12 to restart the recording, and also output to the display unit 18 to restart the display.

This makes it possible to detect an accurate frequency even if the actual sampling output of the digital input changes without the unlock signal being input from the digital I / O 10 for some reason.

If the sampling frequency data is not included in the subcode input from the digital I / O 10 after unlocking, the microcomputer 14 sets the selector circuit 20 to 32
While sequentially switching from the kHz position, it is checked whether the discrimination signal shows a match, and when the signal shows a match, switching is stopped, and recording and display are performed with the sampling frequency data related to the position at that time (NO in step 44).
Judgment, 58, 50, 56, 50, 52).

According to this embodiment, when the digital I / O 10 is unlocked, the sampling frequency is identified from the sampling frequency data of the subcode read by the digital I / O after unlocking, and recording or display on the tape is performed. Since this is done, it is possible to quickly respond to changes in the sampling frequency of the digital input, and the user can know the timing of change in the sampling frequency without delay when recording with the digital input or during subsequent reproduction.

In addition, the digital I / O 10
The extracted clock is compared with the three sampling frequency clocks generated in the DAT to identify the sampling frequency for recording or displaying on the tape, so that the user can know the accurate sampling frequency. it can.

In the above embodiment, the processing of step 46 in FIG. 2 is performed. However, by stopping this processing, the sampling frequency data is included in the subcode input from the digital I / O 10 after unlocking. At this time, the switching frequency in step 48 and the frequency checking process in step 50 are output, and the sampling frequency data is output only when it is determined that they match, thereby ensuring a certain degree of speed and reliability. Can be further improved.

[Effect of device]

In the DAT according to the present invention, digital sampling data, a clock, and a subcode are extracted from a digital input while synchronizing with each other, and a digital input means for outputting an asynchronous detection signal in the case of an asynchronous state, and a clock having a different predetermined sampling frequency. A plurality of clock generating means, a selecting means for selectively selecting and outputting one clock from the clocks generated by the respective clock generating means, an output clock of the selecting means and a digital input means extracted. Frequency comparison means for performing frequency comparison with a clock and outputting a match signal when they match, and switching control for performing switching control of the selection means until the match signal is output when this frequency comparison means does not output a match signal Means and the digital input means stop outputting the asynchronous detection signal, the frequency ratio And the sampling frequency data output means for outputting the sampling frequency data relating to the selected position of the selection means when the means is outputting a coincidence signal,
The sampling frequency data output means temporarily outputs the sampling frequency data included in the subcode extracted by the digital input means immediately after the digital input means stops outputting the asynchronous detection signal. , The sampling frequency after the change can be detected quickly when the sampling frequency of the digital input changes, while the detection can be performed with high reliability under normal conditions.

Also, in another DAT of this invention, digital sampling data, clock,
Digital input means for extracting subcodes and outputting an asynchronous detection signal when asynchronous, a plurality of clock generating means for generating clocks of different predetermined sampling frequencies, and a clock generated by each clock generating means And a frequency comparing means for performing frequency comparison between the output clock of the selecting means and the clock extracted by the digital input means, and outputting a coincidence signal when they coincide with each other. , When the frequency comparing means does not output the coincidence signal, the switching control means for controlling the switching of the selecting means until the coincidence signal is output, and the selection of the selecting means when the frequency comparing means outputs the coincidence signal A sampling frequency data output means for outputting sampling frequency data relating to the position; The control means switches the selection means to the position indicated by the sampling frequency data included in the subcode extracted by the digital input means immediately after the digital input means stops outputting the asynchronous detection signal, thereby sampling the digital input. The reliability of sampling frequency detection when the frequency changes can be further improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of a DAT according to one embodiment of the present invention, and FIG. 2 is a flow chart showing the operation of the microcomputer shown in FIG. 10: Digital I / O, 12: Signal processing circuit, 14: Microcomputer, 16: Operation part, 18: Display part, 20: Selector circuit, 22:
Frequency comparison circuit.

Claims (2)

[Scope of utility model registration request] 1. Digital input means for extracting digital sampling data, a clock, and a sub-code while synchronizing from a digital input, and outputting an asynchronous detection signal at the time of asynchronous, and clocks each having a different predetermined sampling frequency. A plurality of clock generating means, a selecting means for selectively selecting and outputting one clock from the clocks generated by the respective clock generating means, an output clock of the selecting means, and a clock extracted by the digital input means. Frequency comparison means that outputs a match signal when they match, and when this frequency comparison means does not output a match signal,
The switching control means for controlling the switching of the selecting means until the coincidence signal is output, and the switching means for the selecting means when the digital input means stops outputting the asynchronous detection signal and the frequency comparing means outputs the coincidence signal. Sampling frequency data output means for outputting sampling frequency data relating to the selected position is provided, and the sampling frequency data output means temporarily extracts the digital input means immediately after the digital input means stops outputting the asynchronous detection signal. The DAT is characterized in that the sampling frequency data included in the subcode is output. 2. Digital input means for extracting digital sampling data, clock, and sub-code from a digital input while synchronizing with each other, and outputting an asynchronous detection signal at the time of non-synchronization, and clocks each having a different predetermined sampling frequency. A plurality of clock generating means, a selecting means for selectively selecting and outputting one clock from the clocks generated by the respective clock generating means, an output clock of the selecting means, and a clock extracted by the digital input means. Frequency comparison means that outputs a match signal when they match, and when this frequency comparison means does not output a match signal,
Switching control means for controlling the switching of the selecting means until the coincidence signal is output, and sampling frequency data output means for outputting sampling frequency data relating to the selection position of the selecting means when the frequency comparing means outputs the coincidence signal. The switching control means switches the selection means to the position indicated by the sampling frequency data included in the subcode extracted by the digital input means immediately after the digital input means stops outputting the asynchronous detection signal. , DAT characterized by.