JP3085372B2 - Clock switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for switching a clock frequency to be supplied when performing an operation characteristic test depending on a clock frequency of a logic circuit such as a microprocessor.

[0002]

2. Description of the Related Art Conventionally, this kind of clock switching circuit has been disclosed in, for example, Japanese Patent Application Laid-Open No. 3-265016.
When switching between two types of input clocks, it is used for the purpose of not generating a waveform having a width shorter than either clock width.

FIG. 4 is a circuit diagram of a conventional clock switching circuit, and FIG. 5 is a time chart of the signal. The first clock generation circuit 1 and the second clock generation circuit 2 generate a first clock A and a second clock B which are input signals of the timing extraction circuit 3 ′ and the switching circuit 5, respectively. The timing extraction circuit 3 'includes flip-flops 21 to
26, inverters 27 to 30, AND circuits 31 to 33,
The first clock A and the second clock
Of the clock B is detected, and a timing signal C is sent to the synchronization circuit 4. The synchronization circuit 4 includes a D flip-flop 14, synchronizes a switching instruction signal D with a timing signal C, and generates a switching signal E. The switching circuit 5 includes AND circuits 16 and 17, an OR circuit 18, and an inverter 15. The switching circuit 5 switches either the first clock A or the second clock B using the switching signal E and outputs an output signal F. .

Next, the operation of the conventional example will be described with reference to FIG. When the frequency of the second clock B is slightly higher than that of the first clock A, the timing signal C is output as shown in FIG. The rising edge of the timing signal C starts from the timing t1, which is in phase, and
The timing of the falling edge of the timing signal C is the same as the timing of the second rising edge of the second clock B starting from the timing t3, which is the opposite phase.

[0005]

In the conventional clock switching circuit described above, at the time of clock switching, the pulse width of the output signal becomes larger than one of the pulse widths of the two input clocks, and the clock operates dynamically. There is a problem that it cannot be applied to a logic circuit. The reason is that the timing of switching the clocks is later than the timing of the two input clocks being in phase.

An object of the present invention is to provide a clock switching circuit in which the clock switching timing is made coincident with the timing at which two input clocks have the same phase.

[0007]

A clock switching circuit according to the present invention detects a timing at which the phases of a first clock and a second clock having different frequencies coincide with each other, and outputs a timing signal. A synchronization circuit that synchronizes a switching instruction signal externally provided and instructs switching with the timing signal, and outputs the switching signal as a switching signal;
Of selecting one of the clocks, possess a switching circuit for outputting said phase coincidence detecting circuit includes a first clock and a second
When both clock signals are in phase
The maximum rising pulse width at
An AND circuit that generates an interference signal having a small pulse width;
A low-pass filter for inputting the interference signal;
The output signal of the filter to the average level of the signal
And a comparator for digitizing .

The phase coincidence detection circuit detects the timing at which the two input clocks are in phase, and indicates this by the rising edge of the timing signal. The synchronization circuit synchronizes a rising edge of a switching instruction signal input by an operator or the like with a timing signal. The switching circuit selects and outputs one of the clocks at the timing of the rising edge of the signal specified by the synchronization circuit.

[0009]

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, a clock switching circuit according to an embodiment of the present invention uses a first clock A and a second clock B generated by first and second clock generation circuits 1 and 2, respectively. A phase coincidence detection circuit 3 for detecting a timing at which the phases coincide with each other and outputting a timing signal J
A synchronization circuit 4 for synchronizing a switching instruction signal D given from the outside with a timing signal J and generating a switching signal E;
The switching circuit 5 is configured to receive the first clock A and the second clock B, switch with a switching signal E, and output as an output signal F.

The present clock switching circuit differs from the conventional clock switching circuit of FIG. 4 only in the configuration of the phase coincidence detection circuit 3.

The phase coincidence detecting circuit 3 comprises an AND circuit 11, a low-pass filter 12, and a comparator 13.

An interference signal G is generated by an AND circuit 11 from the first clock A and the second clock B input to the phase coincidence detection circuit 3. The interference signal G has a feature that when the phases of the first clock A and the second clock B are the same, the pulse width becomes the maximum rising pulse width, and when the phases are the opposite phases, the pulse width becomes the minimum pulse width. This interference signal G is regarded as an analog signal, and is input to the low-pass filter 12 to obtain a filter signal H. Here, the low-pass filter 12
For example, a circuit as shown in FIG. Assuming that the frequency of the first clock A is f1 and the frequency of the second clock is f2, the resistance value R of the resistor 19 of the low-pass filter 12 and the capacitance C of the capacitor 20 are | f1−f2 | = 1 / 2πCR Is used. In this case, the filter signal H has a cycle of | f1−f2 |, and has a repetitive waveform that generates the maximum level at a timing that is 45 degrees behind the timing when the first clock A and the second clock B become in phase. Becomes The filter signal H is digitized by being input to the comparator 13, and the timing signal J
Get. When the comparison level of the comparator 13 is set to the average level of the filter signal H, the timing of the rising edge of the timing signal J obtained as an output coincides with the timing at which the first clock A and the second clock B become in phase. (Time t0 in FIG. 2).

In response to a switching instruction signal D given at an arbitrary timing by an operator or the like, a synchronization circuit F uses a timing signal J to generate a first clock A and a second clock B.
Synchronizes the switching instruction signal D at the timing when the signals become in-phase, and outputs the same as the switching signal E.

The switching circuit 5 outputs the second clock B when the switching signal E is at the L level, and outputs the first clock A when the switching signal E is at the H level.

[0016]

As described above, according to the present invention, the clock switching timing is performed at the timing when the phases of the two input clocks coincide with each other.
The output clock pulse width at the time of switching is equal to one of the two input clocks.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a clock switching circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart illustrating an operation example of the clock switching circuit of FIG. 1;

FIG. 3 is a diagram illustrating an example of a low-pass filter 12.

FIG. 4 is a circuit diagram of a conventional example of a clock switching circuit.

FIG. 5 is a timing chart showing a shift of the clock switching circuit of FIG. 4;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st clock generation circuit 2 2nd clock generation circuit 3 Phase match detection circuit 4 Synchronization circuit 5 Switching circuit 11 AND circuit 12 Low pass filter 13 Comparator 14 D flip-flop 15 Inverter 16, 17 AND circuit 18 OR circuit 19 Resistance 20 Capacitor A First clock B Second clock G Interference signal H Filter signal J Timing signal D Switching instruction signal E Switching signal F Output signal

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 1/06 H03K 5/00 H03L 7/08

Claims (5)

(57) [Claims] A timing detecting section that detects a timing at which the phases of a first clock and a second clock having different frequencies from each other coincide with each other;
A phase matching detection circuit that outputs a timing signal, a switching circuit that synchronizes a switching instruction signal that instructs switching given from the outside with the timing signal and outputs the switching signal, and a switching signal output from the synchronization circuit. selects one of the first clock and the second Kurroku, have a switching circuit for outputting said phase coincidence detecting circuit includes a first clock and the second black
Clocks and the maximum when both clock signals are in phase.
Rising pulse width, and the minimum
An AND circuit for generating an interference signal having a pulse width;
A low-pass filter for inputting an interference signal;
The output signal of the filter is compared to the average level of the signal and the
A block switching circuit having a comparator for digitizing . Wherein said low-pass filter composed of a resistor and a capacitor, the clock switching circuit of claim 1, wherein. 3. The resistance value R of the resistor and the capacitance C of the capacitor satisfy the relationship of | f1−f2 | = 容量 πCR when the first and second clock frequencies are f1 and f2, respectively. 3. The clock switching circuit according to claim 2, wherein 4. The synchronous circuit according to claim 1, wherein said switching instruction signal is a data input, and said timing signal is a clock input.
4. One of claims 1 to 3 , which is a flip-flop.
Clock switching circuit according to the item. 5. The switching circuit inputs an inverter that inverts the switching signal, a first AND circuit that inputs a first clock and the switching signal, and a second clock and an output signal of the inverter. The clock switching circuit according to any one of claims 1 to 5, further comprising a second AND circuit, and an OR circuit that inputs an output signal of the first AND circuit and an output signal of the second AND circuit.