JPS6028170B2 - Code synchronization method for reception of spread spectrum signals - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a code synchronization method for receiving spectrum spread signals.

In the spectrum spread communication system, which uses a spectrum spread signal that widens (spreads) the information signal by modulating it with a periodically repeated code signal with good cross-correlation, when demodulating the information signal on the receiving side, the spectrum on the transmitting side is A local code signal synchronized with the code signal for spread modulation is required.

Therefore, the receiving side is provided with a code signal generator that generates the same code signal as the code signal on the transmitting side, and this is synchronized with the received signal. There are several methods for synchronizing the output of the local code generator and the received signal, one of which is a delay synchronization method.

Referring to FIG. 1, the delay synchronization method includes a local code generator 1 that generates the same code signal as the code signal on the transmitting side, and a cross-correlator 2 that correlates its output with the received signal. There is.

The local code generator 1 generates two outputs that are out of phase with each other, and the correlator 2 correlates each of the two outputs of the local code generator 1 with the received signal. 21
, 22. The outputs of both correlators 21 and 22 are
After being synthesized in the synthesis circuit 3 and multiplied by the DC multiplier 4,
Pass through loop fill 5. Then, the DC component is supplied to a voltage controlled oscillator (hereinafter referred to as VCO) 6 to control the oscillation frequency of the VCO, and the oscillation output of the VC06 is supplied to the local code generator 1 to control the output code signal phase. . Here, an example of the local code generator is a random noise generator that generates a pseudo-noise code signal (hereinafter referred to as a PN signal). In the figure, the code generator includes an N-stage shift register 11 and a feedback It is shown as a combination with circuit 12.

Note that the clock pulse to shift register 11 is set to V
VC06 is a clock generator since C06 is at the input voltage. The local code signal consists in repeating periodically every 2N clock pulses. Also, the two outputs are shifted by one bit (two clock pulses) in this example. Further, the correlators 21 and 22 may be multipliers, and the synthesis circuit 3 may be a summation circuit.
It is like phasing and reversing one of the outputs of , and then taking the sum.

According to this delay synchronization method, if the output PN signal of the local encoder 1 is not synchronized with the code signal of the input signal, for example, the PN signal, an error signal is generated at the output of the combining circuit 3, which is transmitted to the loop filter. 5 to the VC06 as a clock pulse generator to control it and synchronize the phase of the output of the code generator 1 with the PN signal of the input signal. The state of synchronization of the signal with the PN signal can be stably maintained.

By the way, since the output of the synthesis circuit 3 contains many ripple components, it is necessary to provide a loop filter 8 such as a low-pass filter to extract only the DC component as a control signal for the VC06.

In this case, in order to reduce the phase-dependent fluctuation of VC06 in the synchronized state, it is preferable that the cutoff frequency of the loop filter 5 is low, but the time required for the system to enter the synchronized state (hereinafter referred to as lock-in time) is preferable. ), it is better to have a higher cutoff frequency for the loop filter. Therefore, for example, it may be possible to change the time constant of the loop filter after entering the synchronized state, but doing so would also change the damping factor of the system, which would also change the transfer of the entire system. The need arises and it becomes complicated.

Therefore, an object of the present invention is to provide a delay synchronization method that has a short lock-in time and can stably determine the synchronization state.

In the delay synchronization method described above, the present invention provides an integrator and a sample holding circuit in place of the loop filter, and a circuit for setting the sampling period in the sample holding circuit. The bit time of the code signal (one period of the clock signal mentioned above)
After synchronization, the sampling period is sequentially switched to an integer multiple of the bit time of the code signal and fixed at a predetermined value.

The present invention will be described in detail below with reference to Examples.

FIG. 2 shows a delay synchronization circuit according to an embodiment of the invention, in which similar parts to those in FIG. 1 are designated with the same reference numerals. In this delay synchronization circuit, an integrator 7 for integrating the output of the synthesis circuit 3 is provided on the output side, and a sample holding circuit 8 is provided on the output side of the synthesis circuit 3, and the output thereof is used as a control signal for the VC06. Since the sample holding circuit holds the input signal level at the time of the arrival of the sampling pulse at the output, it can be regarded as a low-pass filter whose cutoff frequency is the sampling pulse frequency. 9 is a generator of sampling pulses to the sample holding circuit 8, which includes a variable divider 91 that frequency divides the output of the VC06, a counter 92 for setting the division ratio of the variable frequency divider 91, and a counting pulse to the counter. The counter 92 is controlled to start/stop and reset its counting operation by an external start/stop/reset signal.

As a result, the frequency divider 91 divides the clock pulse, which is the output of the VC06, by the division ratio set in the counter 92, and a signal is applied to the sample holding circuit 8.

The meaning of providing this delay circuit for one river will be described later.
Incidentally, the power spectrum of the PN signal is as shown in FIG.

In the figure, Nco is the clock pulse frequency for the PN signal, and the oscillation frequency of VC06 matches this. on the other hand,
The frequency division ratio of the variable frequency divider 31 is determined by the counter 92.
By sequentially changing from 1 to n, the cutoff frequency of the sample holding circuit becomes fvco (=fc) the oscillation frequency of VC06.
Then fvco, Nco/2, Wco/3..., fvc
It will change as o/n.

In FIG. 3, curves A and B show the pass characteristics of the sample holding circuit 8 when the frequency division ratio is 1 and n. Therefore, when the sampling period in the sample holding circuit 8 is gradually increased from the clock pulse period of the PN signal, the cutoff frequency becomes smaller, and therefore, the ripple component appearing in the output of the combining circuit 3 is removed, and the DC component is converted to VC06. can be given to In this sense, it is preferable that the final frequency division ratio n can be set to 2n-1 since the repetition period of the code signal is N bits. FIG. 4 shows waveforms of various parts for explaining the operation of the embodiment shown in FIG. 2 in a synchronous state.

Referring to FIGS. 2 and 4, if it is assumed that the input signal PN signal is a and the output signals of the local code generator are b and c, the output signals of the correlators 21 and 22 are d, It becomes e.
This is the output signal f of the combining circuit 3 which combines both output signals. The output of the synthesis circuit 3 is integrated by an integrator 7 to produce a signal with a waveform like f.

On the other hand, it looks like the output clock pulse h of VC06, and P
2N pulses are generated during one repetition of N signals.

The output pulse from the sampling pulse generator 9 is indicated by i, where the frequency division ratio of the frequency divider 91 is set to 2N-1 by the counter 92, and as a result, the output of the sample holding circuit 8 is i is held constant. Here, the sampling pulse is delayed by the delay circuit 10 by Δt from the clock pulse. This determines the timing of sampling with respect to the integral waveform, and if there is no need for delay, the delay circuit 10 is unnecessary. Note that the input PN signal a
When the phase of the local code signals b and c is shifted, the value of the output j of the sample holding circuit 8 changes, so VC06 is controlled to maintain synchronization.

The operation of the sampling pulse generator begins with the counter 92.
If the frequency division ratio is set to 1, the output clock pulse of VC06 is directly applied to the sample holding circuit as a sampling pulse.

Therefore, since the sample holding circuit 8 acts as a filter for the cutoff frequency fvco, it is possible to shorten the roll time. After synchronization, when a start signal is sent to the counter 92, the counter 92 receives the signal from the pulse generator 93. Since the pulses are counted, the division ratio changes sequentially to 2, 3, ..., n, so the sampling period is also 2/fvco, 3/
Nco, ..., n/fvco becomes long, and the cutoff frequency of the sampling holding circuit also becomes fvco/2, fvco/
3,..., fvco/n, and as mentioned above, n=2
If the counter 92 is stopped at N-1, the synchronized state is maintained stably. Changing the sampling period of the sample hold circuit changes the time constant and gain of the system, so it is possible to shorten the lock-in time by simply changing the sampling period.
Moreover, the phase fluctuation of VC06 can be reduced.

Although the present invention has been described below with reference to specific embodiments, the present invention can be applied not only to PN signals but also to those using periodic code signals with good cross-correlation as Svelum spread modulation signals.

Furthermore, various configurations of the local code generator, sampling pulse generator, etc. are possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional delay synchronization circuit, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 3 shows the power spectrum of the PN signal and the sample retention circuit. FIGS. 4a to 4j are diagrams showing the respective signals of a to i in FIG. 2. FIGS. 1... Local code generator, 11... Shift register,
12... Feedback circuit, 2... Cross correlator, 21, 22...
・Correlator, 3...Synthesizing circuit, 6...Voltage controlled oscillator (VCO)
), 7... Integrator, 8... Sample holding circuit, 9...
...Sampling pulse generation circuit, 91...Frequency divider, 92
...Counter, 93...Pulse generator. Figure ↑ Figure 2 Figure 3 Figure 4 Hakama

Claims (1)

[Claims] 1 A method for synchronizing the local code signal and the received spread spectrum signal when receiving a spread spectrum signal that is spread spectrum modulated using a periodically repeated code signal with good cross-correlation, and which is the same as the above code signal. a local code recorder that generates a local code signal and a signal delayed from the local code signal; two correlators that respectively correlate the received signal with the two signals of the local generator; A circuit for synthesizing outputs, a loop filter for extracting a DC component from the output of the synthesis circuit, and a voltage controlled oscillator controlled by the DC output from the loop filter; In a delay synchronization method in which the received signal and the local code signal are synchronized by controlling the output phase of the signal, an integrator is provided on the output side of the synthesis circuit, and when the output of the integrator is input as the loop filter, the sample A holding circuit is provided, and a sampling pulse generator having means for setting the sampling period of the sample holding circuit is separately provided, and the sampling period is set to be the same as the bit time of the code signal until the synchronization state is entered. A code synchronization method for receiving a spread spectrum signal, characterized in that the sampling period is sequentially switched to an integral multiple of the bit time of the code signal and fixed at a predetermined integral multiple.