JP3183492B2 - Spread spectrum receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct spread type spread spectrum receiving apparatus, and prevents a phase error between a transmitting PN code and a receiving PN code when a phase locked loop is used for acquisition and holding. And a spread spectrum receiving apparatus.

[0002]

2. Description of the Related Art As one of wireless communication systems,
Spread spectrum communication systems are widely known. In this spread spectrum system, the transmitting side modulates a carrier with an information signal such as voice or data, and modulates the information modulated signal with an M signal.
Spread spectrum is performed by multiplying a spread code such as a sequence. Then, the spread spectrum signal is transmitted from the antenna. On the other hand, the receiving side multiplies the received spread spectrum signal by the same spreading code as that of the transmitting side to perform despreading, and further demodulates information to obtain an information signal.

In such a spread spectrum communication system, when despreading is performed on the receiving side, it is necessary to synchronize the spread code created on the receiving side with the spread code in the received signal and to multiply the spread code. Therefore, conventionally, a spread spectrum receiving apparatus has been proposed, as shown in FIG. 2, which maintains a synchronous relationship between a spread code created on the receiving side and a spread code in a received signal. In FIG. 2, a received spread spectrum signal is a frequency conversion circuit (1).
After the frequency is converted to a low frequency so that it can be easily processed by the subsequent circuit, the spreading code generation circuit (3)
Is multiplied by the spreading code generated from. The output signal of the multiplier (2) is compared in phase with the output signal of a VCXO (voltage controlled crystal oscillation circuit) (5) in a phase comparison circuit (4). The output signal of the phase comparison circuit (4) according to the result of the phase comparison is applied as a control signal to the VCXO (5) after being smoothed by the LPF (6), and the VCXO (5) is controlled according to the control signal.
The oscillation frequency of O (5) is varied. The output signal of the VCXO (5) is applied to a phase comparison circuit (4) and, after being divided by a frequency dividing circuit (7), to a spreading code generating circuit (3). Here, the multiplier (2), the phase comparator (4), the VCXO (5), the LPF (6), the frequency divider (7), and the spreading code generator (8) are a so-called PLL.
(Phase Locked Loop), and the PLL operates so that the phase difference between the two input signals of the phase comparison circuit (4) becomes zero. Therefore, the generation timing of the spread code from the spread code generation circuit (3) changes in accordance with the change of the oscillation frequency of the VCXO (5), and the PLL controls the phase of the two input signals of the phase comparison circuit (4). Operate in synchronization with each other, so that the output signal of the multiplier (2) and the VCXO (5)
Phase is synchronized with the output signal.

After the PLL is locked, a spread code synchronized with the spread spectrum signal is generated, and the spread spectrum signal and the spread code are multiplied by a multiplier (2) to perform despreading. Then, the output signal of the multiplier (2) generated by the despreading passes through the BPF (8),
The information signal is applied to a demodulation circuit (9) and an information signal can be obtained by demodulation.

[0005]

In FIG. 2, since the PLL operates so that the phases of the two input signals of the phase comparison circuit (4) are synchronized, the output signal of the multiplier (2) and the VCXO ( The phase difference with the output signal of 5) becomes zero. However, in practice, the phase of the spread code generated on the receiving side does not exactly match the phase of the spread code in the spread spectrum signal due to the delay of elements constituting the circuit of FIG. Could not.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is a spread spectrum receiving apparatus for receiving a spread spectrum signal. A spreading circuit, a phase synchronization circuit that generates an output signal synchronized with the phase of the output signal of the first despreading circuit, and a clock that generates a clock signal for a spreading code according to the output signal of the phase synchronization circuit A signal generation circuit, a spread code generation circuit that generates a plurality of spread codes according to an output signal of the clock signal generation circuit, a correlation detection circuit that detects a correlation between the spread spectrum signal and the plurality of spread codes, A control circuit for generating a control signal for controlling an output phase of the clock signal generation circuit in accordance with an output signal of the correlation detection circuit.

[0007] The spread code generating circuit may further include a first spread code,
A second spreading code which is advanced by a predetermined phase from the first spreading code and a third spreading code which is delayed by a predetermined phase from the first spreading code are generated. Further, the correlation detection circuit, a second despreading circuit for despreading the spread spectrum signal with the plurality of spreading codes, a level detection circuit for detecting a level of an output signal of the second despreading circuit,
And a holding circuit for holding an output signal of the level detection circuit.

[0008] Still further, the holding circuit is characterized by comprising a capacitor for holding an output signal of the level detection circuit. Still further, the spread code generating circuit is configured to determine a first spread code, a second spread code advanced by a predetermined phase from the first spread code, and a predetermined spread code from the first spread code in accordance with an output signal of the clock signal generation circuit. A third spreading code delayed by the phase of the first spreading code, wherein the holding circuit comprises a first holding circuit and a second holding circuit, wherein the first holding circuit performs the level detection according to the first spreading code. The output signal of the circuit is held, and the second holding circuit alternately holds the output signal of the level detection circuit according to the second spreading code or the third spreading code.

Further, the level detection circuit detects a minimum value of an output signal level of the second despreading circuit. Further, the holding circuit includes an A / D conversion circuit for digitally converting an output signal of the level detection circuit, and a memory for storing output data of the A / D conversion circuit.

Still further, the control circuit includes a comparison circuit and a control signal generation circuit, wherein the comparison circuit detects a change direction of a correlation output in accordance with an output signal of the correlation detection circuit; The generation circuit generates an advance or delay control signal according to an output signal of the comparison circuit. Still further, the spread code generating circuit is configured to determine a first spread code, a second spread code advanced by a predetermined phase from the first spread code, and a predetermined spread code from the first spread code in accordance with an output signal of the clock signal generation circuit. 3rd delayed by the phase of
A spread code is generated, and the holding circuit holds a first output signal of the level detection circuit according to the first spread code.
A holding circuit, and a second holding circuit for alternately holding an output signal of the level detection circuit in accordance with the second spreading code or the third spreading code, wherein the comparison circuit includes the first and second holding circuits. Are compared with each other.

When the output signal of the second holding circuit for holding the output signal of the level detection circuit corresponding to the second spreading code is larger than the output signal of the first holding circuit, the advance control signal is changed. When the output signal of the second holding circuit that generates and holds the output signal of the level detection circuit corresponding to the third spreading code is larger than the output signal of the first holding circuit, the delay control signal is generated. Characterized in that it occurs.

[0012]

According to the present invention, a clock signal is generated from a clock signal generation circuit in accordance with an output signal of a phase synchronization circuit generated in synchronization with an output signal of a first despreading circuit. First, second and third spreading codes are generated from a spreading code generating circuit according to the clock signal. The first to third spread codes are despread with the spread spectrum signal by the second despreading circuit, the level is detected by the level detection circuit, and the correlation between the spread spectrum signal and the spread code is detected by the correlation detection circuit. Is done. Further, the output signal of the level detection circuit is held in a holding circuit.

The second spreading code is a code whose phase is advanced by a predetermined phase from the first spreading code, and the third spreading code is a code whose phase is delayed by a predetermined phase from the first spreading code. By comparing the output signals of the holding circuit, the phase shift between the spread spectrum signal and the spread code can be determined,
A lead or delay control signal is generated from the control signal generation circuit according to the deviation. The output phase of the clock signal generation circuit is controlled according to the advance or delay control signal, and the phase of the spread code is advanced or delayed. This makes it possible to establish a synchronization relationship between the spreading codes on the transmitting side and the receiving side, so that accurate spectrum despreading can be performed by the first despreading circuit using the spread codes.

[0014]

FIG. 1 shows an embodiment of the present invention.
(10) is a VCO whose oscillation frequency is variable, (11) is a DC voltage source for applying a DC voltage to the VCO (10), and (12) is either an output signal of the LPF (6) or the DC voltage. A first selection circuit for selecting one of them, (13)
Is a capture detection circuit for detecting synchronization capture in accordance with the output signal of the first multiplier (2), (14) is a frequency divider circuit serving as a clock signal generation circuit for generating a spread code, and (15) is the first A second spreading code generating circuit for generating first to third spreading codes P1 to P3 according to the spreading code P0 from the spreading code generating circuit (3); (16) a first spreading code P;
A second selection circuit for selecting one spreading code from 1 to P3; (17) a second multiplication to be a second despreading circuit for multiplying the spread spectrum signal by the output signal of the second selection circuit (16) (18) a correlation detection circuit for detecting the correlation between the spread spectrum signal and the spread code; (19) controlling the second selection circuit (16), and according to the output signal of the correlation detection circuit (18) The control circuit controls the frequency dividing circuit (14). The same circuit as the conventional example of FIG.
The same reference numerals as those of the conventional example are attached, and the description is omitted. Also,
The VCO (10) has a variable frequency range of VC
Since it is wider than that of XO (5), it is used instead of VCXO (5).

In FIG. 1, a received spread spectrum signal is frequency-converted to a low frequency by a frequency conversion circuit (1), and then a second multiplier (2) (first despreading circuit) performs a second spreading code which will be described later. It is multiplied by the spreading code generated from the generating circuit (15). Then, the output signal of the first multiplier (2) is compared in phase with the output signal of the VCO (10) in the phase comparison circuit (4). The output signal of the phase comparison circuit (4) according to the result of the phase comparison is smoothed by the LPF (6), and then applied as a control signal to the VCO (10) via the first selection circuit (12). You. Here, the first multiplier (2),
Phase comparison circuit (4), LPF (6), VCO (10),
The frequency dividing circuit (14), the first and second spreading code generating circuits (3) and (15) constitute a phase locked loop (PLL), and the phase difference between two input signals of the phase comparing circuit (4) is zero. The PLL operates as follows.

The output signal of the VCO (10) is applied to the phase comparison circuit (4) and the frequency divider circuit (1).
4) is also applied and is divided by m. Then, a spread code P0 is generated from the first spread code generation circuit (3) based on the frequency divided output signal of the frequency divider circuit (14). Further, in accordance with the spread code, a second spread code P1 as a reference, a second spread code P2 advanced by a predetermined phase from the first spread code P1, and the second spread code P2 are sent from a second spread code generation circuit (15). A third spreading code P3 delayed by a predetermined phase from one code P1 is generated.

Here, the first spreading code generation circuit (3)
For example, it is a well-known circuit that includes a shift register and an exclusive OR gate and generates an M-sequence code in accordance with an output signal of a VCO (10) serving as a clock signal. Further, the second spread code generation circuit (15) is, for example, a spread code P0 of the first spread code generation circuit (3).
, And a three-stage serial shift register that uses the output signal of the VCO (10) as a clock signal, and the spreading code P0 is sequentially transmitted to the first to third-stage shift registers. The output signal of the second-stage shift register is used as the first spreading code P1, and the VCO (1
0), the second spreading code P2 advanced from the first spreading code by one clock from the first spreading code from the first stage shift register, and the third spreading code P3 delayed by one clock from the third stage shift register by one clock. It is a configuration to generate.

Further, the spread signal from the second spread signal generating circuit (15) is applied to the first multiplier (2). Therefore, the generation timing of the spread code generated from the first spread code generation circuit (3) changes in accordance with the change in the oscillation frequency of the VCO (5), and the PLL operates in the first multiplier (2).
And the output signal of the VCO (10) are synchronized. Therefore, the widely known PL
By using the method of L, it is possible to maintain synchronization between the output signal of the first multiplier (2) and the output signal of the VCO (10).

By the way, before synchronization is maintained, synchronization acquisition must be performed. Here, the operation at the time of synchronization acquisition will be described. Since the first selection circuit (12) selects the DC voltage source (11), a predetermined oscillation frequency signal is generated from the VCO (10), and the PLL is synchronously acquired. The predetermined oscillation frequency is set so as to be a desired lock frequency. When the output signal of the first multiplier (2) becomes equal to or higher than a predetermined level in the synchronization acquisition circuit (13),
When detecting that the PLL synchronization has been captured, the first selection circuit (1) responds to the output signal of the capture detection circuit (13).
2) selects the output signal of the LPF (6). Therefore, the oscillation frequency of the VCO (10) is changed so that the phase difference between the two input signals of the phase comparison circuit (4) becomes 0, and the VCO
The output oscillation frequency of (10) becomes the lock frequency of the PLL.

On the other hand, the control circuit (19) has a VCO (10)
And a first control signal is applied from the control circuit (19) to the second selection circuit (16) in accordance with the output signal of the VCO (10), and the second selection circuit (16) performs a selection operation. . The correlation between the received spread spectrum signal and the spread code is detected by a correlation detection circuit (18). In the control circuit (19), it is determined whether the phase of the spread code is behind or ahead of the phase of the spread spectrum signal in accordance with the detected correlation output, and in accordance with the determination result, the second control signal is generated by the control circuit ( 19) occurs. Then, the output generation timing of the frequency dividing circuit (14) is varied according to the second control signal. That is, if it is determined that the phase of the spread code is behind the phase of the spread spectrum signal according to the comparison result, the output generation timing of the frequency divider (14) is advanced by the second control signal, and as a result,
The phase of the spreading code advances. Conversely, if it is determined that the phase of the spread code is ahead of the phase of the spread spectrum signal, the output generation timing of the frequency divider (14) is delayed, so that the phase of the spread code is delayed.

Therefore, by the above operation, a spread code synchronized with the spread code in the spread spectrum signal is generated,
An accurate despreading is performed by multiplying the spread spectrum signal and the spread code by the first multiplier (2). The output signal of the first multiplier (2) is a BPF
An information signal can be obtained by demodulating the output signal applied to the demodulation circuit (9) via (8).

FIG. 3 shows an example of a specific configuration of a main part of FIG.
Transmission gates S1 to S4 for selecting one of the first to third spreading codes P1 to P3;
Frequency divider circuit (20) for dividing the output signal of CO (10) by n
A timing circuit (21) for generating a timing signal in accordance with an output signal of the frequency dividing circuit (20); and a BPF (2) for limiting an output signal of the second multiplier (17) to a predetermined band.
2), an envelope detection circuit (23) for performing envelope detection on an output signal of the BPF (22) serving as a level detection circuit, and a smoothing circuit (24) for smoothing an output signal of the envelope detection circuit (23). And transmission gates S5 to S8
A capacitor C1 and C2 serving as holding circuits, a comparison circuit (25) for comparing the holding levels of the capacitors C1 and C2, and a second control signal generating second control signal in accordance with an output signal of the comparison circuit (25). Control signal generation circuit (26)
Consisting of However, the frequency division number n is sufficiently larger than the frequency division number m, and the selection cycle of the second selection circuit (16) is at least one cycle of the spread code (one cycle: time corresponding to one pattern of the spread code) or more. Set to be.

In FIG. 3, a first spreading code P1 is applied to a first multiplier (2) and multiplied by a spread spectrum signal. After that, the output signal of the first multiplier (2) is applied to the demodulation circuit (9) and the phase comparison circuit (4). The frequency dividing circuit (20) frequency-divides the output signal of the VCO (10) by n and generates a clock obtained by dividing the frequency by n. The clock is applied to a timing circuit (21), and timing signals a to j are generated from the timing circuit (21) according to the clock. The transmission gates S1 to S8 are controlled by the timing signals a to h, respectively, and the transmission gate is turned on when an "H" level signal is applied.

On the other hand, the output signal of the second multiplier (17) obtained by multiplying the spread code selected according to the timing signals a to d by the spread spectrum signal is a BPF (2
After being limited to a predetermined band in 2), the envelope detection circuit (2)
In 3), envelope detection is performed. The envelope detection output signal is a signal indicating the correlation between the spread spectrum signal and the spread code,
As shown in FIG. 5, this is a triangular wave signal that has a high output when synchronized and has a level of 0 when shifted by one or more chips.
Thereafter, the envelope detection output signal is supplied to a smoothing circuit (24).
Is smoothed. After the output signal of the smoothing circuit (24) is held by the capacitor C1 or C2,
And the output level of C2 are compared by a comparison circuit (25).

The operation of FIG. 3 will be described with reference to the timing chart of FIG. During the period T1 in FIG. 4, the timing signals b, c, and e become “H” level, so that the transmission gates S2, S3, and S5 are turned on. Therefore, the second spreading code P2 is selected, and the second multiplier (17)
Is applied to The output signal of the smoothing circuit (24) according to the despreading of the second spreading code P2 and the spectrum signal is held in the capacitor C2 via the transmission gate S5.

Then, during the period T2 in FIG. 4, the timing signals b, d and f become "H" level, and the transmission gates S2, S4 and S6 are turned on. Therefore, the first spreading code P1 is selected, and the output signal of the smoothing circuit (24) according to the despreading of the first spreading code P1 and the spread spectrum signal is held in the capacitor C1 via the transmission S6.

Further, since the timing signals e and f are at the "L" level during the period T3 in FIG. 4, the transmission gates S5 and S6 are turned off, and are not held at all by the capacitors C1 and C2. Further, since the timing signal g becomes “H” level, the transmission gate S
7 and S8 are turned on. Therefore, the comparison circuit (25)
The holding levels of the capacitors C1 and C2 are compared, and only when the value of the capacitor C2 is larger than the capacitor C1, an "H" level signal is generated. In accordance with the "H" level of the timing signal i, the comparison circuit (25) ) Is taken into the second control signal generation circuit (26).

Thereafter, during the period T4 in FIG. 4, the timing signal j becomes "H" level, so that the frequency dividing circuit (14) responds to the timing signal h and the output signal of the comparing circuit (25).
And a second control signal is generated to advance the generation timing of. Since the timing signal h is at "H" level during the period from T1 to T2, the second control signal generation circuit (26) generates an "H" output signal from the comparison circuit (25).
In addition, since the timing signals a, c, and e are at the “H” level during the period T5 in FIG. 4, the transmission gates S1, S3, and S5 are turned on. Therefore, the third spreading code P3 is selected, and the output signal of the smoothing circuit (24) according to the despreading of the third spreading code P3 and the spectrum signal is transferred to the capacitor C2 via the transmission gate S5.
Is held.

Then, during the period T6 in FIG. 4, the timing signals a, d and f become "H" level, and the transmission gates S1, S4 and S6 are turned on. Therefore, the first spreading code P1 is selected, and the output signal of the smoothing circuit (24) according to the despreading of the first spreading code P1 and the spread spectrum signal is held in the capacitor C1 via the transmission S6.

Further, since the timing signals e and f are at "L" level during the period T7 in FIG. 4, the transmission gates S5 and S6 are turned off, and are not held at all by the capacitors C1 and C2. Further, since the timing signal g becomes “H” level, the transmission gate S
7 and S8 are turned on. The comparison circuit (25) compares the holding levels of the capacitors C1 and C2, generates an "H" level signal only when the value of the capacitor C2 is larger than the capacitor C1, and changes the timing signal i to the "H" level. Accordingly, the output signal of the comparison circuit (25) is taken into the second control signal generation circuit (26).

Since the timing signal j is at the "H" level during the period T8 in FIG. 4, if the output signal of the comparison circuit (25) is at the "H" level, the generation timing of the frequency divider (14) is delayed. A second control signal is generated. Note that T
During the period from 5 to T8, since the timing signal h is at the “L” level, the second control signal generating circuit (26)
4) Acts to generate a delayed second control signal in response to the "H" output signal.

Here, in FIG. 5, when the correlation output between the first to third spreading codes and the spread spectrum signal is A, C and A in FIG. 5, the comparison circuit (25) in the period T3 in FIG.
Is at "H" level, the second control signal is generated, and the generation timing of the frequency dividing circuit (14) is advanced. Therefore, the correlation outputs between the first to third spread signals and the spread spectrum signals are as shown in FIG. Further, when the correlation output between the first to third spreading codes and the spread spectrum signal is f, c and e in FIG. 5, T7 in FIG.
Since the output signal of the comparison circuit (25) becomes "H" level during the period, the second delay control signal is generated, and the frequency dividing circuit (14)
Occurs at a later timing. Therefore, the correlation output between the first to third spread signals and the spread spectrum signal becomes E, F, and D in FIG.

Therefore, as described above, T1 to T in FIG.
By repeating the operation of step 8, the correlation output between the first spread code and the spread spectrum signal becomes as shown in FIG. Since the output signal of the first multiplier (2) is obtained by multiplying the first spread code P1 and the spread spectrum signal, the first multiplier (2)
And accurate spectral despreading is performed. In FIG. 3, the output level of the envelope detection circuit (23) slightly changes. Therefore, the envelope detection signal is converted to a smoothing circuit (24).
, The comparison can be performed by the accurate comparison circuit (25). The smoothing circuit (24) shown in FIG.
, A minimum value detection circuit is connected, and an envelope detection circuit (2
The minimum value of the output signal of 3) may be detected, and the output signal of the minimum value detection circuit may be held.

FIG. 6 shows an example of a configuration in which a memory is used in place of the capacitor as the holding circuit in the circuit of FIG. In FIG. 6, an A / D conversion circuit (27) digitally converts an output signal of the smoothing circuit (23). Memory (2
8) stores and holds digital data of the A / D conversion circuit (27). The memory (28) has areas of memories 1 and 2, digital data corresponding to the first spread code is stored and held in the memory 1 in accordance with a timing signal from the timing circuit (19), and the memory 2 is stored in the memory 2. Digital data corresponding to the second and third spreading codes are stored alternately,
Will be retained. Then, the judgment circuit (29) compares the output data of the memory (28), and when the digital data of the memory 2 is larger than the digital data of the memory 1,
An "H" level output signal is generated. Although the embodiment using a capacitor, an A / D conversion circuit and a memory as the holding circuit has been described, other means may be used for the holding circuit without being limited to this.

Next, the operation of the frequency dividing circuit (14) will be described with reference to the timing chart of FIG. Dividing circuit (1
4) is configured by, for example, m-stage rising-edge detection flip-flops, and the first-stage flip-flop is cleared or preset according to a second control signal of the control circuit (18). VCO as a clock as shown in FIG.
When the output signal of (10) is applied to the frequency dividing circuit (14), the signal obtained by dividing the output signal of the VCO (10) by 2 is shown in FIG.
The solid-line signals of (b) and (f) are as shown by the solid lines in FIGS. 7 (c) and 7 (g), and the divided-frequency signal of FIG. Are output as indicated by the solid line.

Here, when the advanced second control signal of the second control signal is applied to the frequency dividing circuit (14) as shown in FIG. 7 (e), the first-stage flip-flop is cleared, and FIG.
As described above, the frequency-divided signal changes from “H” level to “L” level. Therefore, the signal of the subsequent divide-by-2 is as shown by the dotted line in FIG. 7 (b), and the signal of the divide-by-4 is as shown by the dotted line in FIG. 7 (c). As a result, the output signal of the frequency divider (14) becomes as shown by the dotted line in FIG. 7 (d), and the output generation timing of the frequency divider (14) is advanced as compared with the solid line in FIG. 7 (d).

When the delayed second control signal as shown in FIG. 7 (L) is applied to the frequency dividing circuit (14), the first stage flip-flop is preset and responds to the rising of the clock as shown in FIG. 7 (F). Without this, the frequency-divided signal maintains the “L” level. Therefore, the signal of the subsequent dividing by 2 is shown in FIG.
, And the signal of divide-by-4 is shown in FIG.
It becomes like the dotted line. As a result, the output signal of the frequency dividing circuit (14) becomes as shown by the dotted line in FIG. 7 (h), and the output generation timing of the frequency dividing circuit (14) is delayed as compared with the solid line in FIG. 7 (h).

[0038]

As described above, according to the present invention, the correlation output between the spread code and the spread spectrum signal is detected, and the spread code and the spread spectrum signal are synchronized in accordance with the detection result. Therefore, the spreading codes on the transmitting side and the receiving side are synchronized, and accurate spectrum despreading can be performed.

Further, in the process of generating the input signal of the spread code generation circuit, the phase of the spread code is adjusted by adjusting the generation timing of the input signal. Irrespective of the variation of the free-running frequency and the like, the adjustment range is not limited, so that accurate spectrum despreading can always be performed.
If the phase of the spread code is adjusted in a unit sufficiently smaller than the chip period of the spread code, synchronization can be achieved with high accuracy.

Further, since the correlation between the spread code and the spread spectrum signal is detected and held by time division, the circuit can be simplified.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional example.

FIG. 3 is a block diagram showing a main part of the present invention.

FIG. 4 is a timing chart for explaining the present invention.

FIG. 5 is a waveform chart for explaining the present invention.

FIG. 6 is a block diagram showing another embodiment of the present invention.

FIG. 7 is a timing chart for explaining a main part of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 VCO 14 Divider circuit 15 2nd spreading code generation circuit 16 2nd selection circuit 17 2nd multiplier 18 Correlation detection circuit 19 Control circuit 20 Divider circuit 21 Timing circuit 22 BPF 23 Envelope detection circuit 24 Smoothing circuit 25 Comparison circuit 26 second control signal generation circuit 27 A / D conversion circuit 28 memory 29 determination circuit

Continuation of front page (72) Inventor Yoshiaki Takahashi 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (56) References JP-A-4-196939 (JP, A)

Claims (8)

(57) [Claims] 1. A spread spectrum receiving apparatus for receiving a spread spectrum signal, comprising: a first despreading circuit for despreading the spread spectrum signal; and an output signal synchronized with a phase of an output signal of the first despreading circuit. A clock signal generating circuit for generating a clock signal for a spreading code in accordance with an output signal of the phase synchronizing circuit; and a first spreading circuit in accordance with an output signal of the clock signal generating circuit. Code, a second phase advanced by a predetermined phase from the first spreading code
A spread code generating circuit for generating a spread code and a third spread code delayed by a predetermined phase from the first spread code, and a spread code generating circuit for despreading the spread spectrum signal with the first to third spread codes sequentially selected. (2) a despreading circuit; a correlation detection circuit that detects a correlation between the spread spectrum signal and the plurality of spread codes according to an output signal of the second despreading circuit; And a control circuit for generating a control signal for controlling the output phase of the clock signal generation circuit in a unit sufficiently smaller than the chip period of the spread code. 2. The correlation detection circuit according to claim 1, further comprising: a level detection circuit for detecting a level of an output signal of the second despreading circuit; and a holding circuit for holding an output signal of the level detection circuit. The spread spectrum receiving apparatus according to claim 1. 3. The spread spectrum receiving apparatus according to claim 2, wherein said holding circuit comprises a capacitor for holding an output signal of a level detection circuit. 4. The holding circuit comprises a first holding circuit and a second holding circuit, wherein the first holding circuit holds an output signal of the level detection circuit according to the first spreading code, The spread spectrum receiving apparatus according to claim 2, wherein the second holding circuit alternately holds the output signal of the level detection circuit according to the second spreading code or the third spreading code. 5. An A / D converter for digitally converting an output signal of the level detection circuit.
Spectrum expanding of claim 2, wherein D conversion circuit, a memory for storing the output data of the A / D conversion circuit, that consists of
Scatter receiver. 6. A control circuit, comprising : a comparison circuit;
And a comparison circuit , wherein the comparison circuit is configured to output a phase signal in accordance with an output signal of the correlation detection circuit.
The control signal generation circuit detects a change direction of the related output, and responds to the output signal of the comparison circuit.
Generating an advance or delay control signal
The spread spectrum receiving apparatus according to claim 2. 7. The holding circuit according to claim 1, wherein
A first holding circuit for holding the output signal of the level detection circuit.
Path and before the second or third spreading code
Second holding for alternately holding the output signal of the level detection circuit
It consists of a circuit, the comparator circuit, the output signal of the first and second holding circuit
7. The spectrum according to claim 6, wherein
Spread receiver. 8. The control signal generating circuit according to claim 2, wherein
Before holding the output signal of the level detection circuit corresponding to the signal
The output signal of the second holding circuit is the output signal of the first holding circuit.
If it is larger than the signal, a lead control signal is generated, and the level detection circuit according to the third spreading code generates the advance control signal .
The output signal of the second holding circuit for holding the output signal is
If the output signal is larger than the output signal of the first holding circuit, the delay control signal
8. The spectrum according to claim 7, wherein
Spread receiver.