JPH03258131A - Delay synchronizing loop circuit - Google Patents

Abstract

PURPOSE:To fix a voltage controlled oscillator to a prescribed voltage and to quicken the synchronization locking by bringing the state to a synchronizing loop control range deviation state when any of a correlation between a reception signal and two adjacent receiver PN code series is a prescribed threshold level or below. CONSTITUTION:A transmission data modulated by a PN code series (CS) is used as a reception signal Sr, a correlation between a receiver side code equal to the series CS and the signal Sr is obtained by two multiplier sections 1, 2 and envelope detectors 3, 4. Correlation outputs (1), (2) of the detectors 3, 4 are fed to a subtractor 6 and a phase comparator section 9 and when any of the outputs (1), (2) reaches a threshold level being zero and an offset or below, the state is discriminated to be a synchronizing loop control range deviation state, and a selector 10 selects a prescribed voltage +V controlling a voltage controlled oscillator VCO 7 in place of an output of a loop filter 6. Thus, the synchronization locking is quickened without deviating the control range of the delay synchronizing loop.

Description

[Detailed Description of the Invention] [Summary] A transmission data signal modulated with a PN code sequence using a spread spectrum method is input as a received signal, and a receiving side PN code sequence that is the same as the PN code sequence is combined with the received signal. A correlation function is obtained using two multipliers and an envelope detector, a difference composite correlation function of both correlation function values is obtained using a subtracter, and a loop filter of a delay locked loop and a voltage controlled oscillator are calculated based on the composite correlation function. Regarding the delay-locked loop circuit that controls the clock frequency of the PN code sequence generator that generates the receiving side PN code sequence, the purpose of this is to realize a delay-locked loop circuit that can always control the locking loop. a phase comparator that detects a synchronous loop control range deviation state when any of the outputs does not exceed a dark value obtained by adding an offset value to zero; Instead, the voltage controlled oscillator is configured as a selector for selecting a controllable constant voltage.

[Industrial application field]

The present invention relates to a delay-locked loop circuit, in particular, a transmission data signal modulated with a PN code sequence by a spread spectrum method is input as a reception signal, and the correlation between the receiving side PN code sequence, which is the same as the PN code sequence, and the reception signal is determined. This invention relates to a delay-locked loop circuit that controls the clock frequency of a receiving side PN code sequence by taking .

As one of the data communication methods, the data to be sent and P
Spread spectrum method (S
Pread Spectrum System) has been attracting attention in recent years.

Modulation methods in this spread spectrum method include direct spread, frequency hopping, and pulsed frequency modulation, but the above PN code sequence is used in the direct spread method.
This PN code sequence is also generated on the receiving side,
PN code sequence multiplied on the transmitting side and its receiving side PN
The original transmission data is demodulated by multiplying and combining the code sequences.

In this case, it is necessary to maintain complete synchronization between the PN code sequence included in the received signal and the received @PN code sequence that is independently generated on the receiving side.

[Conventional technology]

FIG. 6 shows a conventional delay-locked loop (DLL) circuit for maintaining such synchronization, and its configuration is as follows: ,4,
The subtracter 5, the loop filter 6, and the voltage controlled oscillator generator (n-stage shift register) 8 are controlled.

In operation, the received signal S, is the product of the original data to be transmitted on the transmitting side multiplied by a predetermined PN code sequence (εOR), and is output from the PNN code generator on the receiving side. By multiplying two adjacent receiving side PN code sequences by the mixer 12 and determining the envelope by the envelope detector 3.4, the received signal S is generated as shown in FIGS. 7(a) and 7(b).

, the receiving side PN code sequence, and the correlation function, ■ is obtained.

A composite correlation function ((C) in the same figure) is obtained by giving the correlation numbers ■ and ■ obtained in this way to the subtracter 5, and the high frequency components are removed by the loop filter 6 to control the VCO 7.
It is given as AT pressure and its frequency is changed.

In this way, the PN code sequence on the receiving side tracks the input code and captures it between the maximum and minimum of the composite correlation function.

[Problem to be solved by the invention]

In such a conventional example, there was a problem that if the controllable range of the synchronous loop was exceeded, the control voltage of the VCO 7 would become zero (actually, the value obtained by adding the DC offset component to this value), making it impossible to perform synchronization. .

Therefore, the present invention inputs a transmitted data signal modulated with a PN code sequence by a spread spectrum method as a received signal, and calculates the correlation function between the receiving side PN code sequence, which is the same as the PN code sequence, and the received signal. A multiplication function section and an envelope detector are used to obtain the correlation function, a difference synthesis correlation function of both correlation function values is obtained using a subtracter, and based on the synthesis correlation function, a loop filter of a delay locked loop and a voltage controlled oscillator are used to generate the receiving side PN code. An object of the present invention is to realize a delay-locked loop circuit that can always control the lock loop in a delay-locked loop circuit that controls the clock frequency of a PN code sequence generator that generates a sequence.

[Means to solve the problem]

In order to solve the above problem, the delay-locked loop circuit according to the first aspect of the present invention, as shown in principle in FIG. a phase comparator 9 that detects a synchronous loop control range deviation state when the threshold value has not been exceeded, and the voltage controlled oscillator 7 can be controlled in place of the input or output of the loop filter 6 when the synchronous loop control range deviation state occurs. A selector 10 for selecting a constant voltage is provided.

In addition to the first aspect, the second aspect of the present invention further provides a method for calculating a correlation function between the PN code sequence and the received signal from the PN code sequence generator 8 at a phase of one-third of the period. a comparator 13 that determines whether the output correlation value of the other envelope detector 12 exceeds a dark value obtained by adding an offset value to zero; When the output correlation value of the envelope detector 12 exceeds a threshold value obtained by adding an offset value to zero, a constant voltage of one polarity is set to the selector by the output of the comparator 13; otherwise, a constant initial voltage of the other polarity is set to the selector. 10 is provided with another selector 14 which is applied to the selector 10.

[For production]

In FIG. 1 shown in the first aspect of the present invention, an envelope detector 3.
The correlation functions ■, ■ (Fig. 3 (a), (
b)) is sent to the subtractor 5 and also to the phase comparator 9, and when ■ of these correlation functions becomes equal to or less than the dark value obtained by adding the offset value to zero, it is calculated as shown in FIG. 3(C). In the phase comparison characteristic, the input from the loop filter 6 to VC○7 is fixed at a constant voltage V, and an asynchronous state in which no control voltage is output to VC○7 can be eliminated.

Note that the selector 10 may be provided before the loop filter 6, as shown by the dotted line in FIG.

However, in such a case, when the phase is at point a shown in FIG. It takes time to pull in because it has to be done synchronously.

Therefore, in the second aspect of the present invention, another multiplier 11 and an envelope detector 12 are provided, and a correlation function (fourth
Figure (C)) is obtained.

Then, by comparing this correlation number ■ with the dark value of the zero-offset value by the comparator 13, it can be determined that, for example, the phase at point a is below the dark value, which is outside the controllable range of the synchronous loop, as shown in FIG. 4(d). Since we know that there is, selector 14
selects a preset constant initial value (for example, constant +V) of the control voltage of ■C○7.

At this time, as in the first aspect of the present invention, selector 0 selects the one that is not the composite correlation function from loop filter 6 (or subtracter 5), so selector 10 selects selector 14.
The initial voltage (+V) from the VCO 7 is output and applied to the VCO 7.

As a result, the phase moves to the left, so that the controllable range of the synchronous loop is reached at point b of the next cycle, and the selector 10 selects the bottom correlation function from the loop filter 6 (or subtractor 5), and the phase becomes 0. point and become synchronized.

Also, in the case of the phase at point d, it is not within the controllable range of the synchronous loop, and at this time, the selector 10 also controls the VCO.
The initial control voltage (! (+V) at point 7 is selected and the phase moves to the left, but since the correlation function exceeds the threshold at point e, the output of the comparator 13 causes the selector 14 to select a constant voltage (-V) of the other polarity. is selected, and therefore the phase moves to the right from point e as shown in FIG. 4(d).

For this reason, the PN code given from the PNN code sequence generation section to the multiplication section 11 is selected to have a phase that divides its period 1:2.

Therefore, the phase shift is at most 2/3 cycles, and high-speed pull-in is possible.

〔Example〕

FIG. 5 shows an embodiment of the phase comparator 9 used in the first and second aspects of the present invention. In this embodiment, comparators 91 and 92 and outputs of these comparators 91 and 92 are input. AND gate 93, and comparators 91 and 92 have correlation functions ■ and ■ (third
(see Figure 4 and Figure 4) is compared with a threshold Th consisting of a zero offset value (DC component), and when it exceeds this threshold Th, the output level becomes "'H" and the comparator 9192
When both outputs are “H” level, receive this and AND
The output of the gate 93 also becomes "H" level, and the output of the loop filter 6 is selected. Incidentally, at this time, the selection of the selector 14 is returned to the initial value as shown by the dotted line.

When either of the correlation functions (7) does not exceed the threshold MTh, the output of the comparator 91 or 92 is at the "L" level, so the output of the AND gate 93 is at the "L" level, and the selector 10 applies a certain control to vCO7. W5iit
The pressure V will be selected.

Note that the loop filter 6 may be installed either on the input side or the output side of the selector 10.

〔Effect of the invention〕

As explained above, according to the delay locked loop circuit according to the first aspect of the present invention, the received signal and the two adjacent receiving side PN
Since the configuration is such that when any of the correlation functions with the code sequence does not exceed a threshold value of zero plus an offset value, it is determined that the synchronous loop control range is out of range and the voltage controlled oscillator is fixed at a constant controllable voltage. Since the control range of the delay synchronization loop is not exceeded, synchronization can be quickly performed.

Furthermore, in the second aspect of the present invention, 3 of the period of the PN code sequence is
Separately calculate the correlation function between the PN code sequence and the received signal at a phase of 1/2, determine whether the correlation function exceeds the dark value obtained by adding the offset value to zero, and set the constant voltage of one or the other polarity to the voltage. Since the control voltage is used as the control voltage of the controlled oscillator, synchronization can be achieved even more quickly without the phase shifting to the next cycle.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the principle of a delay-locked loop circuit according to the first invention; FIG. 2 is a block diagram showing the principle of a delay-locked loop circuit according to the second invention; FIG. 3 is a waveform diagram for explaining the first invention in detail, FIG. 4 is a waveform diagram for explaining the second invention in detail, and FIG. 5 is a waveform diagram for explaining the second invention in detail. FIG. 6 is a block diagram showing a conventional example, and FIG. 7 is a waveform diagram for explaining the operation of the conventional example. In FIG. 1 and FIG. 2, 1.2.11... Multiplier, 3.4.12... Envelope detector, 5... Subtractor, 6... Loop filter, 7... - Voltage controlled oscillator (VC○), 8... PN code sequence generation section, 9... Phase comparison section, Io 14... Selector, 13... Comparator. In the figures, the same reference numerals indicate the same or corresponding parts. 1st principle diagram of the present invention 1st operation explanatory diagram of the present invention Figure 3 +O”+offset value 2nd principle diagram of the present invention Figure 4 Conventional example

Claims (2)

[Claims] (1) A transmission data signal modulated with a PN code sequence using a spread spectrum method is input as a reception signal (Sr), and a correlation function between the receiving side PN code sequence that is the same as the PN code sequence and the reception signal (Sr) is the two multiplication functions (1) (
2) and envelope detectors (3) and (4), a subtracter (5) takes a difference composite correlation function of both correlation function values, and a loop filter (6) of a delay locked loop is calculated based on the composite correlation function.
) and a voltage controlled oscillator (7) to control the clock frequency of the PN code sequence generator (8) that generates the receiving side PN code sequence, the outputs of both detectors (3) and (4) a phase comparator (9) that detects a state out of the synchronous loop control range when either of them does not exceed a threshold value obtained by adding an offset value to zero; A delay locked loop circuit comprising: a selector (10) for selecting a constant voltage that can be controlled by the voltage controlled oscillator (7) instead of an input or output; (2) Another multiplication unit (11) and an envelope detector (12) for calculating the correlation function between the PN code sequence and the received signal from the PN code sequence generation unit (8) at a phase of one-third of the period of the PN code sequence generation unit (8). ), a comparator (13) that determines whether the output correlation value of the other envelope detector (12) exceeds a threshold value of zero plus an offset value, and the other envelope detector (12). ) exceeds a threshold value of zero plus an offset value, the comparator (13) outputs a constant voltage of one polarity; otherwise, the selector (13) outputs a constant initial voltage of the other polarity. 2. The delay locked loop circuit according to claim 1, further comprising: another selector (14) for providing the signal to the signal.