JP2880344B2 - Direct sequence synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct sequence (DS) synchronization circuit used in spread spectrum (SS) ranging.

[0002]

2. Description of the Related Art FIG. 4 shows, for example, "Coherent Spread Spectrum Systems".
trum Systems) (Author; JKHo Holmes)
lmes) issued by John Wheelie and Sons (John
1 is a block diagram showing a conventional DS synchronization circuit shown on pages 475 to 481 of Wiley & Sans) (1982).

[0003] In the figure, 1 is according to a clock signal,
A shift register which generates a pseudo noise (hereinafter referred to as PN) sequence advanced by 1/2 bit and a PN sequence delayed by 1/2 bit. Reference numerals 2a and 2b denote each PN sequence generated by the shift register 1 as an input signal. Is a multiplier for multiplying by.

[0004] Reference numerals 3a and 3b denote band-pass filters for limiting the output bands of the multipliers 2a and 2b.
Reference numerals a and 4b denote detectors for performing envelope detection on the outputs of the multipliers 2a and 2b band-limited by the band-pass filters 3a and 3b, respectively. Reference numeral 5 denotes each of these detectors 4a, 4b
Is a subtractor that generates an error signal by taking the difference between the outputs.

Reference numeral 6 denotes a loop filter for smoothing the error signal from the subtracter 5, and 7 denotes a loop filter.
A voltage-controlled frequency variable oscillator (hereinafter, referred to as a VCO) as an oscillator whose oscillation frequency is controlled based on the error signal smoothed by the above and generates a clock signal to the shift register 1.

8 is 1 / output from the shift register 1.
This is a delay circuit that delays a PN sequence advanced by 2 bits by ビ ッ ト bit. Reference numeral 9 denotes a multiplier for multiplying the PN sequence passed through the delay circuit by the input signal, and reference numeral 10 denotes a bandpass filter for limiting the output band of the multiplier 9.

Next, the operation will be described. The input signal is supplied to multipliers 2a and 2b as a PN sequence advanced by 1/2 bit output from shift register 1, or 1/2.
It is multiplied by the bit delayed PN sequence. Each multiplier 2a, 2
b, the signals respectively multiplied by bandpass filters 3
After passing through a or 3b, the band is limited and the correlation is taken, the envelope is detected by the detector 4a or 4b.

The subtracter 5 subtracts the detection signal multiplied by the PN sequence delayed by 1/2 bit from the detection signal multiplied by the PN sequence advanced by 1/2 bit to generate an error signal. The error signal is smoothed by the loop filter 6 and then supplied to the VCO 7 to generate a clock signal for driving the shift register 1.

As described above, the DS synchronization circuit based on this delay locked loop (hereinafter referred to as DLL) controls the synchronization operation by controlling the delay included in the input signal and the delay supplied from the shift register 1 so as to match. Do.

[0010]

Since the conventional DS synchronous circuit is configured as described above, when performing SS ranging,
When a multipath wave is added to the input signal, a synchronization shift occurs,
There is a problem that a distance measurement error occurs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and provides a DS synchronization capable of compensating for a synchronization shift even when a multipath wave is added to an input signal during SS ranging. The aim is to obtain a circuit.

[0012]

According to a first aspect of the present invention, there is provided a DS synchronization circuit comprising a PN output from a shift register.
A phase search circuit that searches the correlation value of a composite wave of an input signal in which a multipath wave is added to an original signal wave by changing the phase of the series, and a composite wave that is searched by the phase search circuit. And a detection circuit for detecting the peak of the original signal wave based on the change point of the correlation value.

According to a second aspect of the present invention, there is provided a DS synchronization circuit comprising: a dither generator for controlling a switching operation of a switch for selecting a pseudo noise sequence generated by a shift register; and a PN sequence output from the shift register. A phase search circuit that searches the correlation value of a composite wave of an input signal in which a multipath wave is added to an original signal wave by changing a phase, and a correlation of the composite wave searched by the phase search circuit. And a detection circuit for detecting the peak of the original signal wave based on the value change point.

[0014]

[Action] D in the invention of this claim 1 and claim 2
S synchronization circuit is intended to output to the PN sequence phase of the shift register to obtain a variable can DS synchronization circuit.
By varying at position phase search circuit, Yuki searches the correlation value of the composite wave of the input signal multipath waves is applied to the original signal wave in turn, the changing point of the correlation value of the composite wave to be searched A DS synchronization circuit capable of compensating for a synchronization shift of an input signal to which a multipath wave is added by detecting a peak of an original signal wave by detection by a detection circuit is realized.

[0015]

【Example】

Embodiment 1 FIG. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the first aspect of the present invention. In the figure, 1 is a shift register, 2
a and 2b are multipliers, 3a and 3b are bandpass filters,
4a and 4b are detectors, 5 is a subtractor, 6 is a loop filter, 7 is a VCO, 8 is a delay circuit, 9 is a multiplier, and 10 is a band-pass filter. Since they are the same as or equivalent to those described above, detailed description is omitted.

Reference numeral 11 denotes a combination of an input signal obtained by adding a multipath wave to an original signal wave by supplying the PN sequence to the multiplier 9 while changing the phase of the PN sequence from the shift register 1 passed through the delay circuit 8. This is a phase search circuit that searches for a correlation value of a wave in order from the phase advance to the phase delay.

Reference numeral 12 denotes a detector for performing envelope detection on the output of the multiplier 9 band-limited by the band-pass filter 10. Reference numeral 13 denotes a search by the phase search circuit 11 based on the detection output of the detector 12. This is a detection circuit that detects a change point of the correlation value of the synthesized wave to be detected and detects the peak of the original signal wave.

Next, the operation will be described. Here, the basic operation is the same as in the conventional case, and a description thereof will be omitted.

The phase search circuit 11 includes a shift register 1
The phase of the PN sequence output from the delay circuit 8 and passed through the delay circuit 8 is supplied to the multiplier 9 while being continuously changed in order from the phase advance to the phase delay.

The multiplier 9 multiplies the PN sequence output from the phase search circuit 11 by the input signal and sends the multiplied signal to the band-pass filter 10. The band-pass filter 10 limits the band and inputs it to the detector 12. The detector 12 detects the correlation between the two signals by performing envelope detection of the received signal.

FIG. 2 is an explanatory diagram showing a correlation value of a composite wave of an input signal when a multipath wave is added to an original signal wave. In the figure, S ₀ is a correlation value of an original signal wave, S ₁ is a correlation value of a multipath wave, S is a correlation value of a composite wave obtained by combining the two, and P is a change point of the correlation value S of the composite wave. It is. As shown in FIG. 2, the peak of the correlation values S ₁ of the multipath waves always delayed occurrence than the peak of the correlation value S ₀ of the original signal.

Focusing on this point, the correlation value S of the composite wave
As described above by the phase search circuit 11 in order from the phase advance to the phase delay, and the first change point P of the correlation value S of the composite wave is detected by the detection circuit 13. By detecting and detecting the peak of the correlation value S ₀ of the original signal wave, it is possible to synchronize with the required lock point.

By doing so, even when the multipath wave is larger than the original signal wave, the lock point of the original signal wave can be reliably detected.

Embodiment 2 FIG. In the first embodiment, the DL
Although the description has been given of the case where the present invention is applied to a DS synchronous circuit based on L, the present invention may be applied to a DS synchronous circuit using a τ dither synchronous circuit. FIG. 3 is a block diagram showing an embodiment of such an invention described in claim 2, in which the same parts as those in FIG. In the figure, 2,
Reference numerals 3 and 4 denote multipliers, bandpass filters, and detectors corresponding to 2a, 2b, 3a, 3b and 4a, 4b shown in FIG.

Reference numeral 14 denotes a half generated by the shift register 1.
A switch that selects one of a PN sequence advanced by one bit and a PN sequence delayed by ビ ッ ト bit and sends it to the multiplier 2. Reference numeral 15 denotes a dither generator which controls the switching operation of the switch 14. Reference numeral 16 denotes a multiplier which multiplies the detection output of the detector 4 by a signal generated by the dither generator 15 and sends the multiplied signal to the loop filter 6. is there.

Next, the operation will be described. In this case, the basic operation is the same as in the first embodiment. That is, the dither generator 15 creates a small difference between the correlation values to perform synchronization tracking. The PN sequence output from the shift register 1 of the τ dither synchronization circuit shown in FIG.
, And the phase is searched in order from the phase advance to the phase delay, and the detection circuit 13 detects the first change point P of the correlation value S of the composite wave and determines the required lock point. Synchronize.

[0027]

As described above, according to the first and second aspects of the present invention, the phase of the PN sequence output from the shift register is changed by the phase search circuit, so that the multipath wave becomes the original signal wave. The correlation value of the composite wave of the added input signal is searched in order, and a change point of the correlation value of the composite wave to be searched is detected by the detection circuit to detect the peak of the original signal wave. Therefore, even when the multipath wave is larger than the original signal wave, it is possible to reliably detect the lock point, and it is possible to obtain a DS synchronous circuit capable of compensating for a synchronization shift during SS ranging.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a correlation value of a composite wave of an input signal when a multipath wave is added to an original signal wave.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional DS synchronization circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Shift register 2a, 2b, 2 Multiplier 4a, 4b, 4 Detector 5 Subtractor 7 Oscillator (VCO) 11 Phase search circuit 13 Detection circuit 14 Switching device 15 Dither generator 16 Multiplier

Continuation of the front page (56) References JP-A-3-255740 (JP, A) JP-A-4-347944 (JP, A) JP-A-3-113921 (JP, A) JP-A-2-140031 (JP) JP-A-4-47819 (JP, A) JP-A-4-79438 (JP, A) JP-A-4-286235 (JP, A) JP-A-2-276330 (JP, A) (58) Surveyed fields (Int.Cl. ⁶ , DB name) G01S 7/00-7/42 G01S 13/00-13/95 H04L 7/00

Claims (2)

(57) [Claims] 1. A pseudo noise sequence advanced by 1/2 bit and 1 /
A shift register for generating a pseudo-noise sequence delayed by 2 bits, a multiplier for multiplying each of the pseudo-noise sequences generated by the shift register with an input signal, and a detector for performing envelope detection on the output of each of the multipliers When a subtracter for generating an error signal from the difference between the output of each detector is controlled oscillation frequency based on the error signal from the subtracter, oscillator and you generate a clock signal to the shift register Changing the phase of the pseudo-noise sequence output from the shift register to determine the phase advance of the correlation value of the composite wave of the input signal obtained by adding the multipath wave to the original signal wave.
And a detection circuit for detecting the peak of the original signal wave based on the first change point of the correlation value of the composite wave searched by the phase search circuit. And a direct sequence synchronization circuit. 2. A pseudo noise sequence advanced by 1/2 bit and 1 /
A shift register for generating a pseudo-noise sequence delayed by 2 bits, a switch for selecting the pseudo-noise sequence generated by the shift register, a dither generator for controlling a switching operation of the switch, and the switch A multiplier for multiplying the pseudo-noise sequence selected by the above with an input signal, a detector for performing envelope detection on an output of the multiplier, and a multiplier for multiplying an output of the detector by an output of the dither generator When the oscillation frequency based on an output of the multiplier is controlled, an oscillator that occur a clock signal to the shift register, by changing the phase of the pseudo-noise sequence output from the shift register, the original signal Write phase delay correlation value of the composite wave of the input signal plus a multipath wave into a wave from the side of the leading phase
A phase search circuit which slide into the search in turn, first correlation value of the composite wave to be searched by the phase search circuit
And a detection circuit for detecting the peak of the original signal wave based on the first change point.