JPH07297757A - Spread spectrum receiver - Google Patents

Abstract

PURPOSE:To attain inverse spread spectrum processing by generating a spread code synchronously with a reception signal with a simple circuit configuration and to reduce the time required for synchronization. CONSTITUTION:A PLL is formed by a phase comparator 20, an LPF 21 and a VCXO 22, an output signal of the VCXO 22 is fed to a PN code generator as a clock to control timing of generation of the PN code. Furthermore, an output signal of the VCXO 22 is multiplied with the PN code at a 1st multiplier 25 and the multiplied signal and the received spread spectrum signal are given to a phase comparator 20 to compare the phases. Thus, the PLL is operated so as to eliminate a phase error between the multiplied signal and the reception signal and the PN code synchronously with the reception signal is obtained and the PN code is multiplied with the reception signal by a 2nd multiplier and then accurate inverse spread processing is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum receiving apparatus for receiving a signal spread spectrum by using a predetermined code and despreading it.

[0002]

2. Description of the Related Art Conventionally, as one of wireless communication systems,
Spread spectrum communication systems are widely known. In this system (particularly, the direct spread system), on the transmitting side, a carrier is modulated with an information signal such as voice and data, and the information modulated signal is multiplied by a spread code such as an M sequence to perform spectrum spreading. Then, the spectrum-spread signal is converted into a radio frequency and transmitted from the antenna. on the other hand,
On the receiving side, the received spread spectrum signal is multiplied by the same spreading code as on the transmitting side to despread, and thereby the received signal is returned to an information-modulated signal and then information demodulated to obtain an information signal. I am trying.

In such a spread spectrum communication system,
When despreading on the receiving side, the spreading code created on the receiving side must be multiplied in synchronization with the spreading code in the received signal. Therefore, conventionally, a configuration called a delay lock loop (hereinafter referred to as DLL) shown in FIG. 4 has been adopted.

That is, in the DLL, the signal received by the antenna 1 is converted from the radio frequency to a lower frequency by the frequency conversion circuit 2, and the converted spread spectrum signal is divided into the first, second and third signals. Two multipliers 3, 4,
Input to 5. 6 is a spreading code PN (pseudo noise)
A PN code generator composed of a shift register for generating a code, the first PN output from the n-th stage
The code is input to the multiplier 4, is multiplied by the spread spectrum signal, and is output from the (n-1) th stage next to the 1st bit.
Is input to the multiplier 5 and is multiplied by the spread spectrum signal. The outputs of the multipliers 4 and 5 are detected by the envelope detectors 7 and 8, respectively, and the difference is taken by the comparator 9,
A signal according to the difference is applied to the voltage controlled crystal oscillator VCXO11 via the low pass filter LPF10. Then, the output signal of this VCXO 11 is the PN code generator 6
It is applied as a clock.

As shown in FIGS. 5 (A) and 5 (B), the correlation outputs of the envelope detectors 7 and 8 are respectively high level when synchronized and become 0 when deviated by 1 bit or more. Since these two triangular waves are shifted by 1 bit, when the difference of the triangular groups is taken by the comparator 9,
A combined correlation signal as shown in (C) is obtained. In this example, VCXO1 is set so that the difference signal from the comparator 9 is eliminated.
The output frequency of 1 changes and the output timing of the PN code changes accordingly.
A loop works so as to reach the tracking point a at the 0 level in (C).

Here, since point a is located in the middle of the synchronization points of two PN codes shifted by 1 bit, and the time corresponding to 1 bit of the PN code is 1T (chip),
The second PN code from the (n-1) th stage in which the phase is advanced is delayed by T / 2 by the 1 / 2T delay unit 12, and this delayed signal is multiplied by the received spread spectrum signal by the multiplier 3. Then, despreading can be performed with the PN code synchronized with the received signal. Then, the information signal can be taken out by inputting the despread signal in this way to the information demodulation circuit (also referred to as a primary demodulation circuit) 13.

[0007]

In the conventional DLL, if the loss of synchronization is within 1 bit, it effectively follows.
When the number of bits is equal to or more than a bit, the output of the envelope detector becomes 0 level, which makes it impossible to follow up. Therefore, in order to capture the initial synchronization, it is necessary to add a circuit such as a sliding correlator that forcibly drives the synchronization within a 1-bit range in which the synchronization can be followed. There was a problem that it took a long time.

Further, since two loops using two multipliers are formed, if the loop gains do not match, FIG.
An offset occurs at the tracking point “a” of the composite correlation signal, and the synchronization point shifts, and an accurate PN code cannot be reproduced. Further, when the electric field intensity of the received signal is strong, the output from the envelope detector is saturated as shown in FIG. 5D and the apex portion of the triangular wave disappears, so that the synchronization point is detected. It gets harder. For this reason, it is necessary to provide an AGC circuit for adjusting the electrolytic strength of the received signal to an appropriate level, which tends to make the circuit configuration more complicated.

It is therefore an object of the present invention to provide a spread spectrum receiving apparatus which has a simple structure and is capable of performing spectrum despreading with an accurate spread code synchronized with a received signal.

[0010]

According to the present invention, there is provided a phase comparator which compares the phases of signals input to a first terminal and a second terminal and outputs an error signal corresponding to a phase error, and a phase comparator which responds to the error signal. Frequency variable oscillator whose oscillation frequency changes, a spread code generating circuit for generating a spread code based on the output signal of the frequency oscillator, a spread code output from the spread code generating circuit, and an output signal of the frequency variable oscillator. A first multiplier that multiplies the frequency-variable oscillator, and a frequency conversion circuit that frequency-converts the received spread spectrum signal using the output signal of the variable frequency oscillator or a multiplied signal thereof as a local oscillation frequency signal,
A second multiplier for performing despreading by multiplying an output signal of the frequency conversion circuit and a spreading code output from the spreading code generation circuit, and an output signal of the first multiplier of the phase comparator; The input signal is input to the first terminal, and the output signal of the frequency conversion circuit is input to the second terminal of the phase comparator.
This is to solve the above problem.

According to the present invention, a signal line for deriving the output signal of the frequency conversion circuit to the second terminal of the phase comparator and a signal line for deriving the output signal of the frequency conversion circuit to the second multiplier. The first and second amplifiers are respectively inserted in the above, and the gain of the first amplifier is made larger than that of the second amplifier.

[0012]

In the present invention, the PLL is constituted by the phase comparator and the variable frequency oscillator, and the received spread spectrum signal is frequency-converted by using the output signal of the variable frequency oscillator or its multiplied signal as the local oscillation frequency signal. Therefore, the frequency conversion result includes the phase information of the output signal of the frequency variable oscillator. Further, a spread code is generated based on the output signal of the frequency variable oscillator, the spread code and the output signal of the frequency variable oscillator are multiplied by the first multiplier, and a signal of the same level as the received signal is generated. The signal and the frequency-converted signal are compared in phase by a phase comparator. Therefore, the PLL operates so as to eliminate the phase error between the multiplication output and the signal after frequency conversion, thereby generating a spread code synchronized with the received signal, and the spread code is multiplied by the received signal by the second multiplier. Due to this, accurate despreading is realized.

Further, in the present invention, since the amplifier having a small gain is inserted in the signal line to the second multiplier for performing the despreading, the noise component does not increase, and the first component is used.
Since a high-gain amplifier is inserted in the signal line to the multiplier, the signal level required to operate the PLL can be obtained.

[0014]

1 is a block diagram showing the configuration of an embodiment of the present invention, in which 1 and 13 are the same antenna and information demodulation circuit as in the conventional example. Reference numeral 20 denotes a phase comparator PD that compares the phases of the signals d (t) and C (t) input to the first and second terminals and outputs an error signal according to the phase error. Reference numeral 21 denotes a phase comparator PD20. A low pass filter LPF connected to
Reference numeral 22 denotes an oscillation output frequency that changes according to an error signal input via the LPF, and the phase comparator PD20 and the LPF2
Controlled voltage controlled crystal oscillator VCX that composes PLL with 1
O and 23 are frequency dividers for dividing the output of the VCXO 22 by N1,
24 is a PN code generator that generates a PN code m (t) as a spread code based on the frequency-divided output signal, and 25 is a first multiplication that multiplies the input spread spectrum signal C (t) by the output signal CS of the VCXO 22. , 27 is a PN code generator 24
Is a second multiplier that multiplies the PN code m (t) generated from the input spread spectrum signal C (t), and this output signal b (t) is input to the information demodulation circuit 13. Also, the output signal d of the first multiplier 25 of the phase comparator PD
(T) is input, and the spread spectrum signal C is input to the second terminal.
(T) is input.

Here, the PN code generator 24 is, for example,
The circuit configuration is composed of a shift register 100 and an exclusive OR gate 101 as shown in FIG. 2 and generates an m-sequence code. The output signal of the frequency divider 23 is input to the clock terminal CK of the shift register 100 and finally The output of the stage is input to the first and second multipliers 25 and 27. Further, in the present embodiment, further, a multiplier 28 that multiplies the output frequency of the VCXO 22 by N2 (N2 is a positive integer including 1), and the output of this multiplier 28 is the local oscillation frequency signal L.
A frequency converter 29 which converts the frequency of the received signal Ci (t) received as an input (t) from the antenna 1 into a signal f (t) having a frequency lower by the local oscillation frequency, and the output of the frequency converter 29. And a bandpass filter BPF30 for removing high frequency components in the signal.

Further, a first amplifier 31 is inserted in the signal line for leading the output signal of the BPF 30 to the first multiplier 25,
The second amplifier 32 is inserted in the signal line for deriving the output signal of the BPF 30 to the second multiplier 27, the gain A1 of the first amplifier 31 is set large, and the gain A2 of the second amplifier 32 is set small. . This is because it is not necessary to amplify the spread spectrum signal itself with a large gain because a large amount of power can be obtained by the process gain when the spread spectrum signal is despread, and such amplification rather increases the noise component. Is not preferable. on the other hand,
A certain level or more of electric power is required to operate the PLL, and therefore, even if only one amplifier is inserted immediately after the BPF 30 in FIG. 1, it is difficult to properly select its gain. Therefore, as shown in FIG. 1, by reducing the gain A2 of the amplifier 32 inserted in the signal line for despreading, deterioration of the SN ratio is prevented, and the gain A1 of the amplifier 31 inserted in the signal line for PLL is reduced. By increasing the size, the PLL can be operated reliably.

The operation of this embodiment will be described below with reference to the timing chart of FIG. First, the spread spectrum signal Ci (t) received by the antenna 1 is converted by the frequency converter 29 into a signal f (t) having a frequency lower by the local oscillation frequency L (t). Local oscillation frequency L
(T) is the output CS of the PLL VCXO 22 multiplied by the multiplier 2
8 is a signal multiplied by N2 (N2 is a positive integer including 1), and the spread spectrum signal Ci (t) is a signal obtained by multiplying the information modulation signal by the PN code on the transmission side.

Therefore, the PN code is m (t) and the information modulated wave is

[0019]

[Equation 1]

The output signal CS of the VCXO 22
If the received signal has the same frequency and the phase is different,

[0021]

[Equation 2]

And the local oscillation frequency signal L after multiplication
(T) is

[0023]

[Equation 3] Is expressed as Here, the received spread spectrum signal Ci
(T)

[0024]

[Equation 4] Then, the output signal f (t) of the frequency converter 29 is

[0025]

[Equation 5] Is expressed as Of these, the sum component is removed by the BPF 30, so only the difference component is taken out. Therefore, C (t) is

[0026]

[Equation 6] As shown in, the phase component θo / N2 of the VCXO 22 is included. This output signal C (t) (FIG. 3A) is
The phase comparator PD is amplified by the gain A1 by the amplifier 31.
It is input to the second terminal of 20. On the other hand, the output signal CS (FIG. 3B) of the VCXO 22 is frequency-divided by the frequency divider 23 to N1 / 1, and the frequency-divided signal is input as the clock signal of the PN code generator 24. Is changed, the PN code m (t) (FIG.
The output timing of C) changes. Then, the PN code m (t) output from the PN code generator 24 and the VCXO2
The second oscillation output signal CS is multiplied by the first multiplier 25. Therefore, this multiplication yields a signal d (t) (FIG. 3D) having the same level as the spread spectrum signal,
This multiplication signal d (t) is phase-compared with the output signal C (t) of the amplifier 31 in the phase comparator PD20. Then, the PLL operates so as to eliminate the phase error of these signals, and the frequency of the VCXO changes.

Therefore, the PLL is controlled so that the multiplication signal d (t) of the same level as the spread spectrum signal generated on the receiving side is synchronized with the actual spread spectrum signal C (t) received, whereby the multiplication signal d (t) is controlled. PN code generator 2
The PN code m (t) from 4 becomes synchronized with the PN code in the received signal. Therefore, the PN code m (t) synchronized with the received signal C (t) is multiplied by the spread spectrum signal C (t) by the second multiplier 27, whereby despreading is executed. Then, the information modulation signal obtained by such despreading is sent to the information demodulation circuit 13, where the information signal is taken out.

Here, the output d (t) of the first multiplier 25
From the equation (2),

[0029]

[Equation 7] Therefore, the output signal of the phase comparator PD20 is expressed by the following equation.

[0030]

[Equation 8] Since the sum component is removed by the LPF 21 in the equation (8), only the difference component represented by the following equation (9) is extracted.

[0031]

[Equation 9] That is, the VCXO2 is converted by the phase error signal shown in the equation (9).
2 will be controlled and synchronization will be established. In the synchronized state, m ² (t) becomes “1”. As the phase comparator 20, since the duty of the received signal is not 50%, it is preferable to use an edge detection type digital phase comparator.

[0032]

According to the present invention, a special circuit for initial acquisition and an AGC circuit are not required, the circuit configuration is very simple and high-speed synchronization can be realized, and moreover, it is generated by using a plurality of loops. Since there is no influence of the offset, etc., at all times, an accurate spreading code synchronized with the received signal can always be reproduced, and despreading can be performed using this spreading code.

Further, according to the present invention, the received spread spectrum signal is frequency-converted by using the output signal of the variable frequency oscillator of the PLL or its multiplied signal as the local oscillation frequency signal, so that the phase information of the output signal of the variable frequency oscillator is converted into the frequency. Since it can be included in the output of the conversion circuit, the synchronization operation can be performed more easily, and the time required for synchronization can be shortened.

Further, in the present invention, an amplifier having a small gain is inserted in the signal line to the second multiplier for performing despreading, and the gain is provided in the signal line to the first multiplier for forming the PLL. Since a large amplifier is inserted, the signal level required to operate the PLL can be reliably obtained without deteriorating the SN ratio.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a PN code generator in the embodiment.

FIG. 3 is a timing chart of each signal in the example.

FIG. 4 is a block diagram showing a configuration of a conventional DLL.

FIG. 5 is a timing chart of each signal in the DLL.

[Explanation of symbols]

 1 Antenna 2,29 Frequency Converter 13 Information Demodulation Circuit 20 Phase Comparator (PD) 21 LPF 22 VCXO 24 PN Code Generator 25 First Multiplier 27 Second Multiplier 28 Multiplier 30 BPF 31,32 Amplifier

Claims (2)

[Claims] 1. A phase comparator that compares the phases of signals input to a first terminal and a second terminal and outputs an error signal according to a phase error, and a frequency variable whose oscillation frequency changes according to the error signal. An oscillator, a spreading code generation circuit for generating a spreading code based on an output signal of the frequency oscillator, and a first multiplier for multiplying the spreading code output from the spreading code generation circuit by the output signal of the frequency variable oscillator. A frequency conversion circuit that frequency-converts the received spread spectrum signal using the output signal of the variable frequency oscillator or its multiplied signal as a local oscillation frequency signal, and the output signal of the frequency conversion circuit and the spread code generation circuit. A second multiplier for performing despreading by multiplying with a spreading code, and inputting an output signal of the first multiplier to a first terminal of the phase comparator,
The output signal of the frequency conversion circuit is supplied to the second phase comparator.
A spread spectrum receiver characterized in that input is made to a terminal. 2. The apparatus according to claim 1, wherein a signal line for deriving an output signal of the frequency conversion circuit to a second terminal of the phase comparator and an output signal of the frequency conversion circuit to the second multiplier. First and second amplifiers are inserted in the derived signal lines, respectively, and the gain of the first amplifier is set to the second value.
Spread spectrum receiver characterized in that the gain is larger than that of the amplifier.