JPH07297756A - Spread spectrum receiver - Google Patents

Abstract

PURPOSE:To attain inverse spread spectrum processing by generating a spread code synchronously with a reception signal with a simple circuit configuration. CONSTITUTION:A PLL is formed by a phase comparator 20, an LPF 21 and a VCXO 22, an output signal of the VCXO 22 is multiplied with a spread spectrum signal received by a 1st multiplier to obtain a signal of a spread code level. The signal of the spread code level and the PN code generated by a receiver side are given to the phase comparator 20, in which the phases are compared. Then an oscillated output signal is applied to a PN code generator 24 as a clock to control a timing of generation of a PN code. Thus, the PLL is operated so as to eliminate a phase error between the multiplied signal of the spread code level and an oscillated output signal and the spread code synchronously with the reception signal is obtained and the PN code is multiplied with the reception signal by a 2nd multiplier and then accurate inverse spread processing is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum receiving apparatus for receiving a signal spread spectrum by using a predetermined code and despreading it.

[0002]

2. Description of the Related Art Conventionally, as one of wireless communication systems,
Spread spectrum communication systems are widely known. In this system (particularly, the direct spread system), on the transmitting side, a carrier is modulated with an information signal such as voice and data, and the information modulated signal is multiplied by a spread code such as an M sequence to perform spectrum spreading. Then, the spectrum-spread signal is converted into a radio frequency and transmitted from the antenna. on the other hand,
On the receiving side, the received spread spectrum signal is multiplied by the same spreading code as on the transmitting side to despread, and thereby the received signal is returned to an information-modulated signal and then information demodulated to obtain an information signal. I am trying.

In such a spread spectrum communication system,
When despreading on the receiving side, the spreading code created on the receiving side must be multiplied in synchronization with the spreading code in the received signal. Therefore, conventionally, a configuration called a delay lock loop (hereinafter referred to as DLL) shown in FIG. 5 has been adopted.

That is, in the DLL, the signal received by the antenna 1 is converted from the radio frequency to a lower frequency by the frequency conversion circuit 2, and the converted spread spectrum signal is divided into the first, second and third signals. Two multipliers 3, 4,
Input to 5. 6 is a spreading code PN (pseudo noise)
A PN code generator composed of a shift register for generating a code, the first PN output from the n-th stage
The code is input to the multiplier 4, is multiplied by the spread spectrum signal, and is output from the (n-1) th stage next to the 1st bit.
Is input to the multiplier 5 and is multiplied by the spread spectrum signal. The outputs of the multipliers 4 and 5 are detected by the envelope detectors 7 and 8, respectively, and the difference is taken by the comparator 9,
A signal according to the difference is applied to the voltage controlled crystal oscillator VCXO11 via the low pass filter LPF10. Then, the output signal of this VCXO 11 is the PN code generator 6
It is applied as a clock.

As shown in FIGS. 6A and 6B, the correlation outputs of the envelope detectors 7 and 8 are high level when they are synchronized and become 0 when they are deviated by 1 bit or more, respectively. Since these two triangular waves are deviated by 1 bit, if the difference between the triangular groups is taken by the comparator 9, FIG.
A combined correlation signal as shown in (C) is obtained. In this example, VCXO1 is set so that the difference signal from the comparator 9 is eliminated.
The output frequency of 1 changes, and the output timing of the PN code changes accordingly.
A loop works so as to reach the tracking point a at the 0 level in (C).

Here, since point a is located in the middle of the synchronization points of two PN codes shifted by 1 bit, and the time corresponding to 1 bit of the PN code is 1T (chip),
The second PN code from the (n-1) th stage in which the phase is advanced is delayed by T / 2 by the 1 / 2T delay unit 12, and this delayed signal is multiplied by the received spread spectrum signal by the multiplier 3. Then, despreading can be performed with the PN code synchronized with the received signal. Then, the information signal can be taken out by inputting the despread signal in this way to the information demodulation circuit (also referred to as a primary demodulation circuit) 13.

[0007]

In the conventional DLL, if the loss of synchronization is within 1 bit, it effectively follows.
When the number of bits is equal to or more than a bit, the output of the envelope detector becomes 0 level, which makes it impossible to follow up. Therefore, in order to capture the initial synchronization, it is necessary to add a circuit such as a sliding correlator that forcibly drives the synchronization within a 1-bit range in which the synchronization can be followed. There was a problem that it took a long time.

Further, since two loops using two multipliers are formed, if the loop gains do not match, FIG.
An offset occurs at the tracking point “a” of the composite correlation signal, and the synchronization point shifts, and an accurate PN code cannot be reproduced. Further, when the electric field intensity of the received signal is strong, the output from the envelope detector is saturated as shown in FIG. 6 (D) and the apex portion of the triangular wave disappears, so that the synchronization point is detected. It gets harder. For this reason, it is necessary to provide an AGC circuit for adjusting the electrolytic strength of the received signal to an appropriate level, which tends to make the circuit configuration more complicated.

It is therefore an object of the present invention to provide a spread spectrum receiving apparatus which has a simple structure and is capable of performing spectrum despreading with an accurate spread code synchronized with a received signal.

[0010]

According to the present invention, there is provided a phase comparator which compares the phases of signals input to a first terminal and a second terminal and outputs an error signal corresponding to a phase error, and a phase comparator which responds to the error signal. Frequency variable oscillator whose oscillation frequency changes, a first multiplier that multiplies an output signal of the frequency variable oscillator and a received spread spectrum signal, and a spread code generator that generates a spread code based on the output signal of the frequency oscillator. Circuit,
A second multiplier for performing despreading by multiplying the spread code output from the spread code generating circuit by the received spread spectrum signal, wherein the output signal of the first multiplier is the first signal of the phase comparator; The above problem is solved by inputting the spread code output from the spread code generation circuit to the second terminal of the phase comparator.

Further, according to the present invention, the first spreads the received spread spectrum signal to the signal lines for leading the spread spectrum signal to the first and second multipliers, respectively.
And a second amplifier is inserted, and the gain of the first amplifier is made larger than that of the second amplifier. Further, the present invention is characterized by further comprising a frequency conversion circuit for frequency-converting the received spread spectrum signal by using the output signal of the variable frequency oscillator or its multiplied signal as a local oscillation frequency signal.

[0012]

According to the present invention, a PLL is composed of a phase comparator and a variable frequency oscillator, and the output signal of this variable frequency oscillator is multiplied by the spread spectrum signal received by the first multiplier to generate a signal at the spread code level. can get. The spread code level signal is phase-compared with the spread code generated on the receiving side, and the generation of the spread code is controlled based on the output signal of the frequency variable oscillator. Therefore, the PLL operates so as to eliminate the phase error between the multiplied spread code level signal and the spread code generated on the receiving side, whereby a spread code synchronized with the received signal is generated, and this spread code is generated by the second multiplier. It is multiplied with the received signal to achieve accurate despreading.

Further, in the present invention, since the amplifier having a small gain is inserted in the signal line to the second multiplier for performing the despreading, the noise component does not increase, and the first component is used.
Since a high-gain amplifier is inserted in the signal line to the multiplier, the signal level required to operate the PLL can be obtained. Further, according to the present invention, the received spread spectrum signal is frequency-converted using the output signal of the frequency variable oscillator of the PLL or its multiplied signal as the local oscillation frequency signal. Is included in the output of, and the synchronous operation is performed more easily.

[0014]

1 is a block diagram showing the configuration of an embodiment of the present invention, in which 1, 2, 13 are the same antennas as in the conventional example,
A frequency converter and an information demodulation circuit. Reference numeral 20 is a phase comparator PD that compares the phases of the signals e (t) and m (t) input to the first and second terminals and outputs an error signal according to the phase error. Reference numeral 21 is a phase comparator PD20. The low-pass filters LPF and 22 connected to the output of the phase comparator P change their oscillation output frequency according to the error signal input through the LPF.
A voltage controlled crystal oscillator VCXO, 23 forming a PLL together with D20 and LPF21 outputs the output of VCXO22 to N.
A frequency divider for frequency division, 24 a PN code generator for generating a PN code m (t) as a spread code based on the frequency division output signal,
25 is the received spread spectrum signal c (t) and VCXO
22 is a first multiplier for multiplying the output signal cs of 22;
Low-pass filter LP connected to output of multiplier 25
F and 27 are PN codes m generated from the PN code generator 24.
This is a second multiplier for multiplying (t) by the received spread spectrum signal c (t), and this output signal b (t) is input to the information demodulation circuit 13. In addition, the first of the phase comparator PD
The output signal e (t) of the LPF 26 is input to the terminal, and the PN code m (t) from the PN code generator is input to the second terminal.

Here, the PN code generator 24 is, for example,
The circuit configuration is composed of a shift register 100 and an exclusive OR gate 101 as shown in FIG. 2 and generates an m-sequence code. The output signal of the frequency divider 23 is input to the clock terminal CK of the shift register 100 and finally The output of the stage is input to the second multiplier 27 and the phase comparator PD20.

The operation of this embodiment will be described below with reference to the timing chart of FIG. First, the spread spectrum signal received by the antenna 1 is converted from a radio frequency to a lower frequency by the frequency converter 2, and its output signal c (t) is the oscillation output signal CS of the VCXO 22 constituting the PLL and the first multiplier. It is multiplied by 25 to obtain a spread code level signal d (t). And this signal is L
Only the low frequency component is extracted by the PF 26, and this signal e (t) is phase-compared with the PN code m (t) from the PN code generator 24 in the phase comparator PD20. Then, the PLL operates so that the phase error of these signals is eliminated, and the frequency of the VCXO changes. Here, since the PN code m (t) from the PN code generator 24 is input as a clock signal, a signal obtained by dividing the frequency of the VCXO 22 is input, V
When the oscillation frequency of the CXO 22 changes, the PN
The output timing of the code changes.

Therefore, the PN code m (t) from the PN code generator 24 is PL so as to be synchronized with the spread code in the received signal.
L will be controlled and will lock in the synchronized state. Therefore, the PN code m synchronized with the received signal c (t)
Despreading will be performed by multiplying (t) by the spread spectrum signal c (t) received by the second multiplier 27. Then, the information modulation signal obtained by such despreading is sent to the information demodulation circuit 13, where the information signal is taken out.

FIG. 3D shows a state in which the oscillation output signal CS is not yet synchronized with the received signal. When this signal CS is multiplied by the received signal c (t), the signal d shown in FIG. 3E is obtained.
(T). Then, the low frequency component e (t) of this signal
3C and the PN code in FIG. 3C are compared in phase, and when the phase difference disappears, the PN code m (t) becomes a code synchronized with the received signal as shown in FIG. 3C.

Next, the operation will be described in detail using mathematical expressions. PN code is m (t), information modulated wave is

[0020]

[Equation 1]

Then, the received spread spectrum signal c
(T) is

[0022]

[Equation 2]

It is expressed as follows. Further, assuming that the output signal CS of the VCXO 22 has the same frequency as the received signal and has a different phase,

[0024]

[Equation 3] Is expressed as Therefore, the output signal of the first multiplier 25 is

[0025]

[Equation 4] Is expressed as In this equation (4), the sum component is LPF26.
Therefore, only the difference component represented by the following equation (5) is extracted.

[0026]

[Equation 5] Therefore, the output signal of the phase comparator PD20 is

[0027]

[Equation 6] Is expressed as That is, the VCXO 22 is controlled by the phase error signal represented by the equation (6), and the synchronization is established. In the synchronized state, m ² (t) becomes “1”. Next, another embodiment of the present invention will be described with reference to FIG.

First, the difference from the embodiment shown in FIG.
In addition, the first amplifier 3 is connected to the input signal line to the first multiplier 25.
1 is inserted into the second input signal line to the second multiplier 27
The amplifier 32 is inserted, the gain A1 of the first amplifier 31 is set large, and the gain A2 of the second amplifier 32 is set small. This is because it is not necessary to amplify the spread spectrum signal itself with a large gain because a large amount of power can be obtained by the process gain when the spread spectrum signal is despread, and such amplification rather increases the noise component. Is not preferable. On the other hand, a certain level of power is required to operate the PLL, and therefore, even if only one amplifier is inserted immediately after the frequency converter 25 in FIG. 1, it is difficult to properly select the gain. is there. Therefore, as shown in FIG. 4, by reducing the gain A2 of the amplifier 32 inserted in the signal line for despreading, deterioration of the SN ratio is prevented, and the gain A1 of the amplifier 31 inserted in the signal line for PLL is reduced. PL by increasing
L can be operated reliably.

Further, in this embodiment, the VCXO 22 is further provided.
Is multiplied by N2 (N2 is a positive integer including 1), and the output of this multiplier 28 is input as a local oscillation frequency signal L (t), and the frequency of the received signal Ci (t) is input. A frequency converter 29 for converting into a signal f (t) having a frequency lower by the local oscillation frequency and a bandpass filter BPF 30 connected to the output of the frequency converter 29 for removing high frequency components in the signal are provided.

Therefore, the local oscillation frequency signal L (t) is

[0031]

[Equation 7] And the received spread spectrum signal Ci (t) is

[0032]

[Equation 8] Then, the output signal f (t) of the frequency converter 29 is

[0033]

[Equation 9] Is expressed as Of these, the sum component is removed by the BPF 30, so that only the difference component represented by the following equation is taken out. Therefore, C (t) is

[0034]

[Equation 10] As shown in, the phase component θo / N2 of the VCXO 22 is included. Since this signal is multiplied by the output of the VCXO 22 and input to the PLL, as in the first embodiment, the synchronization operation can be made easier and the time required for synchronization can be shortened.

An edge detection type digital phase comparator is preferably used as the phase comparator 20.

[0036]

According to the present invention, a special circuit for initial acquisition and an AGC circuit are not required, the circuit configuration is very simple and high-speed synchronization can be realized, and moreover, it is generated by using a plurality of loops. Since there is no influence of the offset, etc., at all times, an accurate spreading code synchronized with the received signal can always be reproduced, and despreading can be performed using this spreading code.

Further, in the present invention, an amplifier having a small gain is inserted in the signal line to the second multiplier for performing despreading, and the gain is provided in the signal line to the first multiplier for configuring the PLL. Since a large amplifier is inserted, the signal level required to operate the PLL can be reliably obtained without deteriorating the SN ratio. Further, in the present invention, P
Since the received spread spectrum signal is frequency-converted using the output signal of the variable frequency oscillator of LL or its multiplied signal as the local oscillation frequency signal, the phase information of the output signal of the frequency variable oscillator can be included in the output of the frequency conversion circuit. Therefore, the synchronization operation can be performed more easily.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an exemplary embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of a PN code generator in the embodiment.

FIG. 3 is a timing chart of each signal in the example.

FIG. 4 is a block diagram showing the configuration of another embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional DLL.

FIG. 6 is a timing chart of each signal in the DLL.

[Explanation of symbols]

 1 Antenna 2, 29 Frequency Converter 13 Information Demodulation Circuit 20 Phase Comparator (PD) 21 LPF 22 VCXO 24 PN Code Generator 25 First Multiplier 26 LPF 27 Second Multiplier 28 Multiplier 30 BPF 31, 32 Amplifier

Claims (3)

[Claims] 1. A phase comparator that compares the phases of signals input to a first terminal and a second terminal and outputs an error signal according to a phase error, and a frequency variable whose oscillation frequency changes according to the error signal. An oscillator, a first multiplier for multiplying an output signal of the variable frequency oscillator by a received spread spectrum signal, a spread code generation circuit for generating a spread code based on the output signal of the frequency oscillator, and the spread code generation circuit. And a second multiplier that performs despreading by multiplying the spread code output from the received spread spectrum signal by inputting the output signal of the first multiplier to the first terminal of the phase comparator, A spread spectrum receiving apparatus, wherein a spread code output from the spread code generating circuit is input to a second terminal of the phase comparator. 2. The apparatus according to claim 1, wherein first and second amplifying the received spread spectrum signal are respectively provided on signal lines for leading the received spread spectrum signal to the first and second multipliers. A spread spectrum receiver, wherein an amplifier is inserted and the gain of the first amplifier is made larger than that of the second amplifier. 3. The device according to claim 1, wherein
A spread spectrum receiving apparatus further comprising a frequency conversion circuit for converting the frequency of a received spread spectrum signal by using the output signal of the variable frequency oscillator or its multiplied signal as a local oscillation frequency signal.