JPH03255740A - Ds synchronizing circuit - Google Patents

Abstract

PURPOSE:To compensate the synchronizing step-out of a circuit by providing a fine phase variable circuit to finely vary the phase of a PN sequence on the output of a shift register and controlling the phase by a fine phase deciding circuit. CONSTITUTION:The fine phase variable circuit 13 can finely vary the phase of the PN sequence to be outputted from a shift register 5. The PN sequence to be outputted from the fine phase variable circuit 13 is multiplied with an input signal 8 by a multiplier 1 and passes through an envelope detector 3 and therefore, correlation between both signals can be detected. A fine phase deciding circuit 14 generates a signal to control the fine phase variable circuit 13, searches the phase and decides the phase so that the phase of the input signal 8 can be matched with the PN phase of the fine phase variable circuit 13, namely, that the peak of the correlation can be detected.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention is directed to a D S (Direct 5 sequence
e) This relates to a synchronous circuit used in a communication system.

[Conventional technology]

Conventionally, this type of synchronous circuit has been shown in FIG. In the figure, ■ is a multiplier, 2 is a BPF, 3 is an envelope detector, 4 is a subtracter, 5 is a shift register, and 6 is a VCo
, 7 is a loop filter, 8 is an input signal, 9 is a PN sequence advanced by 1/2 bit, 10 is a PN sequence delayed by 1/2 bit, 11 is an error signal, and 12 is a 1/2 bit delay circuit.

Next, the operation will be explained. The input signal 8 is a 1/2 bit advanced PN sequence 9. output from the shift register 5. The multiplier 1 multiplies the PN sequence 10 delayed by 1/2 bit. The signals multiplied by multiplier 1 are each B
After passing through the PF2 and taking the correlation, the signal is detected by the envelope detector 3. The subtracter 4 generates an error signal 11 by subtracting the detected signal multiplied by the 1/2 bit delayed PN sequence from the detected signal multiplied by the 1/2 bit advanced PN sequence. The error signal 11 is smoothed by the loop filter 7 and then supplied to the VCo 6 to generate a clock signal for driving the shift register 5.

This loop thus performs a control operation such that the delay contained in the input signal and the delay provided by the shift register 5 match. After synchronization is performed in this way, the PN sequence 9 advanced by 1/2 bit is processed by the 1/2 bit delay circuit 12.
The signal 15 is delayed by /2 bits and multiplied by the input signal, and a despread signal 15 is output.

[Problem to be solved by the invention]

Since the conventional DS synchronization method is configured as described above, if the free-running frequency of the VCO and the frequency of the input PN signal differ, a steady phase error may occur, or multipath waves of the human-powered PN signal may be input at the same time. If the
There were drawbacks such as a decrease in the processing gain of S.

This invention was made in order to solve the above-mentioned problems, and it is a D
The purpose is to obtain an S-synchronous circuit.

[Means to solve the problem]

The DS synchronization circuit according to the present invention is provided with a minute phase variable circuit for minutely varying the phase of a PN sequence at the output of a shift register, and the phase is controlled by a minute phase determining circuit.

Further, the DS synchronization circuit according to the present invention has Vc.

An adder is inserted in the front stage of the adder, and a minute phase determining circuit is provided which controls the output phase of the PN sequence, which is the output of the shift register, by applying a minute voltage to the adder.

[Effect]

The DS synchronization circuit according to the present invention can detect synchronization errors with very fine precision using a minute phase variable circuit or an adder and a minute phase determining circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a DS synchronization circuit according to a first embodiment of the present invention. In the figure, 13 is a minute phase variable circuit, and 14 is a minute phase determination circuit. The other parts are the same as in Fig. 2.

Next, the operation will be explained. The components from the multiplier 1 to the 1/2-bit delay circuit 12 are the same as the conventional one, but a minute phase variable circuit 13. By adding the minute phase determining circuit 14, it is possible to detect synchronization errors with very fine precision.

The minute phase variable circuit 13 can minutely vary the phase of the PN sequence output from the shift register 5. PN sequence output from minute phase variable circuit 13 and input signal 8
By multiplying by the multiplier 1 and passing it through the BPF 2 and the envelope detector 3, the correlation between the two signals can be detected. The minute phase determining circuit 14 generates a signal to control the minute phase variable circuit 13 and also performs a phase search, so that the phase of the input signal 8 and the PN of the minute phase variable circuit 13 match, that is, the peak of correlation can be detected. Determine the phase like this. In this way, it is possible to detect a synchronization error in the DS synchronization circuit.

In addition to the first embodiment described above, as a method for detecting synchronization errors in the DS synchronization circuit, as shown in another embodiment of the present invention shown in FIG. You may also do so. The conventional synchronous circuit can vary the phase of the PN sequence output from the shift register 5 by applying a minute voltage to the VCO 6 in a synchronized state. and 1
By determining the phase such that the phases of the PN series output from the /2-bit delay circuit 12 match, that is, the peak of the correlation can be detected, and adding a small voltage to the adder 15, the synchronization deviation of the DS synchronization circuit is suppressed. can be detected.

〔Effect of the invention〕

As described above, according to the present invention, a minute phase variable circuit is inserted in the output of the shift register, or an adder is inserted in the front stage of the VCO, and the phase of the PN series that is the output of the shift register is adjusted by the minute phase determining circuit. Since it is possible to control the DS synchronization circuit, it is effective in detecting synchronization errors in the DS synchronization circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a DS synchronization circuit according to a first embodiment of the present invention, FIG. 2 is a diagram showing a conventional DS synchronization method, and FIG. It is a figure which shows Example 2. 1... Multiplier, 2... BPF, 3... Envelope detector, 4... Subtractor, 5... Shift register, 6...
・■C017...Loop filter, 8...Input signal, 9...1/2 bit advanced PN sequence, 10...1
/2 bit delayed PN sequence, 11... error signal, 12
... 1/2 bit delay circuit, 13... Minute phase variable circuit, 14... Minute phase determining circuit, 15... Despread signal, 16... Adder. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (2)

[Claims] (1) In a DS (Direct Sequence) synchronous circuit, there is a minute phase variable circuit that minutely varies the phase of the PN sequence that is the output of the shift register, and a minute phase determination circuit that generates a signal that controls the output phase of this minute phase variable circuit. A DS characterized by being equipped with a circuit.
synchronous circuit. (2) In a DS (Direct Sequence) synchronous circuit, an adder is inserted before the VCO, and a minute voltage is applied to this adder, and the adder and the above-mentioned VC
1. A DS synchronization circuit comprising: a minute phase determining circuit for controlling the output phase of a PN series that is an output of a shift register that has passed through a phase shift register.