JPH04323925A - Synchronization tracing circuit - Google Patents

Abstract

PURPOSE:To realize a synchronization tracing circuit implementing accurate synchronization tracing even when the circuit constant of components of each circuit is deviated from its initial value due to a secular change or a temperature change. CONSTITUTION:Ths oscillation output of a voltage controlled oscillator 20 is used as a clock and fed to a PN code generator 19, and the sum and the subtraction of an early code and a rate code outputted from the PN code generator 19 and an input signal are multiplied respectively by multipliers 11, 12, the multiplication output is given respectively to band pass filters 14, 15, the output signal of the multiplier 22 and the output signal of the band pass filter 15 are multiplied by a multiplier 22, the output signal of the multiplier 22 is given to a low pass filter 25, smoothed by a loop filter 21 and the output of the loop filter 21 is applied to the voltage controlled oscillator 20 as a control voltage.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization tracking circuit having a delay locked loop.

0002

2. Description of the Related Art As shown in FIG. 3, a conventional synchronization tracking circuit uses the output of a voltage controlled oscillator (hereinafter referred to as VCO) 20 as a clock to generate a despreading PN code, and a phase difference from the despreading PN code. It includes a PN code generator 19 that generates an early code that is advanced by a fixed amount and a late code whose phase is delayed by a predetermined amount from the despreading PN code, and a multiplier 11 that calculates the product of the input signal and the early code, and then multiplies the input signal and the early code. The output of the detector 11 is passed through a band pass filter 14 to an envelope detector 16.
, a multiplier 12 calculates the product of the input signal and the rate code, the output of the multiplier 12 is passed through a bandpass filter 15 and detected by an envelope detector 17 , and from the output of the envelope detector 16 The output of the envelope detector 17 is subtracted by a subtracter 18
, the error signal is smoothed by a loop filter 21, and the output of the loop filter 21 is applied as a control signal to the VCO 20 to obtain a PN code sequence in which the phase of the oscillation output of the VCO 20 is included in the input signal. Tracking is continued by controlling the oscillation frequency so as to be synchronized with the phase of the clock, and the input signal and the despreading PN code are multiplied by a multiplier 13 to obtain a despread output.

In the conventional synchronization tracking operation described above, when the input signal is y(t) and the despreading PN code is PN(t), the horizontal axis represents the code sequence included in y(t) and PN( t) and the output voltage of the subtracter 18 on the vertical axis, the code sequence included in y(t) when the output of the envelope detector 17 is turned off and PN( The relationship between the phase difference with t) and the output voltage of the subtracter 18 at that time is shown in FIG.
Similarly, when the output of the envelope detector 16 is turned off, the result is as shown in FIG. 4(b),
The case where neither of the outputs of the envelope detectors 16 and 17 are turned off is as shown in FIG. 4(c). If the phase difference between the code sequence included in y(t) and PN(t) is between points AB in FIG. 4(c), the VCO 20 is controlled by negative feedback and the phase difference becomes near point S.

[0004] Below, the early code is E(t), the late code is L(t), and the carrier component at y(t) is co
sωt, the spreading code component is Y(t), and the data component is d(t
), y(t)=Y(t)d(t)cosωtY(t)=1,
-1, d(t)=1,-1, and E(t)=1,-1, L(t)=1,-1.

At this time, if the gain generated by passing through the multiplier 11, bandpass filter 14, envelope detector 16, and subtracter 18 is α (α>0), then the output of the envelope detector 17 is turned off. Since the output of the subtractor 18 in the state is the product of the correlation output of Y(t) and E(t) and α, it can be expressed as α·(Y(t)*E(t)). Here * represents the convolution integral.

[0006] Also, a multiplier 12, a band pass filter 15
, the gain generated by passing through the envelope detector 17 and the subtracter 18 is also α, so the output of the subtracter 18 when the output of the envelope detector 16 is turned off is Y(t)
Since it is the product of the correlation output of and L(t) and α multiplied by −1, it can be expressed as −α·(Y(t)*L(t)). Further, the output of the subtracter 18 when neither of the outputs of the envelope detectors 16 and 17 is turned off is α・
(Y(t)*E(t)-Y(t)*L(t)), so when PN(t) and Y(t) are synchronized, that is, Y(t)*E(t )=Y(t)*L(t), it becomes zero.

[0007]

However, according to the conventional synchronization tracking circuit described above, the multipliers 11 and 12, the bandpass filters 14 and 15, the envelope detectors 16 and 17, and the subtracter 1
Due to the influence of errors in the parts that make up each circuit in section 8,
Multiplier 11, bandpass filter 14, envelope detector 16
and the gain of the correlation output of Y(t) and E(t) produced by passing through the subtracter 18, and the gain of the correlation output of Y(t) and E(t) produced by passing through the multiplier 12, bandpass filter 15, envelope detector 17, and subtracter 18. When the gains of the correlation outputs of t) and E(t) are different, and the gain of the former is α and the gain of the latter is β (α>β>0), the output of the subtractor 18 is α・(Y (t)*E(t))-β(Y(t)*L(t)
), Y(t) and PN(t) are synchronized, and Y(t)*
Even when E(t)=Y(t)*L(t), it does not become zero.

This is shown in FIGS. 4(a), (b) and (c).
) is equivalent to becoming as shown in FIGS. 5(a), (b), and (c), respectively, and as is clear from FIG. 5(c), the code sequence included in y(t) and PN(t ) is not zero and locks in the vicinity of point P, resulting in a problem that synchronous tracking cannot be performed correctly.

It is an object of the present invention to provide a synchronization tracking circuit having a configuration in which gain imbalance due to errors and variations in circuit components can be ignored, and effects of errors and variations in circuit components on synchronization tracking errors can be ignored. With the goal.

0010

[Means for Solving the Problems] The synchronization tracking circuit of the present invention uses the output of a voltage controlled oscillator as a clock to generate a despreading PN.
A PN code generator that outputs three PN codes: an early code whose phase is ahead of the despreading PN code by a predetermined amount, and a late code whose phase is delayed by a predetermined amount from the despreading PN code, and the early code and the late code. a subtracter that subtracts the late code from the early code; a first multiplier that multiplies the input signal by the output signal of the adder; and a first multiplier that multiplies the input signal and the output signal of the subtracter. Second to do
a multiplier; a first band-pass filter that receives the output signal of the first multiplier; a second band-pass filter that receives the output signal of the second multiplier; The output signal of the two bandpass filters is multiplied by the third
a multiplier, a low-pass filter that receives the output signal of the third multiplier, a loop filter that receives the output signal of the low-pass filter, and a fourth multiplier that multiplies the despreading PN code by the input signal. The output signal of the loop filter is supplied as a control voltage to the voltage controlled oscillator, and the output signal of the voltage controlled oscillator is tracked so that the phase of the output of the voltage controlled oscillator is synchronized with the phase of the clock of the code sequence included in the input signal. shall be.

[0011]

[Operation] In the synchronization tracking circuit of the present invention, the gain of the first multiplier, the gain of the first band-pass filter, the gain of the second multiplier, the gain of the second band-pass filter, and the gain of the low-pass filter are all multiplied. Therefore, as long as the product of these gains is constant, the size of each gain is unrelated to the error in synchronization tracking, so the circuit error caused by errors in each circuit component or the effects of variations can be avoided. Errors in synchronous tracking due to gain imbalance can be ignored, and accurate synchronous tracking can be achieved regardless of errors and variations in the components of each circuit.

0012

[Examples] The present invention will be explained below with reference to Examples.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In this embodiment, the same components as those in the conventional example shown in FIG. 3 are denoted by the same reference numerals. Subtractor 2 subtracts late code L(t) from early code E(t) output from PN code generator 19.
3, and the adder 24 adds the early code E(t) and the late code L(t). The input signal y(t) and the output of the subtracter 23 are multiplied by the multiplier 11, and the input signal y(t) and the output of the adder 24 are multiplied by the multiplier 12.
Multiply by The output of the multiplier 11 is passed through the bandpass filter 14
The output of the multiplier 12 is supplied to a band pass filter 15 to pass signals in a predetermined band. A multiplier 22 multiplies the output of the bandpass filter 14 and the output of the bandpass filter 15.

Here, the output of the multiplier 22 is supplied to a low-pass filter 25, the output of the low-pass filter 25 is taken out as an error signal, and the error signal is sent to the loop filter 21.
Supply and smooth. The output of the loop filter 21 is V
A control voltage is applied to the CO 20 to control the oscillation frequency of the VCO 20, and tracking is continued so that the phase of the oscillation output of the VCO 20 is synchronized with the phase of the clock of the code series included in the input signal y(t). The oscillation output of VCO20 is PN
The despreading PN code PN(t) supplied to the code generator 19 and output from the PN code generator 19 and the input signal y(t
) in the multiplier 13 to perform despreading.

The synchronization tracking operation in this embodiment configured as described above is performed by using two envelope detectors 16 and 17 in FIG.
Similar to the case of using a multiplicative detector, the vertical axis represents the output voltage of the low-pass filter 25, and the phase difference between the code sequence included in the input signal y(t) and the despreading PN code PN(t). If it is plotted on the horizontal axis, it will become as shown in Figure 2, and the input signal y(
t) and the despreading PN code PN(t)
If there is a phase difference between points AB, the VCO 20 is controlled by negative feedback, and the phase difference becomes near point S. In FIG. 2, the distance between points AC and between points BD is a quadratic curve.

Here, the output of the subtracter 23 is aE(t)-
bL(t), (a, b>0) The output of the adder 24 is cE(t)+dL(t), (c, d>0), and the gain generated in the multiplier 11 and bandpass filter 14 is γ( γ>0), multiplier 12 and bandpass filter 15
When the gain generated in the multiplier 22 and the low-pass filter 25 is ε (ε>0), the output of the low-pass filter 25 is 0.5γ
δε・(aY(t)*E(t)−bY(t)*L(t)
) ・(cY(t)*
It can be expressed as E(t)+dY(t)*L(t)). Therefore,
If a=b, the output of the low-pass filter 25 will be zero when Y(t) and PN(t) are synchronized, regardless of c, d, γ, δ, and ε. Further, when a=b and c=d, the output of the low-pass filter 25 becomes as shown in FIG. 2, and a straight line is formed between the points CD. In addition, a=b and c
For example, the output of the low-pass filter 25 when ≠d is shown in FIG.
The curve will be as shown by the broken line (provided that c>d), and the area between points CD' will be a quadratic curve.

As described above, the gain of the multiplier 11, the gain of the bandpass filter 14, the gain of the multiplier 12, the gain of the bandpass filter 15, the gain of the multiplier 22, and the gain of the low-pass filter 25 are all multiplied. In order to
As long as the product of these gains is constant, the size of each gain is unrelated to the synchronization tracking error, so there is no imbalance in the circuit gain due to errors in the components of each circuit or the influence of variations. is no longer a problem,
The error in synchronous tracking can be ignored. therefore,
Correct synchronous tracking is achieved regardless of errors or variations in the components of each circuit.

Note that the low-pass filter 25 for the phase difference between the input signal y(t) and the despreading PN code PN(t)
The output characteristic (phase comparison characteristic) of is equal to the phase comparison characteristic of the output of the subtractor 18 when the conventional envelope detectors 16 and 17 are square-law detectors.

[0019]

[Effects of the Invention] As explained above, according to the present invention, the first
Multiplier gain, first bandpass filter gain, second
The gain of the multiplier, the gain of the second bandpass filter, and the gain of the low-pass filter are all multiplied, so as long as the product of these gains is constant, the magnitude of each gain will be equal to the error in synchronous tracking. Because it has nothing to do with
Errors in synchronous tracking can be ignored, and there is an effect that synchronous tracking can be performed correctly regardless of errors or variations in the components of each circuit. Therefore, it can be used for distance measurement and other purposes to perform highly accurate synchronous tracking.

Furthermore, it is only required that the amplitude ratio of the early code component and the late code component in the output of the sum and difference between the early code and the late code be adjusted to be 1:1, respectively. This eliminates the need to adjust the gains of multipliers and bandpass filters, which were required in the synchronization tracking circuit of 2005, and fewer adjustment points are required, allowing the use of inexpensive components for the circuits that no longer require adjustment.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is an explanatory diagram of the operation of an embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of a conventional example.

FIG. 4 is an explanatory diagram of the operation of a conventional example.

FIG. 5 is an explanatory diagram of the operation of a conventional example.

[Explanation of symbols]

11, 12, 13, 22...multiplier 14, 15...Band pass filter 16, 17...Envelope detector 19...PN code generator 20...VCO 21...Loop filter 23...Subtractor 24...Adder 25...Low pass filter

Claims (1)

[Claims] Claim 1: A despreading PN code, an early code whose phase is ahead of the despreading PN code by a predetermined amount, and a late code whose phase is delayed by a predetermined amount from the despreading PN code, using the output of a voltage controlled oscillator as a clock. P that outputs three PN codes
an N code generator; an adder that adds the early code and the late code; a subtracter that subtracts the late code from the early code; a first multiplier that multiplies the input signal and the output signal of the adder; a second multiplier that multiplies the signal by the output signal of the subtracter; a first bandpass filter that receives the output signal of the first multiplier; and a second bandpass filter that receives the output signal of the second multiplier. a filter, a third multiplier that multiplies the output signal of the first band-pass filter and the output signal of the second band-pass filter, a low-pass filter that receives the output signal of the third multiplier, and a low-pass filter. It includes a loop filter that receives the output signal of the filter as an input, and a fourth multiplier that multiplies the despreading PN code and the input signal, and supplies the output signal of the loop filter as a control voltage to the voltage controlled oscillator to control the voltage. A synchronization tracking circuit characterized in that the phase of an output of an oscillator is tracked so as to be synchronized with the phase of a clock of a code series included in an input signal.