JPH04322526A - Synchronization tracing circuit - Google Patents

Abstract

PURPOSE:To attain accurate phase tracing even when a circuit constant of a component of each circuit is deviated or dispersed from an initial value due to a secular change or a temperature change. CONSTITUTION:The circuit is provided with a phase delay device 25 receiving selectively an output of a loop filter 21 and delaying a phase of an early code by a delay based on an output of the loop filter 21. Prior to the synchronization tracing, an output of a constant voltage power supply circuit 27 is applied to a VCO 20 as a control voltage. The early code subject to phase delay by the phase delay device 25 and an output sinusoidal wave of a sinusoidal wave generator 26 are multiplied by a multiplier 28. The output of the multiplier is fed to a delay lock loop, an output of the loop filter 21 is fed to the phase delay device 25 to set the phase delay of the code. The state is switched to the synchronization tracing state an input signal and the early code subject to phase delay by the phase delay device 25 is used for an inverse spread PN code to apply inverse spread to the input signal.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization tracking circuit having a delay locked loop.

0002

2. Description of the Related Art As shown in FIG. 2, a conventional synchronization tracking circuit uses the output of a voltage controlled oscillator (hereinafter referred to as VCO) 20 as a clock to generate a despreading PN code, and the phase is determined from the despreading PN code. It includes a PN code generator 19 that generates an early code that is advanced by a fixed amount and a late code whose phase is delayed by a predetermined amount from the despreading PN code, and a multiplier 11 that calculates the product of the input signal and the early code, and then multiplies the input signal and the early code. The output of the detector 11 is passed through a band pass filter 14 to an envelope detector 16.
A multiplier 12 calculates the product of the input signal and the rate code, and the output of the multiplier 12 is passed through a bandpass filter 15 and detected by an envelope detector 17 to obtain a first correlation output. Obtain two correlation outputs. The output of the envelope detector 17 is subtracted from the output of the envelope detector 16 by a subtracter 18 which is a composite correlation calculator to obtain an error signal, and the error signal is smoothed by a loop filter 21 to obtain a composite correlation output. The combined correlation output, that is, the output of the loop filter 21 is applied to the VCO 20 as a control signal to control the oscillation frequency so that the phase of the oscillation output of the VCO 20 is synchronized with the phase of the clock of the PN code series included in the input signal. The input signal and the despreading PN code are multiplied by the multiplier 13 to obtain a despread output.

In the synchronization tracking operation of the conventional synchronization tracking circuit described above, the input signal is y(t), and the despreading PN code is PN.
(t), the horizontal axis is the phase difference between the code sequence included in y(t) and PN(t), and the vertical axis is the output voltage of the subtracter 18, then the envelope detector The code sequence included in y(t) and PN(
The relationship between the phase difference with t) and the output voltage of the subtracter 18 at that time is as shown in FIG. If the outputs of the envelope detectors 16 and 17 are not turned off, the result will be as shown in FIG. 3(c). If the phase difference between the code sequence included in y(t) and PN(t) is between A and B in FIG. 3(c), the VCO 20 is controlled by negative feedback and the phase difference becomes near the S point. .

0004

However, according to the conventional synchronization tracking circuit described above, the multipliers 11 and 12, the bandpass filters 14 and 15, the envelope detectors 16 and 17, and the subtracter 1
For example, Figures 3 (a), (b), and (c) may be affected by factors such as the circuit constants of the components deviating from their initial values or varying due to aging or temperature changes. Figures 4(a), (b) and (c)
The level changes as shown in Figure 4(c) and Figure 3(
As is clear from comparing y(t) with PN(t), the phase difference between the code sequence included in y(t) and PN(t) is not zero and locks near point P, making accurate synchronization tracking impossible. There was a problem that it did not work.

[0005] The present invention is designed to prevent circuit constants of components constituting each circuit from deviating from their initial values or varying, resulting in a state in which the phase difference between the code sequence included in y(t) and PN(t) is not zero. It is an object of the present invention to provide a synchronization tracking circuit that generates a code sequence whose phase difference with the code sequence included in y(t) is zero even when locked.

[0006]

[Means for Solving the Problems] The synchronization tracking circuit of the present invention inputs the output of a voltage controlled oscillator as a clock, and generates two codes, an early code and a late code, which are equal to each other and have a predetermined phase difference from each other. P that generates a PN code
In a synchronization tracking circuit equipped with a delay locked loop having an N code generator, a voltage source, an oscillator with a predetermined oscillation frequency, and a composite correlation output are selectively supplied, and the phase of the early code is adjusted by a delay amount based on the composite correlation output. a phase delayer that delays the oscillator, a first multiplier that multiplies the output of the oscillator and the output of the phase delayer, and a delay lock loop that selects either the input signal or the output signal of the first multiplier. first selection means for supplying the output signal of the first multiplier as an input signal; The present invention is characterized by comprising a second selection means for supplying the signal, and a second multiplier for multiplying the output signal of the first selection means by the output of the phase delay device and outputting the result as a despread signal.

[0007]

In the synchronization tracking circuit of the present invention, the first selection means is switched to the output signal selection side of the first multiplier before synchronization tracking of the input signal. When the first selection means is switched to the output signal selection side of the first multiplier, the output of the voltage source is applied as a control voltage to the voltage controlled oscillator by the second selection means, and the oscillation frequency of the voltage controlled oscillator is changed. At the same time, the combined correlation output is supplied to the phase delay device, and the phase delay amount in the phase delay device is controlled so that the combined correlation output becomes zero, and when the combined correlation output becomes zero, the phase delay amount is Fixed. When synchronously tracking an input signal, the input signal is selected by the first selection means and supplied to the delay lock loop circuit, and the input signal is synchronized while being despread by the second multiplier using an early code whose phase is delayed by the phase delay device. be tracked. However, the amount of phase delay of the phase delay device is fixed so that the combined correlation output becomes zero according to the circuit state immediately before synchronization tracking, and the early code whose phase is delayed by this fixed amount of phase delay is used to 1 While despreading the input signal input through the selection means, the same synchronization tracking operation as before is performed, and the circuit constants of the components may change from their initial values due to aging or temperature changes of the circuit components. Even if there is a deviation or variation, accurate synchronized tracking will be performed regardless of the deviation or variation.

[0008]

[Examples] The present invention will be explained below with reference to Examples.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In this embodiment, the same components as those in the conventional example shown in FIG. 2 are denoted by the same reference numerals. The input signal and the output signal of the multiplier 28 (described later) are selectively transferred to the multiplier 11 via the changeover switch 22.
supply to. Reference numeral 29 is a PN code generator which receives the output of the VCO 20 as a clock and outputs two PN codes that are equal to each other and one of which is delayed in phase by a predetermined amount from the other. The one that is ahead in phase is referred to as an early code, and the one that is delayed in phase is referred to as a late code. The multiplier 11 multiplies the output signal from the changeover switch 22 and the early code output from the PN code generator 29,
The output of the multiplier 11 is passed through a bandpass filter 14 and detected by an envelope detector 16 to obtain a first correlation output. Multiplier 1
2, the output signal from the changeover switch 22 is multiplied by the rate code output from the PN code generator 29, and the output of the multiplier 12 is passed through the bandpass filter 15 and detected by the envelope detector 17 to produce a second correlation output. get. The output of the envelope detector 17 is subtracted from the output of the envelope detector 16 by a subtracter 18 which is a synthetic correlation calculator to obtain an error signal, and the error signal is smoothed by a loop filter 21 to obtain a synthetic correlation. get the output. The combined correlation output, that is, the output of the loop filter 21, is supplied as a control signal to the VCO 20 via changeover switches 23 and 24, which will be described later.

Here, multipliers 11 and 12, bandpass filters 14 and 15, envelope detectors 16 and 17, and subtractor 18
, loop filter 21, VCO 20, PN code generator 2
9 constitutes a delay lock loop. The control voltage output from the loop filter 21 is supplied to a changeover switch 24, and selectively supplied to the changeover switch 23 or the phase delay device 25 via the changeover switch 24. The phase delay amount of the phase delay device 25 is controlled by the control voltage output from the loop filter 21. The control voltage from the loop filter 21 supplied via the changeover switch 24 or the output voltage of the constant voltage power supply circuit 27 that outputs the control voltage is selectively switched to VC via the changeover switch 23.
Supply to O20. Here, the changeover switches 23 and 24 are switched in conjunction with the changeover switch 22, and when the changeover switch 22 is switched to select the input signal of the delay lock loop circuit, the control voltage from the loop filter 21 is changed. Supply to VCO20,
When the changeover switch 22 is switched to select the output signal from the multiplier 28, the control voltage from the loop filter 21 is supplied to the phase delay device 25, and the control voltage from the constant voltage power supply circuit 27 is supplied to the VCO 20. can be switched to supply.

The early code output from the PN code generator 29 is supplied to a phase delayer 25 to delay the phase.
The output from the phase delay device 25 is supplied to multipliers 13 and 28, and the multiplier 13 multiplies the output signal from the changeover switch 22 and the output signal from the phase delay device 25 to output a despread signal. Further, the oscillation output of the sine wave generator 26 and the output signal of the phase delay device 25 are supplied to a multiplier 28 for multiplication, and the multiplication output is supplied to the changeover switch 22.

In this embodiment configured as described above,
When performing normal synchronous tracking, the changeover switch 22 is switched to a state where input signals are applied to the multipliers 11 and 12, that is, contacts a-c of the changeover switch 22 are switched to the on state, and before reception starts, etc., the output of the multiplier 28 is The signal selection state, that is, the contacts b-c of the changeover switch 22 are switched to the on state. Contact b of changeover switch 22
-c is turned on, the contacts b-c of the changeover switches 23 and 24 are also turned on, and the early code output from the PN code generator 29 is phase-delayed by the phase delay device 25. The code (hereinafter referred to as variable code) is multiplied by the sine wave output from the sine wave generator 26, and the multiplied signal is supplied to the multipliers 11, 12, and 13 via the changeover switch 22.

On the other hand, in this state, the control voltage from the constant voltage power supply circuit 27 is being supplied to the VCO 20, and in response to the oscillation output of the VCO 20 at this time, the PN code generator 2
The early code and late code outputted from 9 and the output signal of multiplier 28 are multiplied by multipliers 11 and 12 separately, and the control voltage outputted from loop filter 21 becomes zero based on these multiplication outputs. The phase delay amount of the phase delay device 25 is controlled as follows, and the loop filter 21
The phase delay amount of the phase delay device 25 is fixed at the phase delay amount at which the control voltage output from the phase delay device 25 becomes zero.

[0014] Next, when performing normal synchronous tracking, the contacts a to c of the changeover switches 22, 23, and 24 are switched to the on state. By this switching, the input signal is passed through the changeover switch 22 to the multiplier 1.
1 , 12 and 13 , and a control voltage from the loop filter 21 is supplied to the VCO 20 . However, in this state, the phase delay amount of the phase delay device 25 is already fixed as described above so that the control voltage from the loop filter 21 becomes zero according to each circuit state immediately before synchronization tracking, and this fixed A synchronization tracking operation similar to the conventional one is performed while despreading the input signal supplied via the changeover switch 22 using a variable code in which the phase of the early code is delayed by the amount of phase delay.

[0015]

As described above, according to the present invention, the first selection means selects the output signal of the first multiplier and supplies it as an input signal to the delay lock loop before synchronous tracking of the input signal, and The selection means supplies the composite correlation output to the phase delay device, and applies the output of the voltage source to the voltage controlled oscillator as a control voltage to control the amount of phase delay in the phase delay device so that the composite correlation output becomes zero. When performing synchronous tracking of the input signal, the first selection means selects the input signal, supplies it to the delay lock loop, and performs synchronous tracking while despreading the input signal using the phase-delayed early code by the second multiplier. Therefore, even if errors occur during synchronized tracking of input signals due to the circuit constants of components deviating from their initial values or varying due to aging or temperature changes, synchronized tracking will still be possible. Regardless of its errors and variations before,
The phase delay amount of the phase delay device is fixed so that the combined correlation output becomes zero, and during reception, this error does not change rapidly, and the early code is phase-delayed with this fixed phase delay amount. , the synchronization tracking operation is performed while despreading the input signal inputted through the first selection means, and accurate synchronization tracking is performed regardless of the above-mentioned errors and variations in the components constituting each circuit. It has the effect of

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of a conventional example.

FIG. 3 is an explanatory diagram of the operation of the conventional example.

FIG. 4 is an explanatory diagram of the operation of the conventional example.

[Explanation of symbols]

11, 12, 13, 28...multiplier 14, 15...Band pass filter 16, 17...Envelope detector 18...Subtractor 19...PN code generator 20...VCO 21...Loop filter 22, 23, 24...Switch switch 25...Phase delay device 26...Sine wave generator 27... Constant voltage power supply circuit 29...PN code generator

Claims (1)

[Claims] 1. A delay comprising a PN code generator which receives the output of a voltage controlled oscillator as a clock and generates two PN codes, an early code and a late code, which are equal to each other and have a predetermined phase difference from each other. A synchronization tracking circuit with a lock loop includes a voltage source, an oscillator with a predetermined oscillation frequency, and a phase delayer to which a composite correlation output is selectively supplied and delays the phase of an early code by a delay amount based on the composite correlation output. , a first multiplier that multiplies the output of the oscillator and the output of the phase delayer, and a first multiplier that selects either the input signal or the output signal of the first multiplier and supplies it as an input signal to the delay-locked loop. selection means; and second selection means for supplying the combined correlation output to the phase delay device while the first selection means is selecting the output signal of the first multiplier, and supplying the output of the voltage source to the voltage controlled oscillator as a control voltage. and a second multiplier that multiplies the output signal of the first selection means and the output of the phase delayer and outputs the result as a despread signal.