JP2871655B1 - Symbol synchronization circuit - Google Patents

Abstract

Provided is a symbol synchronization circuit capable of performing symbol synchronization stably even in a multipath environment. SOLUTION: An OFDM signal 1 is delayed by one effective symbol by a delay unit 2, and a non-delayed OFDM signal 1 and a delayed OFDM signal are multiplied by a multiplier 3 to obtain a correlation coefficient between the two. The first and second holding circuits 6 and 7 successively hold the integration result, and the subtractor 8 calculates the difference between the two to obtain the timing. The oscillation frequency of the clock generation circuit 10 is controlled by the frequency control circuit 9 based on the timing error estimation value. The timing control circuit 5 controls the timing of the operation of the integration circuit 4 and the holding circuits 6 and 7 based on the clock signal obtained here, and obtains the symbol timing of the finally input OFDM signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an OFDM demodulator for demodulating an OFDM (orthogonal frequency division multiplex) signal, and more particularly to a symbol synchronization technique for identifying an effective symbol period.

[0002]

2. Description of the Related Art In recent years, in digital audio broadcasting for mobile objects and digital terrestrial television broadcasting, a transmission system using the OFDM technique has attracted attention.

[0003] This OFDM transmission system is a type of multi-carrier modulation system, in which transmission data is divided and assigned to a number of subcarriers orthogonal to each other with an effective symbol period length, and assigned to each subcarrier for each symbol. Modulation is performed on the amplitude and phase of subcarriers with transmission data to generate an OFDM signal, and the receiving apparatus demodulates the amplitude and phase of each subcarrier of the effective symbol period length to obtain the original transmission data. It was done.

[0004] This method has a characteristic that the period of a symbol can be lengthened by dividing transmission data into subcarriers and transmitting the divided data, so that it is hardly affected by delay waves such as multipath. Further, by providing a guard period between symbols, inter-symbol interference is prevented and resistance to delayed waves is improved. For example, the guard period precedes the effective symbol period in the symbol, and a signal obtained by copying the rear part of the effective symbol period in the guard period is transmitted. The signal transmitted in the guard period maintains the orthogonality of the subcarriers with respect to the delayed wave and plays a role in preventing interference between the subcarriers.

Here, in order to prevent the interference of the delayed waves as described above, it is necessary to accurately extract the symbol timing in the receiving apparatus. Conventionally, a method of extracting symbol timing by using the same signal transmitted in the guard period and the rear part of the effective symbol period has been described in Ph.J. Tou.
rtier, "Multicarrier modem for digital HDTV terres
trial broadcasting ", Signal Processing: Image Comm
un., Vol. 5, 1993, pp. 379-403 and JP-A-7-994.
No. 86 has proposed this. In the following,
FIG. 12 and FIG.
This will be described with reference to FIG.

FIG. 12 shows a block diagram of a conventional symbol synchronization circuit. In FIG. 12, an OFDM signal 101 is delayed by one effective symbol by a delay unit 102.
The undelayed OFDM signal 101 and the OFDM signal delayed by the delay unit 102 are supplied to the correlation circuit 103. The correlation circuit 103 includes a multiplier 104 and an integration circuit 105. The multiplier 104 obtains a correlation coefficient between the OFDM signal 101 that is not delayed and the OFDM signal that is delayed by the delay unit 102 by multiplying the OFDM signal 101 and the OFDM signal that is delayed by the delay unit 102. The integration circuit 105 integrates the correlation coefficient obtained by the multiplier 104 over a time width corresponding to the guard period length. The integration circuit 105 performs a so-called moving integration operation that sequentially performs an integration operation, and is generally configured as an LPF (low-pass filter). The output of the integration circuit 105 is output from the correlation circuit 103 as a correlation signal.

FIG. 13 shows signal waveforms of various parts during the operation of the symbol synchronization circuit. In FIG. 13, (a) is an OFDM signal 101 input to the symbol synchronization circuit, where one symbol is composed of a guard period and an effective symbol period, and a signal at the end of the effective symbol period is copied in the guard period. (B) schematically shows the time relationship between the symbols of the OFDM signal (a). (C) is OF
The DM signal (b) is delayed by the delay unit 102.
The hatched part in (d) shows the OFDM signal (b) and the delayed ODM signal.
2 shows a correlated portion of the FDM signal (c). (E) is a correlation signal output from the correlation circuit 103. The signal level increases in a correlated portion by the integration processing of the integration circuit 105, and reaches a maximum near a symbol boundary.

[0008] The timing control circuit 106
3 detects the peak of the correlation signal (FIG. 13 (e)) and generates a timing signal (FIG. 13 (f)) indicating the effective symbol period based on the time at which the peak was detected.
The timing control circuit 106 includes a flywheel timing control circuit. The clock control circuit 107 obtains and outputs a time error of the symbol timing signal generated by the timing control circuit 106 based on the peak time of the correlation signal output from the correlation circuit 103.

The time error signal obtained by the clock control circuit 107 is smoothed by an LPF (low-pass filter) 108 and then a D / A (digital / analog) conversion circuit 109
Is converted to an analog signal. The output signal of the D / A conversion circuit 109 is supplied to the clock oscillation circuit 110 to control the oscillation frequency. Here, the clock control circuit 107
The LPFs 108 and D are set so that the time error between the peak time of the correlation signal output from the correlation circuit 103 and the symbol timing signal generated by the timing control circuit 106 becomes zero.
The oscillation frequency of the clock oscillation circuit 110 is controlled via the / A conversion circuit 109.

As described above, the conventional symbol synchronizing circuit applies the timing generation circuit 10 to the input OFDM signal.
7 synchronizes the generated symbol timing signal.

[0011]

However, in the method of observing a peak as described above, the peak becomes ambiguous in a multipath environment, and abrupt change of peak points occurs in a multipath fading environment. There is a problem that the operation of the symbol synchronization circuit becomes unstable.

FIG. 14 shows a signal during operation of each section of the conventional symbol synchronization circuit when a delay wave due to multipath occurs. 14A shows a main wave of the OFDM signal, and FIG. 14B shows a multipath delayed wave of the OFDM signal. When a delayed wave occurs, the symbol synchronization circuit
The FDM signal is input in a state where the main wave (a) and the delayed wave (b) are added. (C) and (d) are OFDM
The main wave (a) and the delayed wave (b) of the signal are signals delayed by one effective symbol by the delay unit 102. Shaded portions (e) and (f) indicate portions where the main wave (a) and the delayed wave (b) of the OFDM signal are correlated with the signal delayed by the delay unit 102, respectively. (G) Correlation circuit 1
03 is a correlation signal output. The correlation signal (g) is the sum of the correlation signal for the main wave and the correlation signal for the delayed wave. (H) is a timing signal indicating an effective symbol period obtained based on the correlation signal (g).

When the main wave and the delayed wave are received with substantially equal power, the correlation signal (g) has a value close to the maximum value as shown in the figure, and the peak detection of the correlation signal (g) becomes ambiguous. The time error signal obtained by the clock control circuit 107 fluctuates. As a result, the operation of the symbol synchronization circuit becomes unstable, and the symbol timing signal output from the symbol synchronization circuit fluctuates as shown in (h).

Further, some integration operation is required to obtain the correlation signal, and it is necessary to continuously perform the integration operation to obtain the correlation signal in order to observe the peak of the correlation signal. Therefore, in the conventional example, a low-pass filter or the like is used for the integration circuit 105. In general, a low-pass filter is composed of a large number of delay units and adders, so that there is a problem that the circuit scale becomes large.

The present invention solves the above-mentioned problems, can stably perform symbol synchronization even in a multipath environment, and can realize an integration operation for obtaining a correlation value with a simple integration circuit. An object of the present invention is to provide a symbol synchronization circuit capable of reducing the overall circuit scale.

[0016]

In order to achieve the above object, a symbol synchronization circuit according to the present invention is configured as follows.

(1) Orthogonal frequency division multiplexing in which one symbol is formed of a guard period and an effective symbol period, and a part of the signal of the effective symbol period is copied in the guard period so that the symbol has periodicity. A symbol synchronization circuit that receives an OFDM signal as a signal and identifies the effective symbol period to extract the OFDM signal in the effective symbol period, wherein the delay unit delays the OFDM signal by the effective symbol period; Multiplication means for obtaining a correlation coefficient between the signal and the OFDM signal delayed by the delay means; integration means for integrating the correlation coefficient obtained by the multiplication means according to an integration timing signal;
And a first and second holding means for holding the correlation coefficients integrated by the integration means in accordance with the second timing signal, respectively, and a difference between the correlation coefficients held by the first and second holding means. Subtraction means for obtaining and outputting the same as a time error signal; frequency control means for generating a frequency control signal for controlling a clock frequency based on the time error signal; and a clock having a variable clock frequency based on the frequency control signal. Clock generating means for generating a signal; and timing signal generating means for outputting the integration timing signal, the first and second holding timing signals, and the symbol timing signal indicating the effective symbol period based on the clock signal. And the timing signal generating means outputs the correlation coefficient to the integrating means based on the integration timing signal. The integration is performed twice within a predetermined period within the symbol period, and the first holding timing signal causes the first holding circuit to hold the previous correlation coefficient integrated by the integration means. According to the timing signal, the second holding circuit holds the correlation coefficient after integration by the integration means.

(2) Orthogonal frequency division multiplexing in which one symbol is formed of a guard period and an effective symbol period, and a part of the signal of the effective symbol period is copied in the guard period so that the symbol has periodicity. A symbol synchronization circuit that receives an OFDM signal as a signal and identifies the effective symbol period to extract the OFDM signal in the effective symbol period, wherein the delay unit delays the OFDM signal by the effective symbol period; Multiplication means for obtaining a correlation coefficient between the signal and the OFDM signal delayed by the delay means; integration means for integrating the correlation coefficient obtained by the multiplication means according to an integration timing signal;
First and second maximum value holding means for holding the maximum value of the correlation coefficient integrated by the integration means according to the second period signal in each period, and the first and second maximum value holding means Subtraction means for calculating the difference between the maximum values of the correlation coefficients held in and outputting as a time error signal, and frequency control means for generating a frequency control signal for controlling a clock frequency based on the time error signal, Clock generating means for generating a clock signal having a variable clock frequency based on the frequency control signal; and symbol timing indicating the integration timing signal, first and second period signals, and the effective symbol period based on the clock signal. Timing signal generating means for outputting a signal, wherein the timing signal generating means is configured to output the signal by the integration timing signal. The correlation coefficient is repeatedly integrated a plurality of times within a symbol period for a fixed period, and the first and second maximum value holding circuits are alternately designated by the first and second period signals to designate the same comparison period. Then, the maximum value of the correlation coefficient integrated by the integration means within a specified period is held.

(3) In the configuration of (1) or (2), the timing signal generation means generates the integration timing signal so that the integration period of the integration means becomes the guard period length.

(4) In the configuration of (1), the timing signal generation means generates the integration timing signal so that the integration period of the integration means is half the symbol period length.

(5) In the configuration of (2), the timing signal generation means generates the integration timing signal so that the integration period of the integration means is half of the guard period length.

(6) The configuration according to (1), further comprising a synchronization state determining means for determining a synchronization state of the symbol timing signal with respect to the effective symbol period, wherein the timing signal generating means responds to the synchronization state of the clock signal. Thus, the integration period for the integration means is changed.

(7) In the configuration of (6), the timing signal generation means widens the integration period in the initial state of the synchronization pull-in, and enters the range where the synchronization state is allowed by the synchronization state determination means. The integration period is narrowed when it is determined that the time has elapsed.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS.

(First Embodiment) FIG. 1 shows a block configuration of a symbol synchronization circuit according to a first embodiment of the present invention, FIG. 2 shows a specific block configuration of an integration circuit according to the first embodiment, and FIG. 4 shows the signal waveform of each part during the operation of the symbol synchronization circuit in the embodiment, and FIG. 4 shows the time error signal characteristics obtained by the symbol synchronization circuit in the embodiment.

In FIG. 1, an OFDM signal 1 is a delay unit 2
Is delayed by one effective symbol. The undelayed OFDM signal 1 and the OFDM signal delayed by the delay unit 2 are supplied to a multiplier 3. The multiplier 3 obtains a correlation coefficient between the OFDM signal 1 that is not delayed and the OFDM signal that is delayed by the delay unit 2 by multiplying the OFDM signal 1 and the OFDM signal that is delayed by the delay unit 2. The integration circuit 4 integrates the correlation coefficient obtained by the multiplier 3 over a time width corresponding to the guard period length. The first holding circuit 6 and the second holding circuit 7 are the first and second holding circuits supplied from the timing control circuit 5, respectively.
The integration result of the integration circuit 4 is held at the input timing of the timing signal. The subtracter 8 subtracts the value held in the second holding circuit 7 from the value held in the first holding circuit 6, and outputs the result as a timing error estimated value.

The frequency control circuit 9 controls the oscillation frequency of the clock generation circuit 10 based on the estimated timing error output from the subtracter 8. The frequency control circuit 9 includes a smoothing filter, an amplifier, or an attenuator to suppress a sudden change, and its time constant determines the response characteristic of the frequency control loop.

FIG. 2 shows a specific configuration of the integration circuit 4. The correlation coefficient from the multiplier 3 is delayed by one sample by a delay circuit (D) 4b via an adder 4a, and is added to the adder 4a. To integrate the correlation coefficient.
The integration process is performed until the clear timing signal CLR is supplied from the timing control circuit 5 to the delay circuit 4b.

In FIG. 3, (a) is an OFDM signal 1 input to the symbol synchronization circuit according to the present embodiment, where one symbol is composed of a guard period and an effective symbol period, and the guard period is the latter of the effective symbol period. The signal is being duplicated. (B) schematically shows the time relationship between the symbols of the OFDM signal (a). (C) is a signal obtained by delaying the OFDM signal (b) by one effective symbol in the delay unit 2. The shaded area in (d) shows a correlated part of the OFDM signal (b) and the delayed OFDM signal (c).
(E) and (f) show the first and second integration periods in the integration circuit 4, respectively. (G), (h), and (i) show the clear timing signal C to the integration circuit 4 generated in the symbol synchronization state in the timing control circuit 5, respectively.
LR, a first holding timing signal to the first holding circuit 6, and a second holding timing signal to the second holding circuit 7. (G ′), (h ′), and (i ′) indicate that the timings of the first integration period (e) and the second integration period (f) in the timing control circuit 5 correspond to the time shown in FIG. A clear timing signal CLR to the integrator 4 generated when the reference position is delayed by an error τ, a first hold timing signal to the first hold circuit 6, and a second hold circuit 7
2 shows a second holding timing signal.

That is, the correlation coefficient integrated by the period integration circuit 4 shown in the integration period (e) is held in the first holding circuit 6 after the completion of the integration operation. The correlation coefficient integrated by the period integration circuit 4 shown in the integration period (f) becomes the second after the integration operation is completed.
Is held in the holding circuit 7.

In FIG. 4, (j) and (k) correspond to the first
When the timing of the integration period (e) and the second integration period (f) deviate from the time position shown in FIG. 2 by the error τ, the first holding circuit 6 and the second 5 shows the characteristics of the integration result of the integration circuit 4 held in the holding circuit 7 of FIG. (L) is a characteristic of the estimated timing error value obtained at the output of the subtracter 8 with respect to the timing error τ.

In this example, when the timing error τ is positive, a positive value is obtained as the timing error estimated value of the subtractor 8. Therefore, by increasing the oscillation frequency of the clock generation circuit 10 via the frequency control circuit 9 based on the output value of the subtracter 8, each timing signal generated by the timing control circuit 5 is advanced. Conversely, if the timing error is negative,
By lowering the oscillation frequency of the clock generation circuit 10,
Each timing signal generated by the timing control circuit 5 is delayed. As a result, the timing error τ gradually decreases, and finally, synchronization is achieved.

(M) and (n) show the first integration period (e) and the second integration period when a multipath delayed wave occurs.
When the timing of the integration period (f) is shifted by the error τ,
The characteristic of the integration result of the integration circuit 4 held in the first holding circuit 6 and the second holding circuit 7 with respect to the timing error τ is shown. (O) is a characteristic of the estimated timing error value obtained from the output of the subtracter 8 with respect to the timing error τ. As can be seen from (o), even when a delayed wave due to multipath occurs, the synchronization point of the symbol synchronization circuit (the point at which the estimated timing error value becomes 0) becomes one point, and stable symbol synchronization can be performed. it can.

As described above, according to the configuration of this embodiment, even when a multipath delayed wave is generated, the timing signal generated by the timing control circuit 5 is stably synchronized with the input OFDM signal 1. As a result, an accurate symbol synchronization signal 11 can be obtained from the timing control circuit 5. Further, since the correlation integration is performed intermittently, the correlation integration can be realized with a simple integration circuit, thereby reducing the overall circuit scale.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. However, the configuration of the symbol synchronization circuit of the present embodiment is basically the same as that of the first embodiment shown in FIG. 1, so that the description thereof will be omitted, and only the differences from the first embodiment in operation will be described. I do. Further, since the integration circuit 4 has the same configuration as that shown in FIG. 2, its description is omitted here.

The present embodiment differs from the first embodiment in that the period during which the integration circuit 4 performs the integration operation is half the symbol period length. FIG. 5 shows signal waveforms of various parts during operation of the symbol synchronization circuit of the present embodiment. (A) to (d) are the same as those of the first embodiment shown in FIG. In the present embodiment, the first and second integration periods during which the integration circuit 4 performs the integration operation are shown in FIG.
And (f). (G), (h) and (i) respectively show a clear timing signal CLR to the integrator 4 generated by the timing control circuit 5, a first hold timing signal to the first hold circuit 6, and a second hold. Second to circuit 7
5 shows the holding timing signal of the first embodiment.

In FIG. 6, (j) and (k) represent the first
When the integration period (e) and the second integration period (f) deviate from the reference position in time shown in FIG. 5 by the error τ, the first holding circuit 6 and the second 2 is a characteristic of an integration result of the integration circuit 4 held by the holding circuit 7 of FIG. (L) is a characteristic of the estimated timing error value obtained at the output of the subtracter 8 with respect to the timing error τ.

In this embodiment, as in the first embodiment, the oscillation frequency of the clock generation circuit 10 is controlled via the frequency control circuit 9 on the basis of the output value of the subtracter 8 to achieve timing synchronization. Here, in the present embodiment, the timing error estimation value is obtained with a wider range of timing error τ than in the first embodiment.

As described above, according to the configuration of the present embodiment, symbol synchronization can be drawn in a wide range of timing error τ. Also, in this configuration,
Since the correlation integration is performed intermittently, it can be realized with a simple integration circuit, and the overall circuit scale can be reduced.

(Third Embodiment) Next, FIGS.
A third embodiment of the present invention will be described with reference to FIG.

FIG. 7 shows a block configuration of the symbol synchronization circuit of this embodiment. 7, the same components as those of the symbol synchronization circuit according to the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. Further, since the integration circuit 4 has the same configuration as that shown in FIG. 2, its description is omitted here.

This embodiment is different from the first embodiment in that the first and second holding circuits 6 and 7 in FIG. 1 are respectively the first and second maximum value holding circuits 26 and 27 shown in FIG. And the timing control circuit 5
And that the first and second timing signals applied to the second maximum value holding circuits 26 and 27 are changed to period signals indicating periods. The integration circuit 4 performs integration of a time width corresponding to a half period of the guard period length, and outputs an integration result for each period. The first and second maximum value holding circuits 26 and 27 perform the predetermined period according to the first and second period signals based on the clear timing signal CLR, the clock signal CK, and the holding timing signal L provided from the timing control circuit 5, respectively. The maximum value of the integration result output by the integration circuit 4 is held.

FIG. 8 shows a specific configuration of the first maximum value holding circuit 26. The integration result of the correlation coefficient from the integration circuit 4 is obtained from one input terminal of the comparator 26a and the selector (S).
EL) 26b. Comparator 26
The previous maximum value obtained by the D latch circuit 26c is supplied to the other input terminal of the input terminal a and the other input terminal of the selector 26b. The selector 26b selects the larger one of the two inputs based on the comparison result of the comparator 26a. The signal selected here is supplied to the D latch circuit 26c and the holding circuit 26d. The D latch circuit 26c takes in the output of the selector 26c every time the clock signal CK is input from the timing control circuit 5. Then, when the clear timing signal CLR is given from the timing control circuit 5, the value fetched is cleared. The holding circuit 26d holds the selector output at the time when the holding timing signal L from the timing control circuit 5 is given. This configuration is the same for the second maximum value holding circuit 27. Therefore, the specific configuration is omitted.

FIG. 9 shows signal waveforms of various parts during operation of the symbol synchronization circuit of the present embodiment. 9A to 9D show (a) in FIG. 3 described in the first embodiment.
To (d), and the description is omitted. (E) and (f) are periods in which the integration circuit 4 performs integration, respectively. In the example of this embodiment, integration is performed five times for each symbol. The maximum value of the five correlation values obtained by integration in the integration period of (e) is held in the first maximum value holding circuit 26, and the five maximum values obtained by integration in the integration period of (f) are obtained. The maximum value of the correlation values is the second maximum value holding circuit 2
7 is held.

(G) is a clear timing signal CLR to the integration circuit 4, (h) is a clock signal CK supplied to each of the maximum value holding circuits 26 and 27, and (i) is to the first maximum value holding circuit 26. Of the clear timing signal CLR, (j) is the hold timing signal L,
(K) shows the clear timing signal CLR to the second maximum value holding circuit 27, and (l) shows the holding timing signal L to the second maximum value holding circuit 27. Thereby, the first
The maximum value of each integration period shown in (e) and (f) is obtained in the maximum value holding circuit 26 and the second maximum value holding circuit 27, respectively.

In FIG. 10, (m) and (n) indicate the timing error τ when the integration period (e) and the integration period (f) deviate from the reference position in time shown in FIG. For the maximum value holding circuits 26 and 2 respectively.
7 shows the characteristics of the integration result of the integration circuit 4 held in the memory 7.
(O) is a characteristic of the estimated timing error value obtained from the output of the subtracter 8 with respect to the timing error τ.

As is clear from FIGS. 9 and 10, in the present embodiment, the oscillation of the clock generation circuit 10 via the frequency control circuit 9 based on the output value of the subtractor 8 as in the first embodiment. Synchronize the timing by controlling the frequency.
Here, in the present embodiment, the timing error estimation value is obtained with a wider range of timing error τ than in the first embodiment. Further, in the second embodiment, integration is performed including a part having no correlation. In contrast, in the present embodiment, since each integration range is half of the guard period, the stability of the integration operation is increased.

As described above, in the present embodiment, symbol synchronization can be more stably drawn in with respect to a wide range of timing error τ. Also, in this configuration,
Since the correlation integration is performed intermittently, it can be realized with a simple integration circuit, and the overall circuit scale can be reduced.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIG. However, in FIG. 11, the same components as those in the symbol synchronization circuits of the first and second embodiments described in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. The configuration of the integration circuit 4 is also omitted for the same reason.

FIG. 11 shows a block configuration of the symbol synchronization circuit of this embodiment. The present embodiment is different from the first and second embodiments described with reference to FIG. 1 in that the synchronization state is determined from the output of the subtracter 8 and the timing signal of the timing control circuit 5 is determined according to the determination result. The point is that a synchronization state determination circuit 31 for switching the generation timing is provided. In this case, the timing control circuit 5 has a function of setting the integration operation period as the guard period length as shown in (e) and (f) of FIG. 3, and a symbol period as shown in (e) and (f) of FIG. It has a function of reducing the length by half, and operates according to one of the functions according to the determination result of the synchronization state determination circuit 31.

That is, the first embodiment is characterized in that the drawing width is narrow but the precision is high. In the second embodiment, although extra integration is performed, stability is lacking, but a wide range of pull-in is possible. Therefore, in the present embodiment, the first and second embodiments are combined, and the synchronization pull-in process is performed at the start of the synchronization pull-in by setting the integration operation period to half the symbol period length, as in the second embodiment.
When synchronization is established, switching is performed to perform synchronization pull-in processing with the integration operation period as the guard period length, as in the first embodiment.

Therefore, according to the present embodiment, the synchronization pull-in can be realized in a short time and with high accuracy.
Also in this configuration, since the correlation integration is performed intermittently, it can be realized with a simple integration circuit, and the overall circuit scale can be reduced.

[0053]

As described above, according to the present invention, a symbol synchronization is obtained in two periods, and a timing error estimation value is obtained from a difference between the correlation values. It can be performed.

Further, the integration operation for obtaining the correlation value can be performed intermittently, so that the integration circuit can be simplified and the circuit size of the symbol synchronization circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a configuration of a symbol synchronization circuit according to a first embodiment of the present invention.

FIG. 2 is a block circuit diagram showing a specific configuration of an integration circuit according to the first embodiment.

FIG. 3 is a timing waveform chart showing signal waveforms of respective units during operation of the symbol synchronization circuit according to the first embodiment.

FIG. 4 is a waveform chart showing a time error signal characteristic obtained by the symbol synchronization circuit according to the first embodiment.

FIG. 5 is a timing waveform chart showing signal waveforms of respective units during operation of the symbol synchronization circuit according to the second embodiment of the present invention.

FIG. 6 is a waveform chart showing a time error signal characteristic obtained by the symbol synchronization circuit according to the second embodiment.

FIG. 7 is a block circuit diagram showing a configuration of a symbol synchronization circuit according to a third embodiment of the present invention.

FIG. 8 is a block circuit diagram showing a specific configuration of a maximum value holding circuit according to a third embodiment.

FIG. 9 is a timing waveform chart showing signal waveforms of various units during operation of the symbol synchronization circuit according to the third embodiment.

FIG. 10 is a waveform chart showing a time error signal characteristic according to the third embodiment.

FIG. 11 is a block circuit diagram showing a configuration of a symbol synchronization circuit according to a fourth embodiment of the present invention.

FIG. 12 is a block circuit diagram showing a configuration of a conventional symbol synchronization circuit.

FIG. 13 is a timing waveform chart showing signal waveforms of various parts during operation of the symbol synchronization circuit shown in FIG. 12;

FIG. 14 is a diagram showing a symbol synchronization circuit shown in FIG.
FIG. 6 is a timing waveform chart showing signal waveforms during operation of each unit when a delay wave is generated due to a value path to be extended.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... OFDM signal 2 ... Delay device 3 ... Multiplier 4 ... Integration circuit 4a ... Adder 4b ... Delay circuit 5 ... Timing control circuit 6 ... First holding circuit 7 ... Second holding circuit 8 ... Subtractor 9 ... Frequency Control circuit 10 Clock generation circuit 11 Symbol timing signal 26 First first value holding circuit 26a Comparator 26b Selector 26c D latch circuit 26d Holding circuit 27 Second maximum value holding circuit 31 Synchronous state Judgment circuit 101 OFDM signal 102 Delay device 103 Correlation circuit 104 Multiplier 105 Integration circuit 106 Timing control circuit 107 Clock control circuit 108 Low-pass filter 109 Digital / analog conversion circuit 110 Clock generation circuit

Continued on the front page (72) Inventor Kenichiro Hayashi 5-2-2-8 Akasaka, Minato-ku, Tokyo Inside the Next Generation Digital Television Broadcasting System Research Laboratories (72) Inventor Sadaji Kageyama 5-chome Akasaka, Minato-ku, Tokyo No. 2-8 Inside the Next Generation Digital Television Broadcasting System Laboratory (72) Inventor Akira Kisoda 5-2-8 Akasaka Minato-ku, Tokyo Inside the Next Generation Digital Television Broadcasting System Laboratory ( 72) Inventor Shigeru Soga 5-2-8, Akasaka, Minato-ku, Tokyo Inside the Next Generation Digital Television Broadcasting System Research Laboratories (72) Inventor Jin Mori 1006 Kazuma Kazuma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. In-house (56) References JP-A-7-143097 (JP, A) JP-A-7-99486 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04J 11/00

Claims (7)

(57) [Claims] 1. An orthogonal frequency division multiplexed signal in which one symbol is formed of a guard period and an effective symbol period, and a part of the signal of the effective symbol period is copied in the guard period so as to have periodicity within the symbol. A symbol synchronizing circuit for receiving the OFDM signal as input and identifying the effective symbol period in order to extract the OFDM signal in the effective symbol period, comprising: a delay unit for delaying the OFDM signal by the effective symbol period; O delayed by the delay means
Multiplication means for obtaining a correlation coefficient with the FDM signal; integration means for integrating the correlation coefficient obtained by the multiplication means according to an integration timing signal; and integration by the integration means according to first and second timing signals. First and second holding means for respectively holding a correlation coefficient; subtraction means for obtaining a difference between the correlation coefficients held by the first and second holding means and outputting the difference as a time error signal; Frequency control means for generating a frequency control signal for controlling the clock frequency based on the error signal; clock generation means for generating a clock signal having a variable clock frequency based on the frequency control signal; and The integration timing signal,
Timing signal generating means for outputting the first and second holding timing signals and a symbol timing signal indicating the effective symbol period, wherein the timing signal generating means sends the phase to the integrating means based on the integration timing signal. The relation number is integrated twice within a symbol period at regular intervals, and the first holding timing signal causes the first holding circuit to hold the previous correlation coefficient integrated by the integration means. 2. A symbol synchronization circuit wherein the second holding circuit holds the correlation coefficient integrated by the integration means in accordance with the holding timing signal of No. 2. 2. An orthogonal frequency division multiplexed signal in which one symbol is formed of a guard period and an effective symbol period, and a part of the signal of the effective symbol period is copied in the guard period so that the symbol has periodicity. A symbol synchronizing circuit for receiving the OFDM signal as input and identifying the effective symbol period in order to extract the OFDM signal in the effective symbol period, comprising: a delay unit for delaying the OFDM signal by the effective symbol period; O delayed by the delay means
Multiplication means for obtaining a correlation coefficient with an FDM signal; integration means for integrating the correlation coefficient obtained by the multiplication means according to an integration timing signal; and integration by the integration means according to first and second period signals The first that holds the maximum value of each period of the correlation coefficient
And a second maximum value holding unit; a subtraction unit that obtains a difference between the maximum values of the correlation coefficients held by the first and second maximum value holding units and outputs the difference as a time error signal; A frequency control unit that generates a frequency control signal for controlling a clock frequency based on: a clock generation unit that generates a clock signal having a variable clock frequency based on the frequency control signal; and Integration timing signal,
Timing signal generating means for outputting first and second period signals and a symbol timing signal indicating the effective symbol period, wherein the timing signal generating means transmits the correlation coefficient to the integrating means based on the integration timing signal. Is integrated a plurality of times repeatedly within a symbol period for a fixed period, and the first and second maximum value holding circuits are alternately designated by the first and second period signals to designate the same comparison period, and designated. A symbol synchronization circuit wherein a maximum value of a correlation coefficient integrated by the integration means during a period is held. 3. The symbol synchronization according to claim 1, wherein said timing signal generation means generates an integration timing signal such that an integration period of said integration means becomes said guard period length. circuit. 4. The symbol synchronization according to claim 1, wherein said timing signal generation means generates an integration timing signal such that an integration period of said integration means is half of said symbol period length. circuit. 5. The symbol synchronization according to claim 2, wherein said timing signal generation means generates an integration timing signal such that an integration period of said integration means is half of said guard period length. circuit. 6. A synchronizing state determining unit for determining a synchronizing state of a symbol timing signal with respect to the effective symbol period, wherein the timing signal generating unit sets an integration period for the integrating unit in accordance with a synchronizing state of the clock signal. 2. The symbol synchronization circuit according to claim 1, wherein the symbol synchronization is changed. 7. The timing signal generating means widens the integration period in an initial state of synchronization pull-in, and when the synchronization state determination means determines that the synchronization state is within an allowable range, the timing signal generation means performs the integration period. 7. The symbol synchronization circuit according to claim 6, wherein is narrowed.