JPH09219692A - Orthogonal frequency division multiplex transmission system and modulator and demodulator therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the influence due to a multipath interference, etc., by coping with frequency errors of ±fsc/2 (fsc is sub-carrier wave frequency space). SOLUTION: Data S13 for a general symbol is generated by making a first digital data series S11 correspond to a prescribed sub-carrier wave by a first frequency arrangement circuit 11. Data S14 for pilot symbol is generated by making a second digital data series S12 correspond to partial sub-carrier waves arranging at prescribed space of sub-carrier waves by a second digital data series S12. Transmission data S15 is generated by switching both of the data S13 and S14 in a prescribed period by using a switch 13. A valid symbol period signal S16 is generated by performing a Fourier inverse transform in a Fourier inverse transform circuit 14. By a guard period addition circuit 15, the part of the valid symbol period signals S16 are added as guard period signals to the valid symbol period signal and the valid symbol signal is outputted as an orthogonal frequency division multiplex signal S17.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an orthogonal frequency division multiplex transmission system and a modulation device and a demodulation device thereof, and more particularly to a carrier frequency synchronization technique on the demodulation side.

[0002]

2. Description of the Related Art In recent years, in digital audio broadcasting for mobiles and terrestrial digital television broadcasting, orthogonal frequency division multiplexing (hereinafter referred to as OFDM (Orthogonal Frequent
cy Division Multiplex)) Transmission system is attracting attention.

This OFDM transmission system is a system in which a large number of subcarriers (hereinafter, subcarriers) orthogonal to each other are modulated by digital data to be transmitted, and these modulated waves are multiplexed and transmitted. This system has a feature that when the number of subcarriers to be used increases to several hundreds to several thousands, the symbol period of each modulated wave becomes extremely long, so that it is hardly affected by multipath interference.

Hereinafter, the principle of the OFDM transmission system will be described.
This will be described with reference to FIGS. 18 and 19.

FIG. 18 is a block circuit diagram showing the principle configuration of the OFDM transmission system, and FIG. 19 is a baseband O
It is a figure which shows the time-axis waveform of an FDM signal. Note that, in FIG. 18, the thick line arrow represents a complex number signal, and the thin line arrow represents a real number signal. The transmission data S61 is digital data arranged on the complex plane.

First, the OFDM modulator 161 on the transmitting side
Is an inverse Fourier transform circuit 171, a guard period adding circuit 1
72, quadrature modulation circuit 173 and up converter 174
It consists of.

The inverse Fourier transform circuit 171 regards the transmission data S61 for one symbol as a signal in the frequency domain, and performs inverse Fourier transform to obtain the effective symbol period signal S.
71 is generated.

The guard period adding circuit 172 includes a rear portion of the effective symbol period signal (19 in FIG. 19) for each symbol.
2) is copied and the guard period signal (19 in FIG.
3) as an effective symbol period signal (19 in FIG. 19).
By adding before 1), an OFDM signal S72 in the base band (hereinafter, base band) is generated.

The quadrature modulation circuit 173 is a baseband OF.
Two carrier waves (hereinafter, carriers) that are orthogonal to each other are modulated by the real part and the imaginary part of the DM signal S72, and then added together to form an intermediate frequency (hereinafter, IF (Intermediate).
Frequency)) frequency conversion to the band signal S73. The up converter 174 converts the IF band signal S73 into a radio frequency (hereinafter, RF (Radio Frequency)) band signal S6.
Frequency converted to 2 and output.

The OFDM signal S62 in the RF band output from the OFDM modulator 161 is sent to the OFDM receiver 163 through a transmission line 162 such as a terrestrial wave, a satellite line, or a cable.

The OFDM demodulation device 163 includes a tuner 181, a quadrature demodulation circuit 182, and a guard period removal circuit 18.
3 and a Fourier transform circuit 184.

The tuner 181 converts the RF band signal S63 received via the transmission line 162 into the IF band signal S81.
Convert frequency to. The quadrature demodulation circuit 182 demodulates the IF band signal S81 into a baseband OFDM signal S82 using two carriers that are orthogonal to each other.

The guard period removing circuit 183 removes the guard period added on the transmitting side from the baseband OFDM signal S82 and extracts the effective symbol period signal S83. The Fourier transform circuit 184 regards the effective symbol period signal S83 as a signal in the time domain, and outputs the Fourier transformed signal as received data S64.

Here, for example, the frequency of the carrier used in the orthogonal demodulation circuit 182 in the OFDM demodulation device 163 and O
If there is an error with the frequency of the carrier used in the quadrature modulation circuit 173 in the FDM modulator 161, the data cannot be demodulated accurately.

Therefore, conventionally, various methods have been proposed for accurately synchronizing the frequency of the carrier on the receiving side, which is disclosed, for example, in Japanese Patent Laid-Open No. 7-143097. The configuration and operation of the conventional OFDM demodulator will be described below with reference to FIGS. 20 to 22.

FIG. 20 is a block circuit diagram showing the structure of a conventional OFDM demodulator. In FIG. 20, the thick line arrow represents a complex number signal, and the thin line arrow represents a real number signal.

In FIG. 20, the quadrature demodulation circuit 21 has a frequency control signal S27 output from the frequency control circuit 25.
2 carriers that are orthogonal to each other are generated based on, and the IF band signal S21 frequency-converted by a tuner (not shown) is demodulated into a baseband OFDM signal S22 using these carriers.

The guard period removing circuit 22 removes the guard period added on the transmitting side from the baseband OFDM signal S22 based on the timing signal S51 output from the synchronous reproducing circuit 141, and the effective symbol period signal S2.
3 is extracted. The Fourier transform circuit 23 regards the effective symbol period signal S23 as a signal in the time domain, and outputs the Fourier-transformed signal as received data S24.

On the other hand, the synchronous reproduction circuit 141 utilizes the fact that the guard period signal of the baseband OFDM signal S22 is a copy of the signal at the rear of the effective symbol period signal, and thus the timing signal S51 and the frequency error signal S5 are used.
Generate 2. The frequency control circuit 25 generates the frequency control signal S27 from the frequency error signal S52.

Hereinafter, the synchronous reproduction circuit 141 shown in FIG.
Will be described. Here, the subcarrier frequency interval is represented by fsc, the effective symbol period is represented by Ts, and the frequency error is represented by Δf. At this time, fsc = 1 / Ts
There is a relationship.

In the synchronous reproduction circuit 141, the delay circuit 2
01 delays the baseband OFDM signal S22 by Ts. The correlation circuit 202 calculates the correlation signal S92 of the baseband OFDM signal S22 and the delayed baseband OFDM signal S91. As a method of calculating the correlation signal S92, it is possible to take a moving average after multiplying by the complex conjugate signal.

The timing detection circuit 203 uses the correlation signal S
Timing signals S51 and S93 are generated by detecting the peak of the amplitude of 92. Frequency error detection circuit 2
04 generates the frequency error signal S52 by calculating the phase angle of the correlation signal S92 at the symbol boundary based on the timing signal S93.

21 (a), (b), (c), and (d) show the baseband OFDM signal S22, the delayed baseband OFDM signal S91, and the correlation signal S92 when Δf = 0, Δf = fsc, respectively. The correlation signal S92 in the case of / 4 is shown.

When Δf = 0, a signal at the rear of the effective symbol period signal (for example, G1 'in FIG. 21 (a)),
Since the signal is exactly the same as the guard period signal (for example, G1 in FIG. 21A), the real part of the correlation signal S92 has a positive peak value at the symbol boundary, and the imaginary part is almost zero.

When Δf ≠ 0, the signal at the rear of the effective symbol period signal (eg, G1 'in FIG. 21A) and
A phase difference of −2πΔf × Ts occurs with the guard period signal (for example, G1 in FIG. 21A). Therefore, when Δf = fsc / 4, the phase difference is −π / 2, the real part of the correlation signal S92 is almost 0, and the imaginary part has a negative peak value at the symbol boundary.

As is clear from the above description, the symbol boundary can be detected by detecting the amplitude peak of the correlation signal S92, and the phase angle of the correlation signal S92 at the symbol boundary can be calculated. , The frequency error Δf can be obtained.

[0027]

By the way, the conventional OF disclosed in the above-mentioned Japanese Patent Laid-Open No. 7-143097.
In the DM demodulator, the frequency error Δf and the frequency error signal S
The relationship with 52 is as shown in FIG. As is clear from this figure, the frequency error signal S52 has a periodicity of the subcarrier frequency interval fsc with respect to the frequency error Δf. Therefore, the above-described method can handle only a frequency error of ± fsc / 2 or less.

Further, the conventional O disclosed in the above publication is used.
In the FDM demodulator, by analyzing the power of each subcarrier signal from the output of the Fourier transform circuit 23,
A frequency error of fsc / 2 or more is calculated. But,
With such a method, it is impossible to accurately calculate the frequency error when the reception frequency characteristic is distorted due to the influence of multipath interference or the like.

Therefore, the present invention solves the above problems by
Provided are an OFDM transmission system that can cope with a frequency error of fsc / 2 or more, and can operate stably even when the reception frequency characteristic is distorted due to the influence of multipath interference and the like, and a modulator and a demodulator thereof. The purpose is to do.

[0030]

In order to solve the above-mentioned problems, the OFDM transmission system according to the present invention modulates and multiplexes a plurality of subcarriers orthogonal to each other in a first digital data sequence to generate a general symbol. In the second digital data sequence, to generate a pilot symbol by modulating and multiplexing some of the sub-carriers forming the general symbol arranged at a predetermined interval
The general symbol and the pilot symbol are switched and transmitted at a predetermined cycle.

According to the above-mentioned OFDM transmission method, on the transmitting side, some of the sub-carriers forming a general symbol, which are arranged at a predetermined interval, are grouped, modulated and multiplexed, and pilot symbols are periodically inserted. Therefore, by utilizing the periodicity of pilot symbols on the receiving side, ± fsc
Carrier frequency synchronization corresponding to a frequency error of / 2 (fsc is a subcarrier frequency interval) or more can be obtained.

Here, in the above OFDM transmission system,
It is characterized in that a set of subcarriers forming the pilot symbol is changed with time. Specifically, the sub-carrier sets are shifted in frequency order or in a specific pattern order. This makes it possible to make pilot symbols less susceptible to the effects of multipath interference and the like.

Further, the OFDM modulator according to the present invention includes a first frequency allocation circuit for outputting the first digital data sequence as data for a general symbol in association with a predetermined subcarrier, and a second digital data. A second frequency allocation circuit that outputs a series of data corresponding to a part of the subcarriers arranged at a predetermined interval as pilot symbol data, and outputs from the first and second frequency allocation circuits. The switch circuit for switching the general symbol data and the pilot symbol data at a predetermined cycle and outputting them as transmission data, and the transmission data output from this switch circuit is regarded as a frequency domain signal, and the Fourier inverse The inverse Fourier transform circuit that performs the transformation and the output of this inverse Fourier transform circuit are the baseband orthogonal frequency division multiplexed signals. To enter comprises a quadrature modulation circuit for quadrature modulation using two carriers orthogonal to each other.

According to the OFDM modulator having the above-mentioned configuration, by performing the switching control of the switch, the pilot symbol is inserted at an arbitrary cycle along with the transmission of the general symbol, converted into the orthogonal frequency division multiplex signal and transmitted. Will be able to.

Here, in the above OFDM modulator,
An arrangement control circuit is provided for the second frequency arrangement circuit, the arrangement control circuit changing a set of subcarriers corresponding to the second digital data with time. By this means, the set of subcarriers forming the pilot symbol can be changed with time. Specifically, the set of subcarriers can be shifted in frequency order or in a particular pattern order. In the above OFDM modulator, the output of the inverse Fourier transform circuit may be input as an effective symbol period signal, and a part of it may be copied and added as a guard period signal to the effective symbol period signal.

Further, in the OFDM demodulator according to the present invention, a plurality of subcarriers orthogonal to each other are modulated and multiplexed in the first digital data sequence as a general symbol, and the general symbol is formed in the second digital data sequence. Among the subcarriers, a part of the subcarriers arranged at a predetermined interval is modulated and multiplexed as a pilot symbol, and the general symbol and the pilot symbol are switched at a predetermined cycle to generate transmission data. A demodulation device for demodulating an orthogonal frequency division multiplex signal conforming to an orthogonal frequency division multiplex transmission system for orthogonally modulating and transmitting this transmission data using two carriers orthogonal to each other, wherein the orthogonal frequency division multiplex signal is An orthogonal demodulation circuit that demodulates into a baseband signal using two carriers that are orthogonal to each other,
A Fourier transform circuit that performs a Fourier transform on the demodulated signal of the quadrature demodulation circuit to demodulate the data in the frequency domain, and a demodulated signal of the quadrature demodulation circuit for a time determined by the effective symbol period and the interval between subcarriers forming the pilot symbol. A delay circuit for delaying only the above, a correlation circuit for calculating a correlation signal between the demodulation signal of the quadrature demodulation circuit and the demodulation signal delayed by the delay circuit, and the quadrature demodulation by obtaining the phase angle of the output signal of the correlation circuit. A frequency error detection circuit for detecting a frequency error of a carrier wave in the circuit, and a phase angle component depending on the frequency of a set of subcarriers forming the pilot symbol is removed from an output signal of the frequency error detection circuit, and a transmitter side and a receiver side And a correction circuit for extracting only the phase angle component depending on the deviation of the carrier frequency from the side.

According to the OFDM demodulator having the above structure, the periodicity of the pilot symbols generated on the transmission side is used, the phase angle component depending on the frequency of the set of subcarriers forming the pilot symbols is taken into consideration, and the frequency The error is detected and the carrier frequency is controlled.

In particular, the delay circuit has a delay time represented by Ts / Np, where Ts is an effective symbol period of an input signal and Np is an interval between subcarriers forming a pilot symbol. This gives ± f
Carrier frequency synchronization corresponding to a frequency error of sc / 2 or more can be obtained.

The correlation circuit outputs a complex conjugate signal of the complex number signal output from the delay circuit, and a complex multiplication that multiplies the complex number signal output from the quadrature demodulation circuit by the complex conjugate signal. And a moving average circuit for obtaining a moving average of the multiplication result of the complex multiplier and outputting the moving average as a correlation signal.

Further, when the set of subcarriers of pilot symbols in the orthogonal frequency division multiplexed signal changes in frequency order with time, the correction circuit detects the number of changes of the set of subcarriers forming the pilot symbol. Then, the phase angle component is removed based on the detection result.

Alternatively, when the set of subcarriers of pilot symbols in the orthogonal frequency division multiplexed signal changes in a specific pattern order with time, the correction circuit
It is characterized in that a pattern change of a set of subcarriers forming the pilot symbol is detected, and the phase angle component is removed based on the detection result.

Further, a frequency control circuit for controlling the carrier frequency of the quadrature demodulation circuit based on the correction output of the correction circuit is provided.

Further, a rounding circuit for rounding the correction output of the correction circuit is provided, and the Fourier transform circuit selectively controls the subcarrier to be converted based on the correction output of the rounding circuit.

Further, when a guard period signal is added to the orthogonal frequency division multiplexed signal, a timing detection circuit for detecting the symbol timing of the demodulated signal from the output signal of the correlation circuit, and the symbol timing detected by this circuit. The guard period removing circuit removes the guard period signal from the demodulated signal based on the above, extracts the effective symbol period signal, and outputs the effective symbol period signal to the Fourier transform circuit.

[0045]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to FIGS. 1 to 17. Here, the subcarrier frequency interval is fsc and the effective symbol period is Tsc.
Let s be the frequency error and Δf be the frequency error. Also, in the following, general control signals such as clocks necessary for the operation of each component are
The explanation is omitted so as not to be complicated.

(First Embodiment) FIG. 1 shows a first embodiment of the present invention.
3 is a block circuit diagram showing the configuration of the OFDM modulation device in the embodiment of FIG. It should be noted that in FIG. 1, thick arrows represent complex signals and thin arrows represent real signals.

In FIG. 1, the first digital data series S11 is input to the first frequency arrangement circuit 11, and the second digital data series S12 is the second frequency arrangement circuit 12.
Is input to The output of each frequency allocation circuit 11 and 12 is
They are supplied to the first and second input terminals of the switch 13 as transmission data for general symbols and transmission data for pilot symbols, respectively, and are selectively switched and output at a predetermined cycle.

The output of the switch 13 is input to the inverse Fourier transform circuit 14, the output of the inverse Fourier transform circuit 14 is input to the guard period adding circuit 15, and the output of the guard period adding circuit 15 is the null symbol insertion circuit 16. To the quadrature modulation circuit 17 and the output of the quadrature modulation circuit 17 is output as an IF band signal S19.

Here, the second frequency arrangement circuit 12 is connected with an arrangement control circuit 18 for changing the set of subcarriers corresponding to the second digital data with time.

The operation of the OFDM modulator configured as described above will be described below.

The first frequency arrangement circuit 11 generates the transmission data S13 for general symbols by making the first digital data sequence S11 correspond only to a specific subcarrier and arranging each data in the frequency domain. In addition, the second frequency allocation circuit 12 associates the second digital data sequence S12 with some subcarriers arranged at a predetermined interval among specific subcarriers, and arranges each data in the frequency domain, Transmission data S14 for pilot symbols is generated.

The switch 13 has transmission data S13 for general symbols and transmission data S14 for pilot symbols.
And are switched at a predetermined cycle and output as transmission data S15. The inverse Fourier transform circuit 14 regards the transmission data S15 for one symbol as a signal in the frequency domain and performs an inverse Fourier transform to generate an effective symbol period signal S16.

The guard period adding circuit 15 generates a baseband OFDM signal S17 by copying the rear part of the effective symbol period signal for each symbol and adding it as a guard period signal before the effective symbol period signal. The null symbol insertion circuit 16 inserts a null symbol consisting of 0 signal into the baseband OFDM signal S17 at a predetermined cycle.

The quadrature modulation circuit 17 separates the baseband OFDM signal S18 in which the null symbol is inserted into the real part and the imaginary part, modulates two carriers orthogonal to each other, and
By adding them together, the frequency is converted to the IF band signal S19. IF band signal S1 generated in this way
9 is RF by an up converter not shown.
A band signal is frequency-converted and transmitted and output.

The operation of the first and second frequency arranging circuits 11 and 12 will be described with reference to FIG.
In the following, as an example, the number of points of the inverse Fourier transform is N
fft = 1024, Nsc = 768 points of them are used as subcarriers, and the number of samples in the guard period is Ng = 128 (that is, the number of samples of one symbol is Nsym = Nfft + Ng = 1024 + 128 = 1.
152) is assumed.

FIG. 2A shows the frequency arrangement of the transmission data S11 for general symbols and the time axis waveform of the effective symbol period signal corresponding thereto. Further, FIG. 2B shows the frequency arrangement of the transmission data S12 for pilot symbols and the time-axis waveform of the effective symbol period signal corresponding thereto.

As shown in FIG. 2, the first frequency allocation circuit 11 uses the transmission data S11 for general symbols in the inverse Fourier transform Nfft = 1024 points (-5
12-511), it is arranged so as to correspond to the central Nsc = 768 points (-384 to 383). At this time, the effective symbol period signal S16 is Nfft = 102
It becomes a random waveform consisting of 4 points.

On the other hand, the second frequency arranging circuit 12 sets the transmission data S12 for pilot symbols to a specific interval (here, as an example, among Nsc = 768 points used for arranging transmission data for general symbols). , Np
= 8 points, -384, -376, ..., -8,
0, 8, ..., 376). At this time, the effective symbol period signal S16 is Nfft / Np = 1024/8 =
The same random waveform is repeated every 128 points (every time Ts / Np) Np = 8 times.

However, if the pilot symbol is constructed using only specific subcarriers as described above, in the worst case, the pilot symbol may be lost due to the influence of multipath interference.

Therefore, in the OFDM modulator according to the first embodiment of the present invention, the arrangement control circuit 18 is provided to shift the arrangement of the second frequency arrangement circuit 12 in order, and the above pilot symbol is set to # 0. On the other hand, one that shifts one subcarrier that constitutes a symbol is # 1, one that shifts two is # 2, ..., Np-1 that shifts # 1.
(Np-1) and use them in order. FIG. 3 shows an example of frequency arrangement of pilot symbols according to the first embodiment of the present invention.

At this time, due to the nature of the Fourier transform, #
The time-axis waveform of the pilot symbols of n (n = 1, 2, ..., Np−1) is Nfft / as shown in FIG.
The same random waveform is repeated every Np = 128 points (each time Ts / Np) Np = 8 times, and is multiplied by the complex sine wave exp (j × n × 2πfsc × t). However, j represents an imaginary unit and t represents time.

Further, in the OFDM modulator according to the first embodiment of the present invention, one frame is composed of one pilot symbol and a plurality of general symbols,
A plurality of frames constitutes one super frame. At this time, a null symbol is inserted by the null symbol insertion circuit 16 in FIG. 1 to indicate the delimiter of the superframe. In the following, the number of symbols forming one frame is Nf. FIG. 4 shows an example of a superframe configuration according to the first embodiment of the present invention.

Here, if the average powers of the general symbol and pilot symbol are made equal, the number of subcarriers used by the pilot symbol is as small as 1 / Np, so the amplitude of each subcarrier is multiplied by Np ^1/2. Can be made larger.

Therefore, if the modulation method for each subcarrier in the pilot symbol and the modulation method for each subcarrier in the general symbol are the same, the pilot symbol is more resistant to noise. Alternatively, by setting the modulation method of each subcarrier in the pilot symbol to be more multivalued than the modulation method of each subcarrier in the general symbol, it is possible to mitigate the decrease in transmission rate due to the decrease in the number of subcarriers.

The transmission data for pilot symbols may be of any type, for example, a signal obtained by branching the transmission data for general symbols, a reference signal for equalization processing on the receiving side, or the like.

FIG. 5 is a block circuit diagram showing the structure of the OFDM demodulator according to the first embodiment of the present invention. In FIG. 5, the thick arrow represents a complex signal and the thin arrow represents a real signal. Further, the portions denoted by the same reference numerals as those in FIG. 20 represent the same configurations as those in FIG.

In FIG. 5, the IF band signal S21 is supplied to the first input terminal of the quadrature demodulation circuit 21, and the output S22 of this quadrature demodulation circuit 21 is the first of the guard period removal circuit 22.
To the input terminal of the synchronous reproduction circuit 24.
The output S23 of the guard period removing circuit 22 is supplied to the input end of the Fourier transform circuit 23. The output of the Fourier transform circuit 23 is output as the reception data S24.

On the other hand, the first output S2 of the synchronous reproduction circuit 24
5 is supplied to the second input terminal of the guard period removing circuit 22, and the second output S26 is supplied to the input terminal of the frequency control circuit 25. The output S27 of the frequency control circuit 25 is supplied to the second input terminal of the quadrature demodulation circuit 21.

In the synchronous reproduction circuit 24, the input S22 from the outside is supplied to the first input end of the correlation circuit 32, the input end of the delay circuit 31 and the first input end of the correction amount control circuit 35. The output S31 of the delay circuit 31 is the correlation circuit 3
2 to a second input terminal.

The output S32 of the correlation circuit 32 is supplied to the input end of the timing detection circuit 33 and the first input end of the frequency error detection circuit 34. The first output of the timing detection circuit 33 is output to the outside as the first output S25 of the synchronous reproduction circuit 24, and the second output S33 is the second input end of the frequency error detection circuit 34 and the correction amount control circuit 35. It is supplied to the second input terminal. Output S of frequency error detection circuit 34
34 is supplied to the first input terminal of the adder 36.

The output S35 of the correction amount control circuit 35 is supplied to the second input terminal of the adder 36. The output of the adder 36 is output to the outside as the second output S26 of the synchronous reproduction circuit 24.

FIG. 6 is a block diagram showing the internal structure of the orthogonal demodulation circuit 21 in FIG. In FIG. 6, a first input S21 externally given to the quadrature demodulation circuit 21 is a bandpass filter (hereinafter, referred to as BPF (Band Pass Filter).
r)) is supplied to the input end of 41. The output of the bandpass filter 41 is the first input terminal of the multiplier 42 and the multiplier 4
3 to the first input terminal.

The output of the multiplier 42 is supplied to the input end of a low pass filter (hereinafter referred to as LPF (Low Pass Filter)) 44, and the output of the multiplier 43 is supplied to the input end of an LPF 45. The output of the LPF 44 is analog / digital (hereinafter,
It is supplied to the input terminal of an A / D (Analog to Digital) converter 46. The output of the LPF 45 is supplied to the input terminal of the A / D converter 47.

The output of the A / D converter 46 is the quadrature demodulation circuit 2.
As the real part of the output of 1, the output of the A / D converter 47 is the imaginary part of the output of the quadrature demodulation circuit 21, and is the signal S in the complex number format.
22 and is output to the outside.

On the other hand, the second input S27 given to the quadrature demodulation circuit 21 from the outside is a voltage controlled oscillator (hereinafter, VC).
It is supplied to the input terminal of an O (Voltage Controled Oscilator) 48. The output of the VCO 48 is supplied to the input end of the π / 2 phase shifter 49 and the second input end of the multiplier 42. π /
The output of the 2-phase shifter 49 is supplied to the second input terminal of the multiplier 43.

FIG. 7 is a block circuit diagram showing the internal structure of the correlation circuit 32 in FIG. In FIG. 7, the first input S22 externally given to the correlation circuit 32 is supplied to the first input terminal of the complex multiplier 52. Further, the second input S31 given from the outside to the correlation circuit 32 is supplied to the input end of the complex conjugate circuit 51, and the output of this complex conjugate circuit 51 is supplied to the second input end of the complex multiplier 52. The output of the complex multiplier 52 is supplied to the input terminal of the moving average circuit 53, and the output of the moving average circuit 53 is the correlation circuit 32.
Is output to the outside as an output S32.

FIG. 8 is a timing detection circuit 3 shown in FIG.
3 is a block circuit diagram showing the internal configuration of FIG. In FIG. 8, an input S32 from the outside of the timing detection circuit 33 is separated into a real part and an imaginary part and supplied to the input ends of the squaring circuits 61 and 62, respectively. The outputs of the squaring circuits 61 and 62 are supplied to the first and second input ends of the adder 63, respectively.
The output of the adder 63 is supplied to the input terminal of the peak detection circuit 64 and the second input terminal of the determination circuit 65.

The output of the peak detection circuit 64 is the determination circuit 65.
Is supplied to the first input terminal of. The output of the determination circuit 65 is supplied to the input terminals of the counters 66 and 67. Counter 6
The output of 6 is the first output S25 of the timing detection circuit 33.
Output to the outside. The output of the counter 67 is output to the outside as the second output S33 of the timing detection circuit 33.

FIG. 9 shows the frequency error detection circuit 3 in FIG.
4 is a block circuit diagram showing the internal configuration of FIG. In FIG. 9, the first externally applied to the frequency error detection circuit 34
Input S32 is supplied to the first input terminal of the hold circuit 71, and the second input is supplied to the second input terminal of the hold circuit 71. The output of the hold circuit 71 is supplied to the input end of the phase angle detection circuit 72. The output of the phase angle detection circuit 72 is output to the outside as the output S32 of the frequency error detection circuit 34.

FIG. 10 shows the frequency control circuit 25 shown in FIG.
3 is a block circuit diagram showing the internal configuration of FIG. In FIG. 10, an input S2 externally applied to the frequency control circuit 25
6 is supplied to the input terminal of the coefficient unit 81. The output of the coefficient unit 81 is supplied to the input terminal of the loop filter 82. The output of the loop filter 82 is digital-analog (hereinafter, D /
It is supplied to the input terminal of an A (Digital to Analog) converter 83. The output of the D / A converter 83 is the frequency control circuit 25.
Output S27 to the outside.

FIG. 11 shows the correction amount control circuit 35 shown in FIG.
3 is a block circuit diagram showing the internal configuration of FIG. In FIG. 11, the first input S22 given from the outside to the correction amount control circuit 35 is separated into a real part and an imaginary part, and the square circuit 9
It is supplied to the input terminals of 1, 92. Each squaring circuit 91, 92
Are supplied to the first and second input terminals of the adder 93, respectively. The output of the adder 93 is supplied to the input terminal of the LPF 94. The output of the LPF 94 is supplied to the input terminal of the determination circuit 95. The output of the decision circuit 95 is the first of the counter 96.
Is supplied to the input terminal of

The second input S33 given from the outside to the correction amount control circuit 35 is supplied to the second input end of the counter 96. The output of the counter 96 is supplied to the input terminal of the coefficient multiplier 97. The output of the coefficient unit 97 is output to the outside as the output S35 of the correction amount control circuit 35.

The operation of the OFDM demodulation device configured as described above will be described below.

First, in FIG. 5, the orthogonal demodulation circuit 21
Demodulates the IF band signal S21 frequency-converted by a tuner (not shown) into a baseband OFDM signal S22 using two carriers that are orthogonal to each other. The carrier is generated based on the frequency control signal S27 output by the frequency control circuit 25.

The guard period removing circuit 22 removes the guard period added on the transmitting side from the baseband OFDM signal S22 based on the timing signal S25 output from the synchronous reproducing circuit 24, and extracts the effective symbol period signal S23. . The Fourier transform circuit 23 regards the effective symbol period signal S23 as a signal in the time domain, performs Fourier transform to obtain a signal in the frequency domain, and outputs it as received data S24.

The synchronous reproduction circuit 24 is a baseband OFD.
The timing signal S25 and the frequency error signal S26 are generated by utilizing the periodicity of the pilot symbols included in the M signal S22. The frequency control circuit 25 generates a frequency control signal S27 from the frequency error signal S26.

In the synchronous reproduction circuit 24, the internal delay circuit 31 shifts the baseband OFDM signal S22 to Nff.
t / Np = 1024/8 = 128 samples (time Ts /
Np). Correlation circuit 32 is baseband O
FDM signal S22 and delayed baseband OFDM signal S
The correlation signal S32 of 31 is calculated.

The timing detection circuit 33 uses the correlation signal S32.
The timing signals S25 and S33 are generated by detecting the peak of the amplitude of. Frequency error detection circuit 34
Calculates the phase angle signal S34 based on the timing signal S33. The correction amount control circuit 35 is a baseband OFDM.
From the signal S22 and the timing signal S33 to the correction signal S5
3 is calculated. The adder 36 adds the correction signal S53 to the phase angle signal S34 and outputs it as a frequency error signal S26.

In the orthogonal demodulation circuit 21 shown in FIG. 6, B
The PF 41 extracts only necessary frequency band components from the IF band signal S21. The VCO 48 uses the frequency control signal S27
Output a sine wave based on. π / 2 phase shifter 49 is VC
The phase of the sine wave output by O48 is shifted by π / 2. The multiplier 42 and the multiplier 43 respectively multiply the signals output by the BPF 41 by mutually orthogonal sine waves output by the VCO 48 and the π / 2 phase shifter 49.

The LPFs 44 and 45 are respectively multipliers 42 and
An unnecessary harmonic component is removed from the signal output by 43.
The A / D converters 46 and 47 convert the signals output by the LPFs 44 and 45, respectively, from an analog format to a digital format and output as a baseband OFDM signal S22.

In the correlation circuit 32 shown in FIG. 7, the complex conjugate circuit 51 outputs the complex conjugate signal of the delayed baseband OFDM signal S31. The complex multiplier 52 performs a complex multiplication between the baseband OFDM signal S22 and the output of the complex conjugate circuit 51. The moving average circuit 53 calculates a moving average of the output of the complex multiplier 52, and outputs it as a correlation signal S32. Here, the number of samples used for the moving average is Nfft-N
It is desirable that fft / Np = 1024-1024 / 8 = 896.

In the timing detection circuit 33 shown in FIG. 8, square circuits 61 and 62 calculate the square of the real part and the imaginary part of the correlation signal S32. The adder 63 is a squaring circuit 6
By adding the outputs of 1 and 62, the correlation signal S32
The square of the amplitude of is calculated.

The peak detection circuit 64 outputs a detection signal at the timing when the output of the adder 63 becomes maximum. The determination circuit 65 outputs a reset signal when the detection signal is supplied from the peak detection circuit 64 when the output of the adder 63 is larger than a predetermined threshold value.

The counter 66 has a symbol period, that is, N.
sym = Nfft + Ng Timing signal S every sample
25, and resets its internal value to 0 based on the output of the determination circuit 65. In addition, the counter 67
Outputs the timing signal S33 every frame period, that is, every Nsym × Nf samples.
Resets its internal value to 0 based on the output of

In the frequency error detection circuit 34 shown in FIG. 9, the hold circuit 71 holds the correlation signal S32 every frame period, that is, every Nsym × Nf samples, based on the timing signal S33 synchronized with the frame. The phase angle detection circuit 72 calculates the phase angle of the complex signal output from the hold circuit 71 and outputs it as the phase angle signal S34.

In the frequency control circuit 25 shown in FIG. 10, the coefficient unit 81 applies the predetermined coefficient k to the frequency error signal S26.
Multiply by. The loop filter 82 integrates the output of the coefficient unit 81. The D / A converter 83 converts the output of the loop filter 82 from a digital format to an analog format and outputs it as a frequency control signal S27.

In the correction amount control circuit 35 shown in FIG. 11, the squaring circuits 91 and 92 are baseband OFDs, respectively.
The square of the real part and the imaginary part of the M signal S22 is calculated. Adder 9
3 calculates the square of the amplitude of the baseband OFDM signal S22 by adding the outputs of the squaring circuits 91 and 92.

The LPF 94 removes unnecessary harmonics from the output of the adder 93 to obtain a baseband OFDM signal.
The envelope waveform of the signal S22 is output. The determination circuit 95
By comparing the output of the LPF 95 with a predetermined threshold value, the null symbol inserted at the beginning of the superframe is detected on the transmission side, and a reset signal is output.

The counter 96 counts the cycle Np = 8, and based on the output of the decision circuit 95, its output value n
Is reset to 0 and the frame cycle timing signal S3
The output value n is incremented by 3. Coefficient unit 9
7 is 2π × fsc × Ts / N for the output value n of the counter 96
It is multiplied by p and output as a correction signal S35.

12 (a), (b), (c) and (d) respectively show the baseband OFDM signal S22, the delayed baseband OFDM signal S31 and the correlation signals S32 and Δf when the frequency error Δf = 0. The correlation signal S32 in the case of = Np × fsc / 4 is shown.

As described above, the effective symbol period signal of pilot symbol # 0 is Nfft / Np = 1024 /
8 = 128 points with the same random waveform Np = 8
Repeat times. Therefore, if Δf = 0,
Since the baseband OFDM signal S22 and the delayed baseband OFDM signal S31 in the period 101 of 2 become the same signal, the real part of the correlation signal S32 takes a peak value at the boundary between the pilot symbol # 0 and the general symbol, and becomes imaginary. The part becomes almost 0.

On the other hand, when Δf ≠ 0, the baseband OFDM signal S22 of the period 101 in FIG.
And -2π between the delayed baseband OFDM signal S31
A phase difference of Δf × Ts / Np occurs. Therefore, Δf =
Since the phase difference in the case of Np × fsc / 4 is −π / 2, the real part of the correlation signal S32 is almost 0, and the imaginary part has a peak value at the boundary between the pilot symbol # 0 and the general symbol.

Therefore, by detecting the peak of the amplitude of the correlation signal S32, the boundary between the pilot symbol # 0 and the general symbol can be detected, and by calculating the phase angle of the correlation signal S32 at the boundary of the symbol, The frequency error Δf can be obtained.

As described above, pilot symbol #n
The time axis waveform of (n ≠ 0) is Nfft / N like # 0.
p = 128 points (every time Ts / Np), the same random waveform is repeated Np = 8 times, and the complex sine wave e
xp (j × n × 2πfsc × t) is multiplied.

Therefore, the phase angle calculated as described above is the phase rotation −2πΔf × due to the frequency error Δf.
Phase rotation of Ts / Np by pilot symbol -2π
× n × fsc × Ts / Np is added.

Therefore, in the OFDM demodulator according to the first embodiment of the present invention, the phase rotation due to the pilot symbol is removed from the phase angle S34 calculated by the frequency error detection circuit 34, and only the phase rotation due to the frequency error Δf is extracted. Therefore, the adder 36 controls the correction amount control circuit 3
2π × n × fsc × Ts / Np output by the phase angle S
Add to 34.

At this time, the frequency error signal S26 has a periodicity of Np × fsc with respect to the frequency error Δf. Therefore, the OFDM demodulator according to the first embodiment of the present invention can cope with a frequency error of ± Np × fsc / 2 or less.

In the above description, the rear part of the effective symbol period signal is copied for each symbol and added as a guard period signal before the effective symbol period signal.
Although the baseband OFDM signal S17 is generated, according to the above configuration, the carrier frequency can be synchronized by the correlation processing of the pilot symbols, so that the synchronization operation is substantially performed without adding the guard period signal. There is no problem on the top.

(Second Embodiment) The second embodiment of the present invention will be described below.
An embodiment will be described. The configuration of the OFDM modulator according to this embodiment is such that the arrangement of the second frequency arrangement circuit 12 in the arrangement control circuit 18 in FIG. 1 is temporally changed in a predetermined pattern. The configuration is the same as that of the first embodiment except for unnecessary points, and thus the description of the configuration is omitted.

FIG. 13 shows an example of a superframe structure generated by the OFDM modulator according to the second embodiment of the present invention.

In FIG. 13, unlike the superframe structure in the first embodiment of the present invention shown in FIG. 4, there is no null symbol for indicating the delimiter of the superframe. Instead, in FIG. 13, the arrangement of pilot symbols included in the frames forming the superframe is # 4, # 1, # 2, # 7, # 5, # 3, # 0, #.
6, ... Has a certain predetermined pattern.

FIG. 14 is a block circuit diagram showing the structure of the OFDM demodulator according to the second embodiment of the present invention. It should be noted that in FIG. 14, bold arrows represent complex signals and thin arrows represent real signals. Further, the portions denoted by the same reference numerals as those in FIG. 5 represent the same configurations as those in FIG. Therefore, the description of the same parts as those in FIG. 5 will be omitted.

In FIG. 14, the second output S33 of the timing detection circuit 33 is supplied to the first input terminal of the correction amount control circuit 121. The output S34 of the frequency error detection circuit 34 is supplied to the second input terminal of the correction amount control circuit 121. The output S41 of the correction amount control circuit 121 is the adder 3
6 to the second input terminal.

FIG. 15 shows the correction amount control circuit 1 in FIG.
21 is a block circuit diagram showing an internal configuration of 21. FIG. The output of the pattern generation circuit 133 is supplied to the first input terminal of the matching circuit 134. The second input S34 externally given to the correction amount control circuit 121 is supplied to the input end of the delay circuit 131 and the first input end of the subtractor 132. Delay circuit 1
The output of 31 is supplied to the second input terminal of the subtractor 132.

The output of the subtractor 132 is supplied to the input terminal of the coefficient unit 137. The output of the coefficient unit 137 is the matching circuit 134.
Is supplied to the second input end of the. The output of the matching circuit 134 is supplied to the first input terminal of the counter 135. The first input S33 given from the outside to the correction amount control circuit 121 is supplied to the second input end of the counter 135. The output of the counter 135 is supplied to the input terminal of the look-up table 136. The output of the lookup table 136 is output to the outside as the output S41 of the correction amount control circuit 121.

The operation of the OFDM demodulator having the above configuration will be described below.

First, the correction amount control circuit 121 shown in FIG.
In, the pattern generation circuit 133 generates a signal string determined by a predetermined pattern included in the above-mentioned pilot symbol array. For example, as described above, the arrangement of pilot symbols is # 4, # 1, # 2, # 7, #.
5, # 3, # 0, # 6, ..., -3, 1, 5,
The pilot symbol number of the current frame minus the pilot symbol number immediately before is generated, such as -2, -2, -3, 6, ...

The delay circuit 131 outputs the phase angle signal S34 to 1
The frame period is delayed by Nsym × Nf samples. The subtractor 132 subtracts the delayed phase angle signal from the phase angle signal S34. The coefficient unit 137 multiplies the output of the subtractor 132 by Np / (2π × fsc × Ts).

The matching circuit 134 considers that the beginning of the superframe has been detected when the signal sequence of the predetermined pattern input from the first input end and the signal sequence input from the second input end match, Output a reset signal. At this time, if the number of signals for confirming the coincidence is increased, the stability of the synchronization is improved, but the time until the synchronization is established becomes long. On the contrary, if the number is decreased, the time until the synchronization is established becomes shorter, but the stability of the synchronization is lowered.

The counter 135 counts the number of frames included in the superframe as one cycle.
The output value n is reset to 0 on the basis of the output of the
Is incremented. The lookup table 136 outputs the correction signal S41 corresponding to the output n of the counter 135. At this time, the correction signal S41 is determined by a predetermined pattern included in the above-mentioned pilot symbol array.

The correction signal S4 generated as described above
1 is added by the adder 36 to the output S34 of the frequency error detection circuit 34
By adding and, the frequency error signal S26 is obtained.
At this time, the frequency error signal S26 has a periodicity of Np × fsc with respect to the frequency error Δf, as in the OFDM modulation device according to the first embodiment of the present invention. Therefore, even the OFDM modulation apparatus according to the second embodiment of the present invention can handle a frequency error of ± Np × fsc / 2 or less.

Furthermore, in the second embodiment of the present invention, the delimiter of the superframe can be detected from the frequency information included in the pilot symbol without using a special symbol such as a null symbol. As a result, the transmission rate can be increased as compared with the OFDM transmission method according to the first embodiment.

In the above description, the rear part of the effective symbol period signal is copied for each symbol and the baseband OFDM signal added before the effective symbol period signal is used as the guard period signal. Even with the configuration, since the carrier frequency can be synchronized by the correlation processing of the pilot symbols, there is substantially no problem in the synchronizing operation without adding the guard period signal.

(Other Embodiments) By the way, the first and second embodiments of the present invention described above are disclosed in Japanese Patent Laid-Open No. 7-1.
Conventional OFD as disclosed in Japanese Patent No. 43097
It can also be used in combination with an M demodulator. FIG.
6 and 17 are block circuit diagrams showing such a configuration example. 16 and 17, the same parts as those of FIGS. 14 and 20 are designated by the same reference numerals, and the duplicated description will be omitted here.

In FIG. 16, the frequency error signal S26 in units of fsc is detected and rounded by the synchronous reproduction circuit 111 according to the second embodiment of the present invention (or may be the synchronous reproduction circuit 24 according to the first embodiment). The circuit 143 extracts only the integer part. The frequency error signal S53 thus obtained is fed to the frequency control circuit 2 via the adder 142.
5 to control the carrier frequency to ± fsc / 2
Coarse synchronization can be performed in a range exceeding.

On the other hand, the conventional synchronous reproducing circuit 141
The frequency error signal S52 of ± fsc / 2 or less is detected by and is sent to the frequency control circuit 25 via the adder 142.
By controlling the carrier frequency, fine synchronization in the range of ± fsc / 2 or less can be established.

Therefore, in this embodiment, the frequency error signal S52 obtained by the synchronous reproduction circuit 141 and the rounding circuit 1 are
The frequency error signal S53 obtained at 43 is added to the adder 142.
Then, the complete frequency error signal S54 is obtained.

Therefore, according to the configuration of the above embodiment, the coarse synchronization and the fine synchronization can be performed at the same time, so that the period required for establishing the synchronization can be shortened.

In FIG. 17, a frequency error signal S52 of ± fsc / 2 or less is detected by the conventional synchronous reproduction circuit 141, and the carrier frequency is controlled only by this signal S52 to establish carrier synchronization.

On the other hand, the frequency error signal S2 obtained by the synchronous reproduction circuit 111 according to the second embodiment of the present invention (or may be the synchronous reproduction circuit 24 according to the first embodiment).
6 is rounded by the rounding circuit 152 to an integer unit,
Fourier transform circuit 1 by obtaining unit frequency error signal S53
Send to 51. In this Fourier transform circuit 151, fsc
Based on the unit frequency error signal S53, Nsc received data S24 is selected from Nfft Fourier transform results.
Take out.

That is, even if the carrier error deviation is corrected by using the frequency error signal S52 obtained by the conventional synchronous reproducing circuit 141, the deviation in subcarrier units remains, and the received data extracted by the Fourier transform circuit 151 is The range is off the specified position. As is clear from the above description, this deviation is caused by the frequency error signal S2 obtained by the synchronous reproduction circuit 111 according to the second embodiment of the present invention.
Corresponds to the integer part of 6.

Therefore, in this embodiment, the rounding circuit 1
The reception data extraction range of the Fourier transform circuit 151 is corrected using the frequency error signal S53 in fsc unit obtained by extracting the integer part from the frequency error signal S26 at 52.

Therefore, according to the configuration of the above embodiment, even if there is a frequency error that cannot be removed by the conventional synchronous reproduction, the received data can be accurately extracted,
Substantially, carrier frequency synchronization corresponding to a frequency error of ± fsc / 2 or more can be obtained. In particular, in this embodiment, one of them is controlled by feedforward instead of being fed back in a double manner as in the previous embodiment, so that the configuration and adjustment can be simplified.

In the above, Nfft = 102
4, the case of Nsc = 768, Np = 8, Ng = 128 has been described as an example, but it goes without saying that these values may be other numerical values.

[0135]

As described above, according to the present invention, by utilizing the periodicity of pilot symbols generated on the transmission side, a frequency error of ± fsc / 2 (fsc is a subcarrier frequency interval) or more on the reception side is achieved. It is possible to obtain carrier frequency synchronization corresponding to. At this time, data can be transmitted also in the pilot symbol.

Further, according to the present invention, the influence of multipath interference can be reduced by changing the subcarriers forming the pilot symbol with time.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing a configuration of an OFDM modulator according to a first embodiment of the present invention.

FIG. 2A is a diagram showing a frequency arrangement of general symbols and a time axis waveform in the present invention. FIG. 3B is a diagram showing a frequency arrangement of pilot symbols and a time axis waveform in the present invention.

FIG. 3 is a diagram showing a frequency allocation of pilot symbols in the first embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a super frame according to the first embodiment of the present invention.

FIG. 5 is a block circuit diagram showing a configuration of an OFDM demodulation device according to the first embodiment of the present invention.

6 is a block circuit diagram showing an internal configuration of a quadrature demodulation circuit 21 in FIG.

7 is a block circuit diagram showing an internal configuration of a correlation circuit 32 in FIG.

8 is a block circuit diagram showing an internal configuration of a timing detection circuit 33 in FIG.

9 is a block circuit diagram showing an internal configuration of a frequency error detection circuit 34 in FIG.

10 is a block circuit diagram showing an internal configuration of a frequency control circuit 25 in FIG.

11 is a block diagram showing an internal configuration of a correction amount control circuit 35 in FIG.

FIG. 12 (a) is baseband OFDM in FIG.
The signals S22 and (b) are the delay baseband O in FIG.
The FDM signal S31, (c) is the correlation signal S3 in FIG.
2 (when Δf = 0) and (d) are diagrams showing the correlation signal S32 (when Δf = Np × fsc / 4) in FIG. 5.

FIG. 13 is a diagram showing a configuration of a super frame according to the second embodiment of the present invention.

FIG. 14 is an OFDM according to the second embodiment of the present invention.
The block circuit diagram which shows the structure of a demodulator.

15 is a block circuit diagram showing an internal configuration of a correction amount control circuit 121 in FIG.

FIG. 16 is a block circuit diagram showing the configuration of an OFDM demodulator according to another embodiment of the present invention.

FIG. 17 is a block circuit diagram showing the configuration of an OFDM demodulator according to another embodiment of the present invention.

FIG. 18 is a block circuit diagram showing the basic configuration of an OFDM transmission system.

FIG. 19 is a diagram showing a time-axis waveform of a baseband OFDM signal.

FIG. 20 is a block circuit diagram showing the configuration of a conventional OFDM demodulator.

21A is a baseband OFD shown in FIG.
The M signal S22, (b) is the delayed baseband OFDM signal S91 in FIG. 20, (c) is the correlation signal S92 (when Δf = 0) in FIG. 20, and (d) is the correlation signal S92 (Δf = fsc) in FIG. / 4)).

FIG. 22 is a characteristic diagram showing the relationship between the frequency error Δf and the frequency error signal S52 in the conventional OFDM demodulator.

[Explanation of symbols]

11, 12 ... Frequency placement circuit, 13 ... Switch, 14 ...
Fourier inverse transform circuit, 15 ... Guard period adding circuit, 16
... Null symbol insertion circuit, 17 ... Quadrature modulation circuit, 18 ...
Arrangement control circuit, 21 ... Quadrature demodulation circuit, 22 ... Guard period removal circuit, 23 ... Fourier transform circuit, 24 ... Synchronous reproduction circuit, 25 ... Frequency control circuit, 31 ... Delay circuit, 32 ... Correlation circuit, 33 ... Timing detection circuit , 34 ... Frequency error detection circuit, 35 ... Correction amount control circuit, 36 ... Adder, 41
... band pass filter (BPF), 42, 43 ... multiplier, 44, 45 ... low pass filter (LPF), 46,
47 ... Analog / Digital (A / D) converter, 48 ... Voltage controlled oscillator (VCO), 49 ... .pi. / 2 phase shifter, 51 ...
Complex conjugate circuit, 52 ... Complex multiplier, 53 ... Moving average circuit, 61, 62 ... Square circuit, 63 ... Adder, 64 ... Peak detection circuit, 65 ... Judgment circuit, 66, 67 ... Counter,
71 ... Hold circuit, 72 ... Phase angle detection circuit, 81 ... Coefficient device, 82 ... Loop filter, 83 ... Digital / analog (D / A) converter, 91, 92 ... Square circuit, 93 ... Adder, 94 ... Low-pass filter (LPF), 95 ... Judgment circuit, 96 ... Counter, 97 ... Coefficient unit, 111 ... Synchronous reproduction circuit, 121 ... Correction amount control circuit, 131 ... Delay circuit,
132 ... Subtractor, 133 ... Pattern generator, 134 ... Collation circuit, 135 ... Counter, 136 ... Lookup table, 141 ... Synchronous reproduction circuit, 142 ... Adder, 143
... Rounding circuit, 151 ... Fourier transform circuit, 152 ... Rounding circuit, 161, ... OFDM modulator, 162 ... Transmission line, 1
63 ... OFDM demodulation device, 171 ... Fourier inverse transformation circuit, 172 ... Guard period addition circuit, 173 ... Quadrature modulation circuit, 174 ... Up converter, 181, ... Tuner, 1
82 ... Quadrature demodulation circuit, 183 ... Guard period removal circuit, 1
84 ... Fourier transform circuit, 201 ... Delay circuit, 202 ...
Correlation circuit, 203 ... Timing detection circuit, 204 ... Frequency error detection circuit.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akira Kisota 5-2-8 Akasaka, Minato-ku, Tokyo Inside the next-generation digital television broadcasting system laboratory (72) Inventor Yasuo Harada 5 Akasaka, Minato-ku, Tokyo Next 2-8 Digital Television Broadcasting Systems Laboratory, Inc. (72) Inventor Tomohiro Kimura 5-2 8 Akasaka, Minato-ku, Tokyo Next Generation Digital Television Broadcasting Systems Laboratory, Ltd.

Claims (18)

[Claims] 1. A general symbol is generated by modulating and multiplexing a plurality of subcarriers orthogonal to each other in a first digital data sequence, and the subcarrier that constitutes the general symbol in a second digital data sequence. Among them, a part of subcarriers arranged at a predetermined interval is paired and modulated and multiplexed to generate a pilot symbol, and the general symbol and the pilot symbol are switched at a predetermined cycle and transmitted. Orthogonal frequency division multiplex transmission system. 2. The orthogonal frequency division multiplex transmission system according to claim 1, wherein a set of subcarriers forming the pilot symbol is changed with time. 3. The orthogonal frequency division multiplex transmission system according to claim 2, wherein the sets of subcarriers are shifted in frequency order. 4. The orthogonal frequency division multiplexing transmission system according to claim 2, wherein the set of subcarriers is shifted in a specific pattern order. 5. A first frequency allocation circuit for outputting a first digital data sequence as data for a general symbol in association with a predetermined subcarrier, and a second digital data sequence among the predetermined subcarriers. A second frequency allocation circuit for outputting as pilot symbol data corresponding to a part of subcarriers arranged at intervals of, and general symbol data output from the first and second frequency allocation circuits, and A switch circuit for switching the pilot symbol data at a predetermined cycle and outputting it as transmission data; and a Fourier inverse transform circuit for performing the inverse Fourier transform by regarding the transmission data output from this switch circuit as a signal in the frequency domain. , The output of this inverse Fourier transform circuit is input as a baseband orthogonal frequency division multiplex signal, and two carriers orthogonal to each other are input. And a quadrature modulation circuit that performs quadrature modulation using waves. 6. The arrangement control circuit further comprises, with respect to the second frequency arrangement circuit, an arrangement control circuit for changing a set of subcarriers corresponding to the second digital data with time. An orthogonal frequency division multiplexing modulation device as described. 7. The orthogonal frequency division multiplexing transmission modulation apparatus according to claim 6, wherein the arrangement control circuit shifts the set of subcarriers in frequency order. 8. The orthogonal frequency division multiplexing transmission modulator according to claim 6, wherein the arrangement control circuit shifts the set of subcarriers in a specific pattern order. 9. The output of the inverse Fourier transform circuit is provided between the inverse Fourier transform circuit and the quadrature modulator as an effective symbol period signal, a part of which is copied and used as a guard period signal. 9. The orthogonal frequency division multiplex according to claim 5, further comprising a guard period addition circuit which adds to the effective symbol period signal and outputs to the orthogonal modulation circuit as a baseband orthogonal frequency division multiplex signal. Type modulator. 10. A general symbol is obtained by modulating and multiplexing a plurality of subcarriers orthogonal to each other in a first digital data sequence, and a predetermined one of the subcarriers forming the general symbol in a second digital data sequence. A part of subcarriers arranged at intervals is modulated and multiplexed as a pilot symbol, the general symbol and the pilot symbol are switched at a predetermined cycle to generate transmission data, and the transmission data is orthogonal to each other. A demodulator for demodulating an orthogonal frequency division multiplex signal conforming to an orthogonal frequency division multiplex transmission system in which two carriers are orthogonally modulated and transmitted, wherein the orthogonal frequency division multiplex signal uses two carriers orthogonal to each other. Quadrature demodulation circuit that demodulates to a baseband signal by Fourier transforming the demodulation signal of this quadrature demodulation circuit A Fourier transform circuit for demodulating the data, a delay circuit for delaying the demodulated signal of the quadrature demodulation circuit by a time determined by an effective symbol period and an interval of subcarriers forming the pilot symbol, and a demodulated signal of the quadrature demodulation circuit A correlation circuit for calculating a correlation signal between the demodulation signal delayed by the delay circuit and the frequency error detection circuit for detecting the frequency error of the carrier in the orthogonal demodulation circuit by obtaining the phase angle of the output signal of the correlation circuit. , The phase angle component dependent on the frequency of the set of subcarriers forming the pilot symbol is removed from the output signal of this frequency error detection circuit, and only the phase angle component dependent on the difference in carrier frequency between the transmitting side and the receiving side is removed. And an orthogonal frequency division multiplexing system demodulation device. 11. The delay circuit has a delay time represented by Ts / Np, where Ts is an effective symbol period of an input signal and Np is an interval between subcarriers forming a pilot symbol. Item 11. An orthogonal frequency division multiplex system demodulator. 12. The correlation circuit outputs a complex conjugate signal of a complex number signal output from the delay circuit, and a complex multiplication that multiplies the complex number signal output from the orthogonal demodulation circuit by the complex conjugate signal. And a moving average circuit for obtaining a moving average of the multiplication result of the complex multiplier and outputting the moving average as a correlation signal. 12. Orthogonal frequency division multiplexing demodulation according to any one of claims 10 to 11, apparatus. 13. When the set of pilot carrier subcarriers in the orthogonal frequency division multiplexed signal changes in frequency order with time, the correction circuit detects the number of changes in the set of subcarriers forming the pilot symbol. The orthogonal frequency division multiplexing system demodulator according to claim 10, wherein the phase angle component is removed based on the detection result. 14. When the set of pilot carrier subcarriers in the orthogonal frequency division multiplexed signal changes in a specific pattern order with time, the correction circuit changes the pattern of the set of subcarriers forming the pilot symbol. Is detected, and the phase angle component is removed based on the detection result. The demodulator of the orthogonal frequency division multiplexing system according to any one of claims 10 to 12. 15. A frequency control circuit for controlling a carrier frequency of the quadrature demodulation circuit based on a correction output of the correction circuit.
2. An orthogonal frequency division multiplexing demodulator according to any one of 1. 16. A rounding circuit for rounding a correction output of the correction circuit, and a frequency control circuit for controlling a carrier frequency of the quadrature demodulation circuit based on the correction output of the rounding circuit. Item 15. An orthogonal frequency division multiplex system demodulator according to any one of items 10 to 14. 17. A rounding circuit for rounding a correction output of the correction circuit, wherein the Fourier transform circuit selectively controls a subcarrier to be converted based on the correction output of the rounding circuit. Item 15. An orthogonal frequency division multiplex system demodulator according to any one of items 10 to 14. 18. A timing detection circuit for detecting the symbol timing of the demodulated signal from the output signal of the correlation circuit when a guard period signal is added to the orthogonal frequency division multiplexed signal, and this timing detection circuit detects the symbol timing. 18. A guard period removing circuit that removes a guard period signal from the demodulated signal based on symbol timing, extracts an effective symbol period signal, and outputs the effective symbol period signal to the Fourier transform circuit. An orthogonal frequency division multiplex system demodulator according to the above paragraph.