JPH08102771A - Ofdm synchronization demodulator - Google Patents

Abstract

PURPOSE: To prevent the degradation of pull-in characteristics and jitter characteristics after pull-in. CONSTITUTION: The output of an orthogonal detection circuit 41 is band-limited by LPFs 47 and 48 and then supplied to a frequency error detection circuit 51 and a frequency error is detected. An NCO(numerically controlled oscillator) 45 generates a numerical value for turning the frequency error to '0' and attains frequency synchronization. In such a manner, an AFC loop is constituted in the preceding stage of an FFT circuit 49. Also, a residual frequency error and a phase error included in the output of the FFT circuit 49 are respectively detected by the frequency error, detection circuit 56 and a phase error detection circuit 57. An adder 60 adds the detected frequency error and phase error and controls the numerical value from the NCO 61. Final carrier synchronization is obtained by the AFC loop and a PLL loop constituted in the poststage of the FFT circuit 49. Since the FFT circuit 49 whose delay time is large is not provided inside the two AFC loops and the PLL loop, the pull-in characteristics and the jitter characteristics after the pull-in are improved.

Description

Detailed Description of the Invention

[Object of the Invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an OFDM synchronization demodulation device, and more particularly to an OFDM synchronization demodulation device for obtaining carrier synchronization from an information signal.

[0002]

2. Description of the Related Art In recent years, in the transmission of video signals or audio signals, digital modulation of high quality and high wave number utilization efficiency has been developed. Particularly in mobile communication, orthogonal frequency division multiplexing (hereinafter referred to as OFDM [or
thogonal frequency division multiplex] modulation is being considered.

The OFDM system has already been adopted in European digital audio broadcasting (hereinafter referred to as DAB) systems, and in recent years, digital television (TV) broadcasting using OFDM has also been studied. This OFDM is described in detail in the document "Mobile Digital Audio Broadcasting Using OFDM" (NHK issue, VIEW May 1993) and the like.

OFDM is a system in which transmission digital data is dispersed into a large number (about 256 to 1024) of carriers (hereinafter referred to as subcarriers) which are orthogonal to each other and modulated. In addition to the characteristics that OFDM is less susceptible to multipath interference, OFDM has the advantages of high frequency utilization efficiency and being less prone to interference.

Each subcarrier of OFDM is modulated by symbol data such as QPSK or multilevel QAM. This modulation is performed by an inverse fast Fourier transform (hereinafter, IFFT) circuit, and one symbol (hereinafter, also referred to as an OFDM symbol) of the OFDM modulated wave is obtained by performing an IFFT operation on N pieces of symbol data for each subcarrier. Created.

FIG. 7 shows an OF used in DAB.
FIG. 2 is a block diagram showing a DM demodulator, “Le Floch et
al, "Digital Sound Broadcasting to Mobile Receiver
s ", IEEE Transactios on Consumer Electronics, Vol.3
5, No. 3, pp.493-530 1989. ".

On the transmitting side, the OFDM symbol (O
After the FDM modulated wave is orthogonally modulated, a high frequency signal (RF
Signal) and transmitted. Also, OF transmitted
A guard period for reducing the influence of multipath is added to the DM symbol. In DAB, each subcarrier is QPSK-modulated, and the QPS to be transmitted is transmitted in order to enable differential detection on the receiving side.
The K symbol is differentially encoded in advance.

Such an RF signal is input to the input terminal 1 of FIG. Out-of-band noise is removed from the input RF signal by the BPF 2, amplified by the amplifier 3, and then supplied to the multiplier 4. The multiplier 4 multiplies the RF signal by the local oscillation signal from the local oscillation circuit 5 and frequency-converts it into an intermediate frequency signal (IF signal). Multiplier
The output of 33 is band-limited by the SAW (surface wave) filter 6, amplified by the amplifier 7 to a predetermined amplitude, and then supplied to the multipliers 8 and 9.

A local oscillation signal having a phase of 0 degree or 90 degrees is supplied from a local oscillation circuit 10 to each of the multipliers 8 and 9 constituting the quadrature detection circuit. The multipliers 8 and 9 perform quadrature detection by multiplying the IF signal from the amplifier 7 and the local oscillation signal, and convert into a baseband OFDM symbol. The outputs of the multipliers 8 and 9 are converted into digital signals by the A / D converters 11 and 12 and then input to the FFT circuit 13.

The FFT circuit 13 Fourier-transforms only the signals of the input OFDM symbol in the effective symbol period excluding the guard period. Thereby, the symbol data of each subcarrier is demodulated. The output of the FFT circuit 13 is
The signal is input to the differential demodulation (delay detection) circuit 14. As described above, the transmitted QPSK symbol has been differentially encoded in advance, and the differential demodulation circuit 14 performs demodulation by obtaining the phase difference from the symbol one time slot before for each carrier. The output of the differential demodulation circuit 14 is the deinterleave circuit 15
After being deinterleaved by, the error correction is performed by the Viterbi decoder 16 and further deinterleaved by the deinterleave circuit 17, which is then decoded into voice data by the CSSR decoder 18.

The demodulation symbol from the differential demodulation circuit 14 is also input to the carrier reproduction circuit 19. The carrier reproducing circuit 19 detects the frequency error of the reproduced carrier based on the demodulation symbol, generates an AFC signal, and supplies it to the oscillator 20. The oscillator 20 outputs an oscillation output having a frequency based on the AFC signal to the local oscillation circuits 5 and 10. In this way, the frequency of the reproduced carrier from the local oscillator circuits 5 and 10 is controlled, and carrier synchronization is achieved.

The outputs of the A / D converters 11 and 12 are AGC.
Also provided to circuit 21. The AGC circuit 21 includes multipliers 8 and 9
The envelope of the input signal is detected based on the sum of the square of the I-axis data and the square of the Q-axis data, and an AGC signal for keeping the envelope constant is generated and supplied to the amplifier 7. The amplifier 7 amplifies the output of the SAW filter 6 based on the AGC signal and supplies a signal of constant amplitude to the quadrature detection circuit.

The outputs of the A / D converters 11 and 12 are also input to the synchronization detection circuit 22. The synchronization detection circuit 22 detects frame synchronization, symbol synchronization, etc. of transmission data. The output of the synchronization detection circuit 22 is given to the timing circuit 23, and OF
An FFT window signal indicating the effective symbol period of the DM symbol is generated and supplied to the FFT circuit 13.

As described above, in the DAB, each subcarrier is modulated by differentially encoded QPSK, and the demodulator demodulates data by performing differential detection. For demodulation, the absolute phase of the demodulated symbol is It is unnecessary. Further, since the differential coded QPSK modulation is adopted, the data can be demodulated if the rotation of the reproduction carrier is within 90 degrees.
That is, in the device shown in FIG. 7, when the carrier is reproduced, only the frequency pull-in should be taken into consideration.
The carrier synchronization is obtained by quadrupling the phase of the reproduced data and comparing, and the configuration is extremely simple.
That is, as shown in the example of FIG. 7, carrier synchronization is obtained by forming an AFC loop that controls the oscillation frequency of the oscillator 20 using the output of the differential demodulation circuit 14.

However, in the differential encoding, when a previous symbol results in a demodulation error, the subsequent symbols cannot be demodulated, and the error easily propagates. Such an error rate characteristic can be improved by adopting synchronous detection. Also, in digital television broadcasting, a method of performing multi-level QAM modulation on each subcarrier is adopted in order to increase the transmission rate. In this case, it is necessary to employ synchronous detection for obtaining an absolute demodulation phase without differential encoding.

As described above, since it is necessary to obtain the absolute phase of the demodulated symbol in the coherent detection, not only the frequency control but also the phase control is necessary in the carrier reproduction. In this case, a PLL loop configuration may be used in which the phase error of the reproduced carrier is detected from the output of the FFT circuit and the oscillation phase of the oscillator 20 is controlled. However, with this configuration,
An FFT circuit is included in the PLL loop. In general,
The FFT circuit demodulates 256 to 1024 OFDM symbols. Therefore, the FFT operation requires a relatively long time. For example, when the PLESSEY FFT processor PDSP16510A is used, 1024
A complex conversion of points requires 3907 clocks of calculation time. As described above, when a circuit having a large delay amount exists in the PLL loop, the feedback control becomes unstable and deterioration of the pull-in characteristic and the frequency jitter characteristic after the pull-in occur.

[0017]

As described above, the conventional O
The PLL loop configured to synchronously demodulate the FDM symbol has a problem that the pull-in characteristic and the jitter characteristic are deteriorated.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an OFDM synchronous demodulation device capable of improving the pull-in characteristic and the jitter characteristic.

[Structure of the Invention]

According to a first aspect of the present invention, an OFDM synchronous demodulation device has an orthogonal frequency division multiplexing modulation signal having an effective symbol period and a guard period having a waveform matching a part of the effective symbol period. A quadrature modulated wave is input, and a quadrature detection means for obtaining an in-phase detection axis signal and a quadrature detection axis signal from the quadrature modulated wave by quadrature detection using a reproduction carrier, and a frequency of the reproduction carrier from an output of the quadrature detection means. A first frequency control loop that detects an error and controls the reproduced carrier based on the detected frequency error; demodulation means that outputs the demodulated symbol data by orthogonal frequency division multiplex demodulation of the output of the orthogonal detection means; The frequency error of the reproduced carrier is detected from the demodulated symbol data, and the carrier error of the demodulated symbol is detected based on the detected frequency error. And a phase lock loop for detecting a phase error of the reproduced carrier from the demodulated symbol data and correcting a carrier error of the demodulated symbol based on the detected phase error. And OFDM according to claim 2 of the present invention
The synchronous demodulation device receives an orthogonal modulated wave of an orthogonal frequency division multiplex modulated signal having an effective symbol period and a guard period having a waveform matching a part of the effective symbol period, and performs the orthogonal detection by orthogonal detection using a reproduction carrier. Quadrature detection means for obtaining an in-phase detection axis signal and a quadrature detection axis signal from a modulated wave, first frequency error detection means for detecting a frequency error of the reproduction carrier from the output of the quadrature detection means, and the first frequency Frequency control means for controlling the frequency of the reproduction carrier based on the frequency error detected by the error detection means, demodulation means for outputting demodulated symbol data by orthogonal frequency division multiplex demodulation of the output of the orthogonal detection means,
Second frequency error detecting means for detecting a frequency error of the reproduced carrier from the demodulated symbol data, phase error detecting means for detecting a phase error of the reproduced carrier from the demodulated symbol data, and second frequency error detecting means Carrier control means for correcting the carrier error of the demodulated symbol data based on the output of the means and the output of the phase error detection means.

[0020]

In the first aspect of the present invention, the quadrature modulation wave of the quadrature frequency division multiplex modulation signal is quadrature detected by the quadrature detection means, and the in-phase detection axis signal and the quadrature detection axis signal are obtained. The first frequency control loop detects a frequency error from the output of the quadrature detection means to obtain frequency synchronization of the reproduced carrier. The output of the quadrature detection means is subjected to orthogonal frequency division multiplex demodulation by the demodulation means to obtain demodulated symbol data.
The second frequency control loop detects a frequency error from the output of the demodulation means and corrects carrier synchronization of the output of the demodulation means,
The phase locked loop detects a phase error from the output of the demodulation means and corrects carrier synchronization of the output of the demodulation means. Since the demodulation means having a large delay time is not included in the first and second frequency control loops and the phase locked loop, the pull-in characteristic and the jitter characteristic are not deteriorated.

In the second aspect of the present invention, the quadrature frequency division multiplexing modulation signal is quadrature detected by the quadrature detection means. This detection output is given to the first frequency error detecting means, and the frequency error of the reproduced carrier is detected. The frequency control means controls the frequency of the reproduction carrier based on the frequency error to obtain frequency synchronization. As a result, the residual frequency error included in the demodulation symbol data from the demodulation means becomes relatively small. The second frequency error detecting means is
A frequency error is detected from the output of the demodulation means. The carrier control means corrects the carrier error of the demodulated symbol data based on the frequency error. Further, the phase error of the reproduced carrier is detected by the phase error detecting means, and the carrier controlling means corrects the carrier error of the demodulated symbol data based on the phase error to finally obtain the carrier synchronization.

[0022]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an OFDM synchronous demodulation device according to the present invention.

The RF (high frequency) signal input to the input terminal 31 is transmitted after the OFDM modulated wave is orthogonally modulated and frequency-converted to the RF band. This RF modulated wave in the RF band is supplied to the BPF 32. The BPF 32 removes out-of-band noise and outputs it to the amplifier 33, and the amplifier 33 amplifies the input signal and outputs it to the multiplier 34. The local oscillator 35 outputs a local oscillation output for frequency-converting the RF band signal to an intermediate frequency band signal to the multiplier 34. The multiplier 34 frequency-converts the OFDM modulated wave by multiplying the output of the amplifier 33 and the local oscillation output, and outputs it to the BPF 36. The BPF 36 band-limits the OFDM modulated wave and outputs it to the variable gain amplifier 37. The gain of the variable gain amplifier 37 is controlled by an envelope detection circuit 40, which will be described later, so that the OFDM modulated wave from the BPF 36 is amplified and output to the A / D converter 38.

The A / D converter 38 converts the output of the variable gain amplifier 37 into a digital signal by using a sampling clock from a clock recovery circuit 39 described later. A / D converter
The output of 38 is supplied to the quadrature detection circuit 41.

The quadrature detection circuit 41 includes multipliers 42, 43 and sin /
It is composed of a cos converter 44 and a numerically controlled oscillator (hereinafter referred to as NCO) 45. The NCO 45 is controlled by the output of a loop filter 46, which will be described later, to convert a numerical value for generating a reproduction carrier of a predetermined frequency into a sin / cos converter.
It is designed to output to 44. sin / cos converter
Reference numeral 44 reproduces an in-phase axis carrier having a predetermined frequency and supplies it to the multiplier 42 based on the numerical value from the NCO 45, and reproduces an orthogonal axis carrier having a predetermined frequency and supplies it to the multiplier 43. The multiplier 42 multiplies the output of the A / D converter 38 by the in-phase axis carrier to obtain the in-phase axis detection output, and the multiplier 43 multiplies the output of the A / D converter 38 by the quadrature axis carrier to detect the quadrature axis detection. Get the output. The outputs of the multipliers 42 and 43 are given to the LPFs 47 and 48, respectively. In this embodiment, since the conversion accuracy is high, the quadrature detection circuit 41 is composed of a digital circuit, but it may be composed of an analog circuit.

The LPFs 47 and 48 limit the real part and imaginary part of the baseband OFDM modulated wave which is the quadrature detection output from the multipliers 42 and 43, respectively, and remove the higher harmonic component F.
Output to the FT circuit 49. The outputs of the LPFs 47 and 48 are also given to the envelope detection circuit 40. The envelope detection circuit 40 detects the envelope of the input signal based on the sum of squares of the outputs (I, Q data) of the LPFs 47 and 48, generates a control signal for keeping the envelope constant, and supplies the control signal to the variable gain amplifier 37. To do. As a result, the variable gain amplifier 37 amplifies the output of the BPF 36 and supplies a signal of constant amplitude to the quadrature detection circuit 41.

Further, in this embodiment, LPFs 47 and 48 are used.
The output of is also supplied to the frequency error detection circuit 51. The frequency error detection circuit 51 detects the frequency error of the reproduction carrier based on the outputs of the LPFs 47 and 48 and outputs it to the loop filter 46. The loop filter 46 smoothes the input signal and outputs it to the NCO 45. By the frequency control loop (AFC loop) for feeding back the output of the frequency error detection circuit 51 to the NCO 45 through the loop filter 46,
The reproduction carrier is frequency-synchronized, and quadrature detection is possible in a state where the frequency shift is relatively small.

The FFT circuit 49 performs OFDM demodulation by performing FFT processing on the input OFDM modulated wave and obtains I and Q data of symbol data. In addition, OF
A guard period for reducing the influence of multipath is added to the DM modulated wave, and the FFT circuit 49 is adapted to perform FFT processing only on the signal in the effective symbol period excluding the guard period. . The output of the FFT circuit 49 is input to the complex multiplier 50 for synchronous detection. The complex multiplier 50 is adapted to synchronously detect symbol data by multiplication with the reproduced carrier from the sin / cos converter 55 and output demodulated symbol data.

By the way, the AF constructed in the quadrature detection circuit 41
Perfect carrier synchronization cannot be obtained only by the C loop. The residual frequency error and the phase error at the time of the quadrature detection by the quadrature detection circuit 41 appear as the phase rotation and the phase error of the constellation of the output of the FFT circuit 49. Therefore, in this embodiment, the final carrier synchronization is obtained by forming a PLL loop in the subsequent stage of the FFT circuit 49 to achieve the phase synchronization. That is, the complex multiplier 50
The output of is supplied to the clock recovery circuit 39, and also to the frequency error detection circuit 56 and the phase error detection circuit 57. The frequency error detection circuit 56 and the phase error detection circuit 57 detect the frequency error and the phase error of the reproduced carrier from the demodulation constellation, respectively. The loop filters 58 and 59 smooth the outputs of the frequency error detection circuit 56 and the phase error detection circuit 57, respectively, and output the smoothed outputs to the adder 60. The adder 60 adds the outputs of the loop filters 58 and 59 and outputs the result to the NCO 61.

An AFC loop is constructed by feeding back the output of the frequency error detection circuit 56 to the NCO 61 through the loop filter 58 and the adder 60, and the output of the phase error detection circuit 57 is passed through the loop filter 59 and the adder 60. NCO61
To form a PLL loop.

Based on the output of the adder 60, the NCO 61 sets a numerical value for reducing the frequency error and the phase error to 0.
The output is output to the cos converter 55. sin /
The cos converter 55 reproduces the in-phase axis carrier and the quadrature axis carrier of a predetermined frequency based on the numerical value from the NCO 61, and gives them to the complex multiplier 50. This allows
The residual frequency error and the phase error of the quadrature detection circuit 41 are corrected to obtain carrier synchronization.

The AFC loop formed by the frequency error detection circuit 56 and the PLL loop formed by the phase error detection circuit 57 are designed to operate after the AFC operation by the AFC loop provided in the quadrature detection circuit 41 is completed. It has become. AFC provided in the quadrature detection circuit 41
The loop completes the pulling action and locks at the predetermined frequency. After this lock, the AFC loop constituted by the frequency error detection circuit 56 starts the AFC operation. It should be noted that this AFC loop performs an auxiliary operation for pulling the frequency to the pull-in range of the PLL loop. After the pull-in of the AFC loop constituted by the frequency error detection circuit 56 is completed, the PLL loop operates to obtain the phase synchronization.

The clock reproducing circuit 39 reproduces the clock from the output of the complex multiplier 50 and outputs it to the A / D converter 38 and the timing circuit 62. Synchronous playback circuit 63
Are supplied with the outputs of the LPFs 47 and 48, detect the frame synchronization and symbol synchronization of the transmission data, and reproduce the synchronization. The timing circuit 62 is adapted to generate clock and timing signals for each circuit based on the output of the synchronous reproduction circuit 63 and the output of the clock reproduction circuit 39.

FIG. 2 is a block diagram showing a specific structure of the frequency error detection circuit 51 in FIG. Further, FIG. 3 is a waveform diagram showing OFDM transmission data to which a guard period is added.

In OFDM, since transmission data is modulated by being dispersed into hundreds to thousands of subcarriers, the modulation symbol rate of each subcarrier becomes extremely low,
The period of one symbol is extremely long. Therefore, the influence of the delay time due to the reflected wave is reduced. Further, as shown in FIG. 3, by setting the guard period before the effective symbol period, it is possible to effectively remove the influence of multipath interference. The guard period is as shown in FIG.
The latter half of the effective symbol period is cyclically copied. Therefore, the signal in the guard period and the signal in the latter half of the effective symbol period have a high correlation. When the delay time of the multipath interference is within the guard period, by demodulating only the signal in the effective symbol period at the time of demodulation, it is possible to prevent intersymbol interference due to delayed adjacent symbols.

The AFC loop of the quadrature detection circuit 41 uses a baseband OFDM modulated wave. As shown in FIG. 3, since the OFDM modulated wave has a waveform similar to random noise, it is difficult to directly detect the frequency error from the OFDM modulated wave. Therefore, in this embodiment, the frequency error of the reproduced carrier is detected by obtaining the correlation between the guard period and the effective symbol period included in the OFDM modulated wave.

In FIG. 2, input terminals 71 and 72 are respectively L
I data and Q data of the baseband OFDM modulated wave are input from the PFs 47 and 48. These I and Q data are supplied to the shift registers 73 and 74, respectively. The shift registers 73 and 74 transfer the I and Q data to the valid symbol period ts, respectively.
It is delayed by just the amount and output to the correlation calculation units 75 and 76. The I data from the input terminal 71 is also input to the correlation calculation units 75 and 76.

The correlation calculator 75 includes a multiplier 81 and a shift register.
82, a subtractor 83, an adder 84 and a latch 85. Since the calculation amount increases when the correlation is calculated by the convolution calculation, the correlation calculation unit 75 detects the correlation by multiplying the two inputs and calculating the moving average. The multiplier 81 multiplies the I data from the shift register 73 and the I data from the input terminal 71 and supplies the result to the shift register 82 and the subtractor 83. The shift register 82 is a multiplier
The output of 81 is delayed by the guard period length and output to the subtractor 83.

The subtractor 83 subtracts the output of the shift register 82 from the output of the multiplier 81 and outputs it to the adder 84. Adder 84
Is output to the latch 85, and the latch 85 latches the output of the adder 84 and outputs it to the adder 84. Adder 84 is a subtractor
The output of 83 is accumulated and output via the latch 85. The output of the correlation calculator 75 is given to the arctangent calculator 77 as a correlation coefficient SII indicating the correlation between the I data and the delayed I data.

The correlation calculator 76 has the same structure as the correlation calculator 75, and is composed of a multiplier 86, a shift register 87, a subtractor 88, an adder 89 and a latch 9. Correlation calculator 7
6 multiplier 86, shift register 87, subtractor 88, adder 89
The latch 90 is composed of a multiplier 81 and a shift register 8 respectively.
2. Similar to the subtracter 83, the adder 84, and the latch 85, the correlation calculator 76 calculates the correlation between the delayed signals of the I data and the Q data, and outputs it as the correlation coefficient SIQ to the arctangent calculation circuit 77. .

The arctangent calculation circuit 77 takes in the correlation coefficients SII and SIQ to obtain the arctangent of SIQ / SII. The latch 78 latches the output of the arctangent operation circuit 77 in symbol synchronization and outputs it as a frequency error signal from the output terminal 79.

Next, the operation of the frequency error detection circuit 51 thus constructed will be described with reference to FIG. FIG.
3 is a timing chart for explaining frequency error detection. 4A shows the I data input to the input terminal 71, and FIG. 4B shows the output of the shift register 73.
FIG. 4C shows the correlation coefficient SII from the correlation calculator 75.

The I data input via the input terminal 71 is given to the correlation calculation units 75 and 76 as it is, and is given by the shift register 73 after being delayed by the effective symbol period. As described above, the OFDM modulated signal has a guard period G at the beginning of each effective symbol period S1, S2 ,.
1, G2, ... Are added (see FIG. 4A). The guard periods G1, G2, ... Are valid symbol periods S1, S2.
, Is a copy of the end period G1 ', G2' ,. Therefore, when the I data from the input terminal 71 is delayed by the effective symbol period, as shown in FIGS. 4A and 4B, the timings of the guard periods G1, G2, ... Of the delay signal and the termination periods G1 ', G2. The timing of ′, ... matches. Since the signal in the guard period is a copy of the signal in the terminal period, the correlation between the I data and its delayed signal is high in this period. In other periods, the I data is a noise signal as shown in FIG.
The correlation between the data and its delayed signal is small.

For this reason, the correlation calculator 75 calculates the correlation between the I data and its delayed signal. The I data and its delayed signal input to the correlation calculator 75 are multiplied by the multiplier 81. The output of the multiplier 81 is input to the shift register 82 and delayed by the guard period length. Subtractor 83 is multiplier 81
And the output of the shift register 82 are obtained. The output of the subtractor 83 is accumulated by the adder 84 and the latch 85. In this way, the current multiplication result of the I data and its delay signal is added, and the previous multiplication result by the guard period length is subtracted to obtain the moving average of the guard period width. The correlation calculator 75 outputs the output of the latch 85 to the arctangent calculator 77 as a correlation coefficient SII between the I data and its delayed signal. On the other hand, the correlation calculation unit 76 has the I from the input terminal 71.
The data and the Q data delayed by the effective symbol period by the shift register 74 are input. The correlation calculation unit 76 obtains the correlation between the delayed signals of the I data and the Q data, and outputs the correlation coefficient SIQ to the arctangent calculation circuit 77.

As shown in FIG. 4 (c), the correlation coefficient SII from the correlation calculation unit 75 gradually increases from the start timing of the end periods G1, G2, ... It becomes a peak at the boundary. Further, since the I data and the Q data are signals whose phases are shifted by 90 degrees on the complex plane and have no mutual correlation,
In this case, the correlation coefficient SIQ between the delayed signal of I data and Q data becomes a value near 0.

By the way, the correlation coefficient SII shown in FIG.
Is an ideal demodulation with carrier synchronization. On the other hand, when carrier synchronization is not established, the detection output phase in quadrature detection rotates, and the correlation coefficient may not increase even in the termination period. For example, when the frequency error Δf of the reproduced carrier is fs / 4 (fs is the frequency difference between adjacent subcarriers),
Since the phase is rotated by 90 degrees in the effective symbol period ts, the signal G'has a phase advanced by 90 degrees from the signal G.
Therefore, in this case, the correlation coefficient SII has a value near 0, and the correlation coefficient SIQ has a negative peak at the end timing of the termination period.

That is, the correlation coefficients SII and SIQ at the guard timing are a function of the carrier frequency error Δf, and the arc tangent of SIQ / SII is a signal that crosses 0 at a position of an integral multiple of fs. For this reason, the arctangent calculation circuit 77 calculates the arctangent of SIQ / SII. The output of the arctangent calculation circuit 77 is latched by the latch 78 at the symbol boundary timing and output as a frequency error signal. By using the frequency error signal, the reproduced carrier frequency can be controlled so that the carrier frequency error Δf becomes an integral multiple of fs.

In FIG. 2, the correlation between the I data and its delayed signal and the correlation between the I data and the delayed signal of the Q data are obtained, but the correlation between the Q data and its delayed signal and the Q data and the I signal are obtained. It is clear that the frequency error can be detected by determining the correlation of the data with the delayed signal.

Next, the operation of the embodiment thus constructed will be described.

RF band O input via the input terminal 31
The FDM modulated wave is band-limited by the BPF 32, amplified by the amplifier 33, and then supplied to the multiplier 34. The local oscillator 35 outputs a local oscillation output for frequency-converting the RF band signal to an intermediate frequency band signal to the multiplier 34. The multiplier 34 frequency-converts the OFDM modulated wave by multiplying the output of the amplifier 33 and the local oscillation output to perform variable gain amplifier 37.
Output to. The OFDM modulated wave is amplified by the variable gain amplifier 37 and given to the A / D converter 38. OFD
The M modulated wave is converted into a digital signal by the A / D converter 38 and supplied to the multipliers 42 and 43 of the quadrature detection circuit 41.

The multiplier 42 obtains the in-phase axis detection output by multiplication with the in-phase axis reproduction carrier from the sin / cos converter 44 and outputs it to the LPF 47, and the multiplier 43 multiplies with the orthogonal axis reproduction carrier to obtain the quadrature axis detection signal. Obtains output and outputs to LPF48. In this way, the quadrature detection circuit 41 obtains I data and Q data of the baseband OFDM modulated wave.

In-phase detection axis output from the quadrature detection circuit 41 (I
Data) and quadrature detection axis output (Q data) are LP
After being band-limited by F47 and F48, it is supplied to the FFT circuit 49. On the other hand, the I and Q data from the LPFs 47 and 48 are also given to the frequency error detection circuit 51. The frequency error detection circuit 51 generates the frequency error signal indicating the frequency error of the reproduced carrier by obtaining the correlation between the I data and its delayed signal and the correlation between the I data and the delayed signal of the Q data, and the loop error detection circuit 51 Output to 46. The frequency error signal is smoothed by the loop filter 46 and supplied to the NCO 45. The NCO 45 generates a numerical value for reducing the frequency error to 0 based on the frequency error signal, and the sin / cos
Output to the converter 44. With this AFC loop, si
The frequencies of the in-phase axis carrier and the quadrature axis carrier from the n / cos converter 44 are controlled to achieve frequency synchronization.

The FFT circuit 49 receives the input LPFs 47 and 48.
Of the I and Q data from, only the signal in the effective symbol period is Fourier transformed. Thereby, the symbol data of each subcarrier is demodulated. The demodulated symbol from the FFT circuit 49 is given to the complex multiplier 50, is synchronously detected, and demodulated symbol data is output.

At this point, the frequency pulling operation of the AFC loop formed in the quadrature detection circuit 41 is locked, but perfect carrier synchronization is not achieved. The FFT circuit 49 detects the residual frequency error and the phase error of the quadrature detection circuit 41.
It appears as a phase rotation and a phase error of the output constellation, and a frequency error detection circuit 56 and a phase error detection circuit 57.
Respectively detect the frequency error and the phase error of the reproduced carrier from the output of the complex multiplier 50.

The frequency error from the frequency error detection circuit 56 is smoothed by the loop filter 58 and then supplied to the NCO 61 via the adder 60. As a result, the NCO 61 generates a numerical value for reducing the frequency error of the reproduced carrier to 0 and outputs it to the sin / cos converter 55. This controls the carrier frequency supplied to the complex multiplier 50,
The frequency is pulled up to the pull-in range of the PLL loop formed by the phase error detection circuit 57.

The phase error signal from the phase error detection circuit 57 is smoothed by the loop filter 59 and then given to the adder 60, added to the frequency error signal from the loop filter 58, and supplied to the NCO 61. With this PLL loop, the NCO 61 generates a numerical value for making the frequency error and the phase error of the reproduced carrier zero, and the NCO 61 performs the sin / cos converter conversion.
Output to 55. Thus, carrier synchronization is finally achieved.

As described above, in this embodiment, the fact that the guard period is a copy of the end period of the effective symbol period is used to make quadrature detection output, that is, I data before FFT demodulation and its delayed signal. The frequency error of the reproduction carrier is detected and the frequency synchronization of the reproduction carrier is obtained by obtaining the correlation between the reproduction carrier and the delay signal of the I data and the Q data. The AFC loop can be configured in the preceding stage of the FFT circuit 49 without including the FFT circuit 49 in the quadrature detection AFC loop, and the loop delay is minimized to prevent the deterioration of the frequency pull-in characteristic and the jitter characteristic after the pull-in. ing. Further, when the frequency error in the quadrature detection circuit 41 is large, the constellation of the output of the FFT circuit 49 is deteriorated, but the residual frequency error after the frequency pull-in of the AFC loop configured in the quadrature detection circuit 41 is small. , The output of the FFT circuit 49 only causes the rotation of the constellation. Therefore, after frequency pulling is performed by the AFC loop configured in the quadrature detection circuit 41, F
By detecting the residual frequency error and the phase error from the output of the FT circuit 49 and controlling the carrier given to the complex multiplier 50 based on these error signals, the carrier synchronization can be finally achieved. An AFC loop and a PLL loop that detect a residual frequency error and a phase error from the output of the FFT circuit 49 to achieve carrier synchronization are provided at the subsequent stage of the FFT circuit 49.
Since the loop can be configured with the minimum loop delay, it is possible to prevent deterioration of the pull-in range and the jitter characteristic after the pull-in.

FIG. 5 is a block diagram showing another embodiment of the present invention. 5, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

In this embodiment, the frequency correction circuit 53 and the adder 52
1 is different from the embodiment of FIG. In this embodiment, F
By feeding back the residual frequency error and the phase error detected by the AFC loop and the PLL loop configured in the subsequent stage of the FT circuit 49 to the AFC loop of the quadrature detection circuit 41, it is possible to remove the frequency shift generated after the carrier synchronization. It is the one.

That is, the frequency error signal from the frequency error detection circuit 51 forming the AFC loop of the quadrature detection circuit 41 is supplied to the loop filter 46 via the adder 52. On the other hand, the output of the adder 60 forming the AFC loop and the PLL loop in the subsequent stage of the FFT circuit 49 is NC.
It is supplied to O61 and also to the frequency correction circuit 53. The frequency correction circuit 53 creates a frequency correction signal based on the residual frequency error and the phase error of the output of the FFT circuit 49 detected by the AFC loop and the PLL loop, and outputs it to the adder 52. The adder 52 adds the output of the frequency error detection circuit 51 and the output of the frequency correction circuit 53 and outputs the result to the loop filter 46.

FIG. 6 is a block diagram showing a specific structure of the frequency correction circuit 53 shown in FIG.

The sign bit of the output of the adder 60 is input to the input terminal 95. This sign bit is supplied to the ROM 97. The ROM 97 outputs a predetermined positive value when the sign bit is 0, and outputs a predetermined negative value when the sign bit is 1. The output of the ROM 97 is output as a frequency correction signal via the terminal 98. By supplying this frequency correction signal to the NCO 45 via the adder 52 and the loop filter 46, the reproduction carrier frequency in the quadrature detection circuit 41 is synchronized. The value stored in the ROM 97 is set to a sufficiently small value so that the PLL loop can follow the output of the FFT circuit 49 when the carrier frequency of the quadrature detection circuit 41 is changed.

In the embodiment constructed as described above,
The frequency error detection circuit 51 detects the frequency error of the I and Q data from the LPFs 47 and 48. This frequency error is applied to the loop filter 46 via the adder 52 and smoothed, and then applied to the NCO 45 to synchronize the frequency of the reproduction carrier. With only the frequency control by the AFC loop, the demodulated output of the FFT circuit 49 contains the residual frequency error and the phase error. Frequency error detection circuit 56 is FF
The residual frequency error is detected based on the demodulation constellation from the T circuit 49. After this residual frequency, it is smoothed by the loop filter 58, and the NCO is passed through the adder 60.
It is supplied to 61 to be frequency synchronized. Further, the phase error detection circuit 57 detects a phase error from the output of the complex multiplier 50 and supplies it to the NCO 61 via the loop filter 59 and the adder 60 to achieve phase synchronization. This establishes carrier synchronization.

Here, it is assumed that a frequency error occurs in the reproduction carrier. The residual frequency error and the phase error detected by the frequency error detection circuit 56 and the phase error detection circuit 57 are added by the adder 60 and supplied to the NCO 61.
It is also supplied to the frequency correction circuit 53. Frequency correction circuit
53 creates a frequency correction signal based on the frequency shift after carrier synchronization. This frequency correction signal has a small positive or negative value corresponding to the frequency shift direction, is added to the frequency error signal by the adder 52, and is supplied to the NCO 45 via the loop filter 46. As a result, a numerical value for making the frequency error 0 is generated from the NCO 45, and carrier synchronization is established again.

Thus, in this embodiment, the FFT
By feeding back the frequency error signal detected in the AFC loop and the PLL loop in the latter stage of the circuit 49 to the AFC loop of the quadrature detection circuit 41, even if the frequency shift occurs after carrier synchronization, the frequency shift can be ensured finally. Can be removed.

In this embodiment, the frequency correction circuit 53 is composed of a ROM, but the frequency of the quadrature detection circuit 41 is detected by using the frequency error signal detected by the AFC loop and the PLL loop at the subsequent stage of the FFT circuit 49. The configuration is not limited to that shown in FIG. 6 as long as a signal for correction can be generated.

[0067]

As described above, according to the present invention, the pull-in characteristic and the jitter characteristic can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an OFDM synchronization demodulation device according to the present invention.

FIG. 2 is a block diagram showing a specific configuration of a frequency error detection circuit 51 in FIG.

FIG. 3 is a waveform diagram showing OFDM transmission data with a guard period added.

FIG. 4 is a timing chart for explaining the operation of the embodiment.

FIG. 5 is a block diagram showing another embodiment of the present invention.

6 is a block diagram showing a specific configuration of a frequency correction circuit 53 in FIG.

FIG. 7 is a block diagram showing an OFDM demodulator.

[Explanation of symbols]

41 ... Synchronous detection circuit, 46, 58, 59 ... Loop filter, 47,
48 ... LPF, 49 ... FFT circuit, 50 ... Complex multiplier, 51, 56
… Frequency error detection circuit, 57… Phase error detection circuit

Continuation of the front page (51) Int.Cl. ⁶ Identification number Reference number within the agency FI Technical indication location H04L 27/22 9297-5K H04L 27/22 C (72) Inventor Yasushi Sugita 8 Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa Address Incorporated company Toshiba Multimedia Technology Laboratories (72) Inventor Makoto Sato 3-3-9 Shimbashi, Minato-ku, Tokyo Inside Toshiba Abu E., Ltd.

Claims (7)

[Claims] 1. An orthogonal modulation wave of an orthogonal frequency division multiplex modulation signal having an effective symbol period and a guard period having a waveform matching a part of the effective symbol period is input, and the orthogonal detection is performed by quadrature detection using a reproduction carrier. Quadrature detection means for obtaining an in-phase detection axis signal and a quadrature detection axis signal from a modulated wave, and a frequency error of the reproduction carrier is detected from the output of the quadrature detection means, and the reproduction carrier is controlled based on the detected frequency error. A first frequency control loop; demodulation means for outputting the demodulated symbol data by performing orthogonal frequency division multiplex demodulation on the output of the quadrature detection means; a frequency error of the reproduced carrier detected from the demodulated symbol data; A second frequency control loop for correcting a carrier error of the demodulated symbol based on an error; The detecting the phase error of the reproduced carrier, the detected OFDM synchronization demodulation apparatus characterized by comprising a phase locked loop for correcting a carrier error of the demodulated symbols based on the phase error from. 2. A quadrature modulated wave of an orthogonal frequency division multiplex modulated signal having an effective symbol period and a guard period having a waveform matching a part of the effective symbol period is input, and the quadrature is detected by quadrature detection using a reproduction carrier. Quadrature detection means for obtaining an in-phase detection axis signal and a quadrature detection axis signal from a modulated wave, first frequency error detection means for detecting a frequency error of the reproduced carrier from the output of the quadrature detection means, and the first frequency Frequency control means for controlling the frequency of the reproduction carrier based on the frequency error detected by the error detection means, demodulation means for outputting demodulated symbol data by orthogonal frequency division multiplex demodulation of the output of the orthogonal detection means, Second frequency error detecting means for detecting a frequency error of the reproduced carrier from demodulated symbol data; Phase error detection means for detecting a phase error of the reproduced carrier, and carrier control means for correcting a carrier error of the demodulated symbol data based on the output of the second frequency error detection means and the output of the phase error detection means. An OFDM synchronous demodulation device comprising: 3. The first frequency error detection means delays the in-phase detection axis signal by the effective symbol period, and the second delay means delays the quadrature detection axis signal by the effective symbol period. Delay means, correlation calculating means for obtaining a correlation coefficient between the in-phase detection axis signal and the quadrature detection axis signal from the quadrature detection means and the output of the first or second delay means, and the correlation coefficient 3. The OFDM synchronous demodulation device according to claim 2, further comprising a calculation unit that detects a frequency error of the reproduction carrier based on the calculation result. 4. The correlation calculating means multiplies the in-phase detection axis signal and the quadrature detection axis signal from the quadrature detection means by the output of the first or second delay means to obtain a moving average and obtain a phase. The OFDM synchronous demodulation device according to claim 3, wherein a relation number is obtained. 5. The calculation unit detects the frequency error of the reproduction carrier by calculating an arc tangent of a ratio of the correlation coefficients calculated by the correlation calculation unit. OFDM synchronous demodulation device. 6. The carrier control means, carrier generation means for generating a carrier based on the output of the second frequency error detection means and the output of the error detection means, and the carrier from the carrier generation means and the demodulation means. 3. The OFDM synchronous demodulation device according to claim 2, further comprising a complex multiplication means for performing a multiplication with the output of the. 7. A correction signal generating means for generating a correction signal based on the output of the second frequency error detecting means and the output of the phase error detecting means, and the correction signal and the output of the first frequency error detecting means. 3. The OFDM synchronous demodulation device according to claim 2, further comprising: an addition unit for adding the value of the above to the frequency control unit to control the frequency of the reproduction carrier.