JPH11205275A - Ofdm reception device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To share plural memories used in a device, to substantially reduce the capacity of the memory and to easily make the device into LSI. SOLUTION: An OFDM(orthogonal frequency division/multiplex) modulation signal is inputted to an orthogonal detection circuit 34 and orthogonally detects it. A frequency error detection circuit 41 detects the frequency errors of a clock and a carrier from orthogonal detection output. An FFT circuit 35 converts orthogonal detection output from a time area into a frequency area. The result is delay-detected between symbols in a delay detection circuit 37. The frequency errors of the clock and the carrier are detected in a frequency error detection circuit 44 from delay detection output. The respective outputs of the frequency error detection circuits 41 and 44 are switched in switch circuits 40 and 45 and the switch control circuit 44. The output of the frequency error detection circuit 41 is selected in the pull-in of an initial stage and the output of the frequency error detection circuit 44 is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an OFDM (Orthogonal Frequency Division Multiplexing) modulation method for receiving a transmission signal.
It relates to a DM receiver.

[0002]

2. Description of the Related Art In recent years, digital modulation systems have been actively developed for transmission of audio signals and video signals. Especially in digital terrestrial broadcasting, it is strong against multipath interference.
Attention has been paid to an orthogonal frequency division multiplexing (hereinafter, OFDM) modulation scheme having features such as high frequency use efficiency.
Hereinafter, a conventional technique related to the present invention will be described.

[0003] For the configuration of an OFDM receiving apparatus, refer to "OFDM receiver".
Development of DM Modem Apparatus ”Technical Report of the Institute of Image Information and Television Engineers
Vol.21, No.44, and PP.13-18. FIG. 7 shows a configuration of a conventional OFDM receiver described in this document.

In FIG. 7, an OFDM modulated wave inputted to an input terminal 11 is tuned by a tuner 12 and converted into an IF signal, and then supplied to a clock supplied from a voltage controlled oscillator 14 by an A / D conversion circuit 13. Is converted into a digital signal. The output of the A / D conversion circuit 13 is converted by a quadrature detection circuit 15 into a baseband in-phase component (I signal) and a quadrature component (Q signal). These signals are FF
After being converted into frequency axis data by an FFT operation by a T (Fast Fourier Transform) circuit 18, an equalization processing circuit 19 cancels transmission line distortion by a sparsely arranged known signal (scattered pilot). The amplitude and phase of each carrier are corrected and output from the output terminals 23 and 24 as synchronous demodulated data.

[0005] The output of the quadrature detection circuit 15 is also supplied to an error detection circuit 17. The error detection circuit 17 detects a clock error signal and a carrier frequency error signal up to ± １ ／ of the carrier interval using the correlation of the guard period. The voltage controlled oscillator 14 is controlled by the clock error signal. Further, the carrier frequency error signal is added to a carrier frequency error signal output from an error detection circuit
16 are used for frequency control.

On the other hand, the output of the FFT circuit 18 is subjected to delay detection by the delay detection circuit 20 and output from output terminals 25 and 26 as differential demodulated data. Further, the delay detection circuit 20
Is input to the error detection circuit 21. The error detection circuit 21 detects a known signal (unmodulated pilot carrier) inserted for each symbol in a specific frequency slot, and compares the detected signal with pilot arrangement information held in the receiver in advance to determine a carrier interval. A unit for detecting a frequency shift is output to the adder 22 as a carrier frequency error signal.

As described above, the OFDM having the above configuration
In the receiving apparatus, the clock and carrier frequency error detection using the correlation of the guard period and the carrier frequency error detection using the known pilot signal arrangement information are used together to establish clock and carrier frequency synchronization. I have.

[0008]

As described above, in the conventional OFDM receiver, the frequency error detection of the clock and the carrier using the correlation of the guard period and the detection of the carrier frequency error using the arrangement information of the known pilot signal are performed. However, the error detection circuit 17 requires one effective symbol delay circuit (memory) for the correlation calculation process in the guard period, and the error detection circuit 21 detects a known signal. Requires memory. further,
The delay detection circuit 20 also requires one symbol of memory.

In the case of the OFDM transmission system, it is considered that about 2000 or about 8000 carriers are used, and a memory capacity for one symbol is required for the number of carriers, so that a large memory capacity is required. In particular, in the case where an LSI is considered in order to reduce the cost of the OFDM receiver, it is important to reduce the memory capacity.

Accordingly, an object of the present invention is to provide an OFDM receiver in which a plurality of memories used in the apparatus are shared, the memory capacity is substantially reduced, and the realization of an LSI is facilitated.

[0011]

To achieve the above object, an OFDM receiving apparatus according to the present invention comprises a quadrature detecting means for inputting an OFDM modulated signal and performing quadrature detection, a clock and a carrier from an output of the quadrature detecting means. First frequency error detecting means for detecting the frequency error of the signal, discrete Fourier transform means for transforming the output of the quadrature detection means from the time domain to the frequency domain by discrete Fourier transform, and delaying the result of the discrete Fourier transform between symbols. Delay detection means for detecting, and second frequency error detection means for detecting clock and carrier frequency errors from the output of the delay detection means,
Switching means for switching between the output of the first frequency error detection means and the output of the second frequency error detection means, wherein the switching means selects the output of the first frequency error detection means in the initial pull-in. Then, switching is performed so as to select the output of the second frequency error detecting means.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. FIG. 1 shows a configuration of an OFDM receiving apparatus according to a first embodiment of the present invention. An OFDM modulated wave input from an input terminal 31 is as follows.
After being tuned by the tuner 32 and converted into an IF signal, A
The digital signal is converted into a digital signal by the clock from the voltage controlled oscillator 49 in the / D conversion circuit 33,
4 is input. In the quadrature detection circuit 34, the signal is detected by a reproduced carrier from a numerically controlled oscillator (NCO) 38 to obtain a baseband OFDM modulated wave. This OFD
The in-phase detection axis output (I signal) and the quadrature detection axis output (Q signal) of the M modulated wave are the real part and the imaginary part of the OFDM modulated wave, respectively.

The O obtained by the quadrature detection circuit 34 is
The FDM modulated wave is converted to an FFT (Fast Fourier Transform) circuit 35
After being converted into frequency axis data by the FFT operation, the equalization processing circuit 36 adjusts the amplitude and phase of each carrier so that transmission line distortion is canceled by a sparsely arranged known signal (scattered pilot signal). The corrected data is output from the output terminals 50 and 51 as synchronous demodulated data.

The output of the FFT circuit 35 is input to the delay detection circuit 37, and the signal subjected to the delay detection is output from the output terminals 52 and 53 as differential demodulated data. The output of the quadrature detection circuit 34 is also supplied to the error detection circuit 41, and a clock frequency error signal and a carrier frequency error signal up to ± 1/2 of the carrier interval are detected by using the correlation of the guard period. The signal is input to one input terminal of the switching circuit 45, and the carrier frequency error signal is
0 is supplied to one input terminal. The error detection circuit 41 outputs an error level signal indicating the magnitude of the clock and carrier frequency errors to the switching control circuit 43.

The output of the delay detection circuit 37 is
4 and a known signal (unmodulated pilot carrier) inserted for each symbol in a specific frequency slot
And detects the frequency shift in carrier interval units by comparing with the pilot carrier arrangement information previously held in the receiver, and further detects the clock frequency error signal and the carrier within the carrier interval from the pilot carrier phase information. The frequency error signal is detected, the clock frequency error signal is supplied to the other input terminal of the switching circuit 45, and the carrier frequency error signal is supplied to the other input terminal of the switching circuit 40. Further, a detection flag indicating the detection state of the pilot carrier is output to the switching control circuit 43.

The output of the FFT circuit 35 is further input to a clock error detection circuit 42, which detects a clock phase error signal and outputs a phase error signal to an adder 46. The switching circuit 40 selects one of the above two carrier frequency error signals based on the switching control signal from the switching control circuit 43 and outputs the selected signal to the loop filter 39.
After that, the signal is input to the frequency control terminal of the NCO 38 to control the frequency of the reproduction carrier.

The switching circuit 45 selects one of the two clock frequency error signals based on the switching control signal from the switching control circuit 43 and outputs it to the adder 46. Switching circuit 4
5 is added to the phase error signal by the adder 46,
D / A conversion circuit 48 smoothed by loop filter 47
Is converted to an analog signal. The converted signal is supplied to the frequency control terminal of the voltage controlled oscillator 49, and the frequency of the clock is controlled.

The clock and carrier frequency pull-in algorithm and the operation of the switching control circuit 43 will now be described with reference to FIG. First, at the time of the initial operation, the error detection circuit 41 operates to perform the correlation detection in the guard period (ST1). A clock and carrier frequency error signal is detected from the correlation operation result (ST2). The clock and carrier frequency error signals are supplied to the switching circuit 4 respectively.
5 and 40, while being smoothed every predetermined period to obtain its absolute value, and input to the switching control circuit 43 as an error level signal. The switching control circuit 43 compares the error level signal with a predetermined value (ST3). If the error level signal is larger than a predetermined value, the switching circuits 40 and 45
Then, the switching control signal is output so that the frequency error signal of the error detection circuit 41 is selected. The clock and carrier frequencies are respectively controlled by the selected frequency error signal (ST4).

When the error level signal is smaller than a predetermined value, the switching circuits 40 and 45 output a switching control signal so that the frequency error signal of the error detecting circuit 44 is selected. Thereafter, switching control is performed by the detection flag of the error detection circuit 44. The error detection circuit 44 detects a pilot carrier (ST5). The frequency error of each carrier interval is detected by comparing the detected frequency slot of the pilot carrier with the frequency slot position of the pilot carrier previously held in the OFDM receiver (ST7).
If the pilot carrier has not been detected for a predetermined period, the detection flag is not detected, and the switching circuits 40 and 45 output a switching control signal so that the frequency error signal of the error detection circuit 41 is selected. If detected, a switching control signal is output so that the frequency error signal of the error detection circuit 44 is selected (ST6). Therefore, in a state where the pilot carrier can be detected, the frequency of the clock and the carrier are thereafter controlled by the frequency error signal of the error detection circuit 44 (ST7, ST7).
ST8).

In this embodiment, the switching of the frequency error signal is controlled by comparing the magnitude of the frequency error signal using the correlation of the guard period with a predetermined value. It is also possible to control to switch between the frequency error signal of the detection circuit 41 and the frequency error signal of the error detection circuit 44.

FIG. 3 is a block diagram showing a configuration example of the error detection circuit 41. The operation will be described in more detail with reference to this. Note that, in FIG. 3, a thick line portion represents a complex signal. The output of the quadrature detection circuit 34 is supplied from the input terminal 4101. The signals are output to correlation operation circuits 4105 and 410
6 and to the delay circuit 4102. The delay circuit 4102 delays the input signal by an effective symbol period and outputs the delayed signal to the complex filters 4103 and 4104.

The complex filter 4103 has a filter characteristic of passing only the positive frequency component, and the complex filter 4104 has a filter characteristic of passing only the negative frequency component. The signals are input to arithmetic circuits 4105 and 4106, respectively. Therefore, the calculation result of the positive frequency component is output from the correlation calculation circuit 4105, and the calculation result of the negative frequency component is output from the correlation calculation circuit 4106.

In the frequency error detection circuit 4106, the output of the correlation operation circuit 4105 and the correlation operation circuit 4106
Are added, and the phase is detected to obtain a frequency error signal of the carrier. Then, the output of the correlation operation circuit 4105 and the output of the correlation operation circuit 4106 are subtracted. An error signal is obtained and output. Further, an error level signal is detected and output according to the magnitude of the absolute value of the clock and carrier frequency error signals.

The error level obtained by frequency error detection circuit 4107 is derived from output terminal 4108, the clock frequency error signal is derived from output terminal 4109, and the carrier frequency error signal is derived from output terminal 4110.

Next, referring to FIG.
4 will be described. It should be noted that also in FIG. 4, the thick line portion represents a complex signal. In FIG. 4, the output of the delay detection circuit 37 is supplied from an input terminal 4401. This signal is supplied to one input terminal of the adder 4402, and the other input terminal is supplied with the output signal of the delay circuit 4403. The output of the adder 4402 is input to the delay circuit 4403. Delay circuit 4403 delays the input signal by one symbol period and outputs the result. Therefore, here, an inter-symbol filter is configured to add an input signal of a predetermined number of symbols to the same carrier between symbols and to output the same. At this time, the amplitude is increased if the pilot carrier is integrated because it is not modulated, but the amplitude is reduced if the integration is performed because the other information carriers have a random phase.

The amplitude judgment circuit 4404 detects the amplitude of the input signal, compares it with a predetermined value, and outputs the comparison result. The correlation detection circuit 4405 detects the correlation between the output signal and the arrangement information from the arrangement information generation circuit 4406 of the pilot carrier. The correlation detection result is obtained by the frequency error detection circuit 4
At 407, a frequency error in carrier interval units is detected from the position of the correlation peak, and an error signal is output to the adder 4408.

The output of the delay detection circuit 37 is also input to a carrier extraction circuit 4409, where only the pilot carrier is output and other information carriers are masked.
The signal is supplied to the phase detection circuit 4410, and the phase is detected. This phase signal is output from the frequency error detection circuit 4411.
The positive frequency slot pilot carrier signal and the negative frequency slot pilot carrier signal are added to the carrier frequency error signal, the positive frequency slot pilot carrier signal and the negative frequency slot pilot The carrier frequency error signal is detected by subtracting the carrier signal, the carrier frequency error signal is output to the other input terminal of the adder 4408, and the clock frequency error signal is output to the output terminal 4414.
The output of the adder 4408 is output to the output terminal 4412 as a carrier frequency error signal.

Further, the frequency error detection circuit 4407 determines whether a pilot carrier has been detected from the correlation calculation result and outputs a detection flag. FIG. 5 is a block diagram showing a configuration of another embodiment of the present invention. This embodiment is a configuration example in which a delay circuit used for frequency error detection using guard correlation and a delay circuit used for delay detection are shared. The description of the parts operating in the same manner as in FIGS. 1 to 4 will be omitted, and only the parts unique to this embodiment will be described.

The output of the quadrature detection circuit 34 is supplied to the error detection circuit 41. The input signal is a correlation operation circuit 4105,
4106 and the switch 54. The other end of the switch 54 receives the output of the FFT circuit 35 and is controlled by the above-described switching control signal.

Here, when the switching circuits 40 and 45 select the frequency error signal detected using the correlation of the guard period, the switch 54 operates so that the output of the quadrature detection circuit 34 is selected. . Switching circuit 4
When the frequency error signal detected using the pilot carrier is selected in 0 and 45, the switch 54 selects the output of the FFT circuit 35. The selected result is delayed by the delay circuit 55 and input to the complex filters 4103 and 4104 of the error detection circuit 41 or the complex conjugate conversion circuit 3702 of the delay detection circuit 37 via the switch 56.

Here, the operation of the switch 56 is
Same as 4. That is, when the switching circuits 40 and 45 select the frequency error signal detected using the correlation of the guard period, the switch 56 uses the error detection circuit 4
The operation is performed so that the first side is turned ON. Switching circuit 4
When the frequency error signal detected using the pilot carrier is selected in 0 and 45, the switch 56 turns on the delay detection circuit 37 side.

By operating as described above, the delay circuit 55
Can be shared by the error detection circuit 41 and the delay detection circuit 37. FIG. 6 is a block diagram showing a configuration of another embodiment of the present invention. This embodiment is an example of a configuration in which a delay circuit used for frequency error detection using guard correlation and a delay circuit used for frequency error detection using pilot carriers are shared. A description of parts that operate in the same manner as in FIGS. 1 to 5 will be omitted, and only parts specific to this embodiment will be described.

One of the switches 54 has a quadrature detection circuit 34
The output of the adder 4402 of the error detection circuit 44 is supplied to the other end. The switch 54 is controlled by the switching control signal, and the switching circuits 40 and 45
In the case of selecting the frequency error signal detected using the correlation of the guard period in the above, that is, the output terminal 4109,
When the output signals 4110 are selected, the switch 54 operates so that the output of the quadrature detection circuit 34 is selected.

When the frequency error signal detected by using the pilot carrier in the switching circuits 40 and 45 is selected, that is, when the output signals of the output terminals 4412 and 4414 are respectively selected, the switch 54 has an adder. The output of 4402 is selected. The selected result is delayed by the delay circuit 55, and the complex filters 4103 and 4104 of the error detection circuit 41 or the amplitude determination circuit 4404 and the adder 44 of the error detection circuit 44 are passed through the switch 56.
02 is input. Here, the switch 56 is also the switch 54
Similarly, when the switching circuits 40 and 45 select the frequency error signal detected by using the correlation of the guard period, the switch 56 operates so that the error detection circuit 41 side is turned on. When the switching circuits 40 and 45 select the frequency error signal detected by using the pilot carrier, the switch 56 has
It becomes N. With this operation, the delay circuit 55 can be shared by the error detection circuit 41 and the error detection circuit 44.

[0035]

As described above, according to the present invention, only one of the clock and carrier frequency error detection circuit using the guard period correlation and the clock and carrier frequency error detection circuit using the pilot carrier operates. By setting the sequence to be performed, the delay circuit can be shared, and the circuit scale of the OFDM receiver can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration as an embodiment of an OFDM receiving apparatus according to the present invention.

FIG. 2 is a flowchart for explaining the operation of the OFDM receiver according to the embodiment.

FIG. 3 is a block diagram showing a specific configuration of an error detection circuit used in the embodiment.

FIG. 4 is a block diagram showing another specific configuration of the error detection circuit used in the embodiment.

FIG. 5 is a block diagram showing a configuration in which a delay circuit in a frequency error detection circuit and a delay detection circuit are shared as another embodiment of the OFDM receiver according to the present invention.

FIG. 6 is a block diagram showing a configuration in which a delay circuit in two frequency error detection circuits is shared as another embodiment of the OFDM receiver according to the present invention.

FIG. 7 is a block diagram showing a configuration of a conventional OFDM transmission / reception device.

[Description of Signs] 32: Tuner, 33: A / D conversion circuit, 34: Quadrature detection circuit, 35: FFT circuit, 136: Equalization processing circuit, 1
37: delay detection circuit, 138: numerically controlled oscillator, 39 ...
Loop filter, 40 switching circuit, 41 error detection circuit, 42 clock error detection circuit, 43 switching control circuit, 44 error detection circuit, 45 switching circuit, 46 adder, 47 loop filter, 48 D / A conversion circuit, 4
9 ... voltage controlled oscillator.

Claims (5)

[Claims] 1. An orthogonal detection means for inputting an OFDM modulated signal and performing orthogonal detection, a first frequency error detection means for detecting a frequency error of a clock and a carrier from an output of the orthogonal detection means, Discrete Fourier transform means for transforming the output from the time domain to the frequency domain by discrete Fourier transform; delay detection means for delay-detecting the result of the discrete Fourier transform between symbols; and clock and carrier frequency errors from the output of the delay detection means. A second frequency error detecting means for detecting an output of the first frequency error detecting means and an output of the second frequency error detecting means. Then, the output is switched to select the output of the first frequency error detecting means, and then to select the output of the second frequency error detecting means. OFDM receiving apparatus according to claim Rukoto. 2. The apparatus according to claim 1, wherein said switching means switches from said first frequency error detecting means to said second frequency error detecting means in accordance with an output of said first frequency error detecting means. An OFDM receiver as described in the above. 3. The OFDM apparatus according to claim 1, wherein said switching means switches from said first frequency error detecting means to said second frequency error detecting means at a predetermined time.
Receiver. 4. The first frequency error detecting means includes delay means for delaying an output of the quadrature detection means for an effective symbol period, and correlation detection for detecting a correlation between an output of the quadrature detection means and an output of the delay means. Means for detecting a frequency error of a clock and a carrier from an output of the correlation detecting means; delay means for delaying one symbol period of the delay detecting means; and the delay of the first frequency error detecting means. The OFDM receiving apparatus according to any one of claims 1 to 3, wherein the OFDM receiving apparatus is shared with a unit. 5. The first frequency error detecting means includes a delay means for delaying an output of the quadrature detecting means for an effective symbol period, and a correlation detecting means for detecting a correlation between an output of the quadrature detecting means and an output of the delay means. Means, and error detecting means for detecting a frequency error of a clock and a carrier from an output of the correlation detecting means, wherein the second frequency error detecting means averages the output of the delay detecting means by a predetermined number of symbols. Averaging means, and error detecting means for detecting a frequency error of a clock and a carrier from an output of the averaging means, wherein the delay means of the first frequency error detecting means and the delay means of the second frequency error detecting means 4. The OFDM receiver according to claim 1, wherein the OFDM receiver shares a memory of the averaging means.