JPH10200446A - Pn sequence trace circuit of spread spectrum demodulator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the scale of a delay discriminator small and also to make a trace characteristic satisfactory. SOLUTION: A clock acquired in a clock oscillator 16 drives a PN sequence oscillator 17 and the oscillator 17 generates a PN sequence. On the other hand, a spread spectrum signal is inputted to a quasi-synchronous detection circuit 12 and applied quasi-synchronous detection, and an LPF 13 extracts a modulation band and inputs it to a delay discriminator 14. The discriminator 14 converts into a pattern that is the level only when a pattern converter 14b performs level change of the PN sequence, a multiplier 14a multiplies it by an inputted receiving signal, an ADC 14c samples the multiplication result through a clock that is delayed by 1/2 chip by a 1/2 delay circuit 14d, and an integrator 14e integrates and makes a delay discrimination output of a received signal. A loop filter 15 converts it into a control signal and makes the PN sequence coincide with the time phase of a received signal by controlling an oscillation frequency of a clock oscillator 16.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum demodulator used, for example, in a receiver of a spread spectrum communication system, and in particular, to a PN (Pseu) included in the received signal.
do-Noise) relates to a PN sequence tracking circuit that tracks a sequence.

[0002]

2. Description of the Related Art As is well known, in a spread spectrum communication system, in order to track a PN sequence on a receiver side, a time delay of a PN sequence included in a received signal is correctly estimated, and the estimated value of the estimated value is calculated. There is a need for a delay discriminator that generates a control signal whose polarity changes in response to advance and delay.

FIG. 4 shows a configuration of a PN sequence tracking circuit using a delay discriminator. 4, an input terminal 11 is supplied with an IF signal obtained by converting a received spread spectrum signal into an intermediate frequency. This IF signal is subjected to coarse synchronization processing in a quasi-synchronous detection circuit 12, and is limited to only a signal in a modulation band by a low-pass filter (LPF) 13, and then supplied to a delay discriminator 14.

On the other hand, a PN sequence generator 17 is driven by a clock generated by a voltage controlled clock oscillator (VCC) 16 and sequentially shifts a predetermined PN code every time a clock is input to generate an n-chip PN sequence. I do. Among them, for example, the PN codes of the (n−2) th and nth chips are supplied to the delay discriminator 14.

[0005] The delay discriminator 14 distributes and supplies an input signal to two correlators 141 and 142, each of which has n−2
The correlation signal is obtained by giving the n-th and n-th PN codes, each correlation result is input to a subtractor 143, and the other is subtracted from one, whereby an error signal e (t) corresponding to the lead / lag of the PN sequence is obtained. obtain. This error signal e (t) is supplied to the loop filter 15.

The loop filter 15 determines the response speed of the PN tracking loop, and receives the input error signal e (t).
Is converted to a control voltage having a different polarity according to the lead / lag. This control voltage is controlled by a voltage-controlled clock oscillator (V
CC) 16.

The voltage controlled clock oscillator 16 controls the oscillation frequency in accordance with the polarity of the control voltage. For example, the frequency is advanced in the case of positive polarity, and is delayed in the case of negative polarity. Therefore, by receiving the control voltage from the loop filter 15, the clock frequency can be controlled so that the error signal e (t) becomes small.

The above configuration is called a delay lock loop system, and the delay discriminator 14 used in this system utilizes the autocorrelation characteristic of the PN sequence shown in FIG.
(Note that in FIG. 5, Δ represents one chip time.
The same shall apply. In this case, one correlator 141 samples at a timing advanced by a predetermined time (corresponding to two chips here) from the reference time point to obtain a correlation value, and the other correlator 142 has a timing delayed by the same time. Sample and determine the correlation value. When the respective correlation values are subtracted, a delay discrimination characteristic shown in FIG. 6 is obtained.

Therefore, an error signal e (t) corresponding to the time delay of the PN sequence is obtained from the subtractor 143, and the driving clock frequency of the PN sequence generator 17 is controlled based on the signal e (t). Thus, the PN sequence included in the input IF signal operates so that the time phases of the PN sequence output from the PN sequence generator coincide with each other, whereby the PN sequence can be tracked.

However, in the above-mentioned method, two correlators are required in the delay discriminator, so that the hardware scale becomes large. Further, if the balance between the gains of the two correlators is lost, a certain error occurs, which has a problem that the tracking performance is adversely affected.

Incidentally, there is another type conventionally called a vibration loop type. The delay discriminator used in this method divides a time period between a period in which the correlator is sampled at a timing advanced from the reference time point by a predetermined time and a period in which the correlator is sampled at a timing delayed by the same time, and calculates the correlation value Is subtracted to obtain the delay discrimination characteristic shown in FIG.

In this system, only one correlator is required in the delay discriminator, so that no balance problem occurs. However, there is a problem that resistance to thermal noise is weak. In addition, there is also a problem that the correlation output is reduced because the data sampling point is shifted from the optimum value.

[0013]

As described above, in the conventional PN sequence tracking circuit of the spread spectrum demodulator, the PN tracking in both the delay lock loop system and the vibration loop system is caused by the problem of the delay discriminator. However, there is a problem that the loop operation becomes unstable and the loop may be disconnected at a low C / N.

An object of the present invention is to solve the above-mentioned problems and to provide a PN sequence tracking circuit of a spread spectrum demodulator in which the hardware size of the delay discriminator is small and the tracking characteristics are good.

[0015]

According to the present invention, there is provided a PN sequence tracking circuit used in a spread spectrum demodulator for tracking a PN sequence included in a received spread spectrum signal. A PN sequence generator for generating a PN sequence in accordance with a drive clock, a clock oscillator for generating the drive clock at an arbitrary frequency, a quasi-synchronous detection circuit for inputting the spread spectrum signal and quasi-synchronous detection; A filter circuit for extracting a modulation band from the detection output of the received signal, and a reception signal advance based on a time phase relationship between a PN sequence included in the spread spectrum signal extracted by the filter circuit and the PN sequence from the PN sequence generator, A delay discriminator for detecting a delay; and a clock frequency for controlling a clock frequency of the clock generator based on an output of the delay discriminator. Control means, wherein the delay discriminator is adapted to set the PN sequence from the PN sequence generator to the level when the level changes in the cycle of the drive clock, and to the reference level when the level does not change. A pattern converter for conversion; a multiplier for multiplying the converted output of the pattern converter by a spread spectrum signal from the filter circuit; a clock delay circuit for shifting the driving clock by ク ロ ッ ク clock; Sampling means for sampling the output of the multiplier at the set clock timing, and the sampling result of this means is used as a delay discrimination output.

In particular, the delay discriminator further comprises an integrator for integrating the sample output of the sampling means to obtain a delay discrimination output. Further, the pattern converter performs pattern conversion to "+1" when the PN sequence changes to a high level at one clock timing, to "0" when it does not change, and to "-1" when it changes to a low level. I do.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to FIGS. However, in FIG. 1, the same parts as those in FIG. 4 are denoted by the same reference numerals, and the duplicate description will be omitted.

FIG. 1 shows the configuration, and the configuration of the delay discriminator 14 is different from that of the conventional configuration shown in FIG. That is, the modulated signal from the low-pass filter 13 input to the delay discriminator 14 is supplied to the multiplier 14a.

On the other hand, the PN code of the n-th chip output from the PN sequence generator 17 is input to the pattern converter 14b. This pattern converter 14b outputs “+” when the PN code changes to the H (high) level at one clock timing.
The pattern is converted to "1", not changed to "0", and changed to L (low) level to "-1". The output is supplied to the multiplier 14a.

The multiplier 14a multiplies the modulation signal by the pattern conversion signal, and the result of the multiplication is supplied to an analog / digital converter (ADC) 14c. This ADC
14c is a signal from the 1/2 chip delay circuit 14d to the VCC 16
Is input as a sample clock, the result of multiplication of the timing is sampled, converted into a digital value, and output.

The output of the ADC 14c is averaged by being integrated by the integrator 14e, and is output to the above-described loop filter 15 as an error signal e (t) corresponding to the advance and delay of the received signal.

In the above configuration, the operation of the delay discriminator 14 will be described below with reference to FIGS. Now, P
Assuming that the PN sequence shown in FIG. 2A is generated from the N-sequence generator 17, the pattern converter 14b that has input the PN sequence changes the PN code to the H (high) level at one clock timing. "+1" when not changed, "0" when not changed, and "-" when changed to L (low) level.
1 ". Therefore, the pattern converter 14
The output of b is as shown in FIG.

Here, since the received signal supplied to the multiplier 14a is substantially synchronized by the quasi-synchronous detection circuit 12, it is input substantially at the timing shown in FIG. For this reason, the multiplier 14a multiplies the pattern conversion signal shown in FIG. 2B by the reception signal shown in FIG. 2C, and the result of the multiplication is a signal waveform as shown in FIG. Become.

On the other hand, the clock obtained by the 1/2 chip delay circuit 14d is a clock obtained by shifting the clock for driving the PN sequence generator 17 by 1/2 chip from the reference point, and is shown in FIG. It's timing. Therefore, the ADC 14c samples the multiplication result shown in FIG. 2D at the timing shown in FIG.

Here, the sample value obtained by the ADC 14c is "0" when the time phase of the received signal and the VCC output coincide, the polarity is negative when the received signal is advanced, and the received signal is delayed. When it is positive. Therefore, the delay dispersion characteristic in this case is as shown in FIG.
The advance and delay of the received signal can be detected with high accuracy.

The output of the ADC 14c is an integrator 1
4e is integrated and averaged. For this reason, even in a low C / N state, it is possible to suppress a large fluctuation due to noise, thereby improving the possibility that a loop is disconnected in a low C / N state.

Therefore, the PN sequence tracking circuit of the spread spectrum demodulator according to the above configuration has a
Since a complicated arithmetic circuit configuration such as a correlator can be omitted, the hardware scale can be significantly reduced. Also, circuit components relatively resistant to thermal noise can be used. Further, the integration process in the delay discriminator allows a low C /
The loop operation at the time of N can be stabilized.

[0028]

As described above, according to the present invention, it is possible to provide a PN sequence tracking circuit of a spread spectrum demodulator in which the hardware size of the delay discriminator is small and the tracking characteristics are good.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram showing a configuration of an embodiment of a PN sequence tracking circuit of a spread spectrum demodulator according to the present invention.

FIGS. 2A and 2B are timing waveform diagrams for explaining the operation of the delay discriminator used in the embodiment, wherein FIG. 2A shows an example of a PN sequence, and FIG. The figure which shows the signal which converted, The figure which shows the received signal (c),
(D) is a diagram illustrating a result of multiplication of the signal of (b) and the signal of (c), and (e) is a diagram illustrating a timing of a clock shifted by チ ッ プ chip from a reference point.

FIG. 3 is a characteristic diagram showing delay discrimination characteristics of the delay discriminator used in the embodiment.

FIG. 4 is a block circuit diagram showing a configuration of a PN sequence tracking circuit based on a delay locked loop system of a conventional spread spectrum demodulator.

FIG. 5 is a characteristic diagram showing an autocorrelation characteristic of a PN sequence in a spread spectrum communication system.

FIG. 6 is a characteristic diagram showing delay discrimination characteristics of a delay discriminator used in the PN sequence tracking circuit shown in FIG.

FIG. 7 is a characteristic diagram showing a delay discrimination characteristic of a delay discriminator used in a vibration loop type PN sequence tracking circuit of a conventional spread spectrum demodulator.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... IF signal input terminal 12 ... Semi-synchronous detection circuit 13 ... Low-pass filter (LPF) 14 ... Delay discriminator 141,142 ... Correlator 143 ... Subtractor 14a ... Multiplier 14b ... Pattern converter 14c ... Analog / digital converter (ADC) 14d ... 1/2 chip 14e ... Integrator 15 ... Loop filter 16 ... Voltage control clock oscillator (VCC) 17 ... PN sequence generator

Claims (3)

[Claims] 1. A P which is used in a spread spectrum demodulator and tracks a PN sequence included in a received spread spectrum signal.
In the N-sequence tracking circuit, a PN sequence generator that generates the PN sequence according to a driving clock; a clock oscillator that generates the driving clock at an arbitrary frequency; A synchronous detection circuit, a filter circuit for extracting a modulation band from a detection output of the circuit, and a time phase of a PN sequence included in the spread spectrum signal extracted by the filter circuit and a PN sequence from the PN sequence generator. A delay discriminator that detects the advance of the received signal from the relationship and a delay, and a clock frequency control unit that controls a clock frequency of the clock generator based on an output of the delay discriminator, wherein the delay discriminator includes: When there is a level change in the PN sequence from the PN sequence generator in the cycle of the drive clock, the level change is made to the level. A pattern converter for converting to a reference level, a multiplier for multiplying a converted output of the pattern converter by a spread spectrum signal from the filter circuit, and a clock delay for shifting the driving clock by ク ロ ッ ク clock. PN sequence tracking of a spread spectrum demodulator, comprising: a circuit; and sampling means for sampling an output of the multiplier at a clock timing shifted by the circuit, wherein a sampling result of the means is output as a delay discrimination output. circuit. 2. The PN sequence tracking circuit of a spread spectrum demodulator according to claim 1, wherein said delay discriminator further comprises an integrator for integrating a sample output of said sampling means to produce a delay discrimination output. . 3. The pattern converter outputs "+1" when the PN sequence changes to a high level at one clock timing.
“0” when not changing, “−” when changing to low level
2. The PN sequence tracking circuit of a spread spectrum demodulator according to claim 1, wherein the PN sequence tracking circuit performs pattern conversion to 1 ".